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[AArch64][nfc] Remove duplicate [us]addl tests (#152664)
in the following list we keep the first test: - extadd[us]_v8i8_i16, test_vaddl_[us]8, [us]addl8h - extadd[us]_v4i16_i32, test_vaddl_[us]16, [us]addl4s - extadd[us]_v2i32_i64, test_vaddl_[us]32, [us]addl2d
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‎llvm/test/CodeGen/AArch64/arm64-neon-3vdiff.ll‎

Lines changed: 2 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -34,42 +34,6 @@ declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>)
3434
declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>)
3535
declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>)
3636

37-
define <8 x i16> @test_vaddl_s8(<8 x i8> %a, <8 x i8> %b) {
38-
; CHECK-LABEL: test_vaddl_s8:
39-
; CHECK: // %bb.0: // %entry
40-
; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
41-
; CHECK-NEXT: ret
42-
entry:
43-
%vmovl.i.i = sext <8 x i8> %a to <8 x i16>
44-
%vmovl.i2.i = sext <8 x i8> %b to <8 x i16>
45-
%add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i
46-
ret <8 x i16> %add.i
47-
}
48-
49-
define <4 x i32> @test_vaddl_s16(<4 x i16> %a, <4 x i16> %b) {
50-
; CHECK-LABEL: test_vaddl_s16:
51-
; CHECK: // %bb.0: // %entry
52-
; CHECK-NEXT: saddl v0.4s, v0.4h, v1.4h
53-
; CHECK-NEXT: ret
54-
entry:
55-
%vmovl.i.i = sext <4 x i16> %a to <4 x i32>
56-
%vmovl.i2.i = sext <4 x i16> %b to <4 x i32>
57-
%add.i = add <4 x i32> %vmovl.i.i, %vmovl.i2.i
58-
ret <4 x i32> %add.i
59-
}
60-
61-
define <2 x i64> @test_vaddl_s32(<2 x i32> %a, <2 x i32> %b) {
62-
; CHECK-LABEL: test_vaddl_s32:
63-
; CHECK: // %bb.0: // %entry
64-
; CHECK-NEXT: saddl v0.2d, v0.2s, v1.2s
65-
; CHECK-NEXT: ret
66-
entry:
67-
%vmovl.i.i = sext <2 x i32> %a to <2 x i64>
68-
%vmovl.i2.i = sext <2 x i32> %b to <2 x i64>
69-
%add.i = add <2 x i64> %vmovl.i.i, %vmovl.i2.i
70-
ret <2 x i64> %add.i
71-
}
72-
7337
define void @test_commutable_vaddl_s8(<8 x i8> %a, <8 x i8> %b, ptr %c) {
7438
; CHECK-LABEL: test_commutable_vaddl_s8:
7539
; CHECK: // %bb.0: // %entry
@@ -87,42 +51,6 @@ entry:
8751
ret void
8852
}
8953

90-
define <8 x i16> @test_vaddl_u8(<8 x i8> %a, <8 x i8> %b) {
91-
; CHECK-LABEL: test_vaddl_u8:
92-
; CHECK: // %bb.0: // %entry
93-
; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
94-
; CHECK-NEXT: ret
95-
entry:
96-
%vmovl.i.i = zext <8 x i8> %a to <8 x i16>
97-
%vmovl.i2.i = zext <8 x i8> %b to <8 x i16>
98-
%add.i = add <8 x i16> %vmovl.i.i, %vmovl.i2.i
99-
ret <8 x i16> %add.i
100-
}
101-
102-
define <4 x i32> @test_vaddl_u16(<4 x i16> %a, <4 x i16> %b) {
103-
; CHECK-LABEL: test_vaddl_u16:
104-
; CHECK: // %bb.0: // %entry
105-
; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
106-
; CHECK-NEXT: ret
107-
entry:
108-
%vmovl.i.i = zext <4 x i16> %a to <4 x i32>
109-
%vmovl.i2.i = zext <4 x i16> %b to <4 x i32>
110-
%add.i = add <4 x i32> %vmovl.i.i, %vmovl.i2.i
111-
ret <4 x i32> %add.i
112-
}
113-
114-
define <2 x i64> @test_vaddl_u32(<2 x i32> %a, <2 x i32> %b) {
115-
; CHECK-LABEL: test_vaddl_u32:
116-
; CHECK: // %bb.0: // %entry
117-
; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s
118-
; CHECK-NEXT: ret
119-
entry:
120-
%vmovl.i.i = zext <2 x i32> %a to <2 x i64>
121-
%vmovl.i2.i = zext <2 x i32> %b to <2 x i64>
122-
%add.i = add <2 x i64> %vmovl.i.i, %vmovl.i2.i
123-
ret <2 x i64> %add.i
124-
}
125-
12654
define void @test_commutable_vaddl_u8(<8 x i8> %a, <8 x i8> %b, ptr %c) {
12755
; CHECK-LABEL: test_commutable_vaddl_u8:
12856
; CHECK: // %bb.0: // %entry
@@ -2926,9 +2854,9 @@ define <8 x i16> @cmplx_mul_combined_re_im(<8 x i16> noundef %a, i64 %scale.coer
29262854
; CHECK-GI-LABEL: cmplx_mul_combined_re_im:
29272855
; CHECK-GI: // %bb.0: // %entry
29282856
; CHECK-GI-NEXT: lsr x9, x0, #16
2929-
; CHECK-GI-NEXT: adrp x8, .LCPI198_0
2857+
; CHECK-GI-NEXT: adrp x8, .LCPI192_0
29302858
; CHECK-GI-NEXT: rev32 v4.8h, v0.8h
2931-
; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI198_0]
2859+
; CHECK-GI-NEXT: ldr q3, [x8, :lo12:.LCPI192_0]
29322860
; CHECK-GI-NEXT: fmov d1, x9
29332861
; CHECK-GI-NEXT: dup v2.8h, v1.h[0]
29342862
; CHECK-GI-NEXT: sqneg v1.8h, v2.8h

‎llvm/test/CodeGen/AArch64/arm64-vadd.ll‎

Lines changed: 0 additions & 91 deletions
Original file line numberDiff line numberDiff line change
@@ -170,51 +170,6 @@ declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>) nounwind
170170
declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
171171
declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
172172

173-
define <8 x i16> @saddl8h(ptr %A, ptr %B) nounwind {
174-
; CHECK-LABEL: saddl8h:
175-
; CHECK: // %bb.0:
176-
; CHECK-NEXT: ldr d0, [x0]
177-
; CHECK-NEXT: ldr d1, [x1]
178-
; CHECK-NEXT: saddl v0.8h, v0.8b, v1.8b
179-
; CHECK-NEXT: ret
180-
%tmp1 = load <8 x i8>, ptr %A
181-
%tmp2 = load <8 x i8>, ptr %B
182-
%tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
183-
%tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
184-
%tmp5 = add <8 x i16> %tmp3, %tmp4
185-
ret <8 x i16> %tmp5
186-
}
187-
188-
define <4 x i32> @saddl4s(ptr %A, ptr %B) nounwind {
189-
; CHECK-LABEL: saddl4s:
190-
; CHECK: // %bb.0:
191-
; CHECK-NEXT: ldr d0, [x0]
192-
; CHECK-NEXT: ldr d1, [x1]
193-
; CHECK-NEXT: saddl v0.4s, v0.4h, v1.4h
194-
; CHECK-NEXT: ret
195-
%tmp1 = load <4 x i16>, ptr %A
196-
%tmp2 = load <4 x i16>, ptr %B
197-
%tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
198-
%tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
199-
%tmp5 = add <4 x i32> %tmp3, %tmp4
200-
ret <4 x i32> %tmp5
201-
}
202-
203-
define <2 x i64> @saddl2d(ptr %A, ptr %B) nounwind {
204-
; CHECK-LABEL: saddl2d:
205-
; CHECK: // %bb.0:
206-
; CHECK-NEXT: ldr d0, [x0]
207-
; CHECK-NEXT: ldr d1, [x1]
208-
; CHECK-NEXT: saddl v0.2d, v0.2s, v1.2s
209-
; CHECK-NEXT: ret
210-
%tmp1 = load <2 x i32>, ptr %A
211-
%tmp2 = load <2 x i32>, ptr %B
212-
%tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
213-
%tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
214-
%tmp5 = add <2 x i64> %tmp3, %tmp4
215-
ret <2 x i64> %tmp5
216-
}
217-
218173
define <8 x i16> @saddl2_8h(<16 x i8> %a, <16 x i8> %b) nounwind {
219174
; CHECK-LABEL: saddl2_8h:
220175
; CHECK: // %bb.0:
@@ -266,52 +221,6 @@ define <2 x i64> @saddl2_2d(<4 x i32> %a, <4 x i32> %b) nounwind {
266221
ret <2 x i64> %add.i
267222
}
268223

269-
define <8 x i16> @uaddl8h(ptr %A, ptr %B) nounwind {
270-
; CHECK-LABEL: uaddl8h:
271-
; CHECK: // %bb.0:
272-
; CHECK-NEXT: ldr d0, [x0]
273-
; CHECK-NEXT: ldr d1, [x1]
274-
; CHECK-NEXT: uaddl v0.8h, v0.8b, v1.8b
275-
; CHECK-NEXT: ret
276-
%tmp1 = load <8 x i8>, ptr %A
277-
%tmp2 = load <8 x i8>, ptr %B
278-
%tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
279-
%tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
280-
%tmp5 = add <8 x i16> %tmp3, %tmp4
281-
ret <8 x i16> %tmp5
282-
}
283-
284-
define <4 x i32> @uaddl4s(ptr %A, ptr %B) nounwind {
285-
; CHECK-LABEL: uaddl4s:
286-
; CHECK: // %bb.0:
287-
; CHECK-NEXT: ldr d0, [x0]
288-
; CHECK-NEXT: ldr d1, [x1]
289-
; CHECK-NEXT: uaddl v0.4s, v0.4h, v1.4h
290-
; CHECK-NEXT: ret
291-
%tmp1 = load <4 x i16>, ptr %A
292-
%tmp2 = load <4 x i16>, ptr %B
293-
%tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
294-
%tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
295-
%tmp5 = add <4 x i32> %tmp3, %tmp4
296-
ret <4 x i32> %tmp5
297-
}
298-
299-
define <2 x i64> @uaddl2d(ptr %A, ptr %B) nounwind {
300-
; CHECK-LABEL: uaddl2d:
301-
; CHECK: // %bb.0:
302-
; CHECK-NEXT: ldr d0, [x0]
303-
; CHECK-NEXT: ldr d1, [x1]
304-
; CHECK-NEXT: uaddl v0.2d, v0.2s, v1.2s
305-
; CHECK-NEXT: ret
306-
%tmp1 = load <2 x i32>, ptr %A
307-
%tmp2 = load <2 x i32>, ptr %B
308-
%tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
309-
%tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
310-
%tmp5 = add <2 x i64> %tmp3, %tmp4
311-
ret <2 x i64> %tmp5
312-
}
313-
314-
315224
define <8 x i16> @uaddl2_8h(<16 x i8> %a, <16 x i8> %b) nounwind {
316225
; CHECK-LABEL: uaddl2_8h:
317226
; CHECK: // %bb.0:

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