[ARM] Add mayRaiseFPException to appropriate instructions and mark all instructions that read/write fpscr rounding bits as doing so (#160698)

Added new register FPSCR_RM to correctly model interactions with
rounding mode control bits of fpscr and to avoid performance regressions
in normal non-strictfp case

This PR is part of the work on adding strict FP support in ARM, which
was previously discussed in #137101.

Author: Varnike

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

@@ -232,6 +232,7 @@ getReservedRegs(const MachineFunction &MF) const {
   markSuperRegs(Reserved, ARM::SP);
   markSuperRegs(Reserved, ARM::PC);
   markSuperRegs(Reserved, ARM::FPSCR);
+  markSuperRegs(Reserved, ARM::FPSCR_RM);
   markSuperRegs(Reserved, ARM::APSR_NZCV);
   if (TFI->isFPReserved(MF))
     markSuperRegs(Reserved, STI.getFramePointerReg());

llvm/lib/Target/ARM/ARMInstrVFP.td

@@ -177,8 +177,9 @@ def Q15 : ARMReg<15, "q15", [D30, D31]>;
 }
 
 // Current Program Status Register.
-// We model fpscr with two registers: FPSCR models the control bits and will be
-// reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV
+// We model fpscr with three registers. FPSCR models the control bits and will be
+// reserved. FPSCR_RM models rounding mode control bits and will be reserved.
+// FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV
 // models the APSR when it's accessed by some special instructions. In such cases
 // it has the same encoding as PC.
 def CPSR       : ARMReg<0,  "cpsr">;
@@ -189,6 +190,9 @@ def FPSCR      : ARMReg<3,  "fpscr">;
 def FPSCR_NZCV : ARMReg<3,  "fpscr_nzcv"> {
   let Aliases = [FPSCR];
 }
+def FPSCR_RM : ARMReg<3,  "fpscr_rm"> {
+  let Aliases = [FPSCR];
+}
 def ITSTATE    : ARMReg<4, "itstate">;
 
 // Special Registers - only available in privileged mode.

llvm/lib/Target/ARM/ARMRegisterInfo.td

@@ -447,7 +447,7 @@ body:             |
     ; CHECK-LABEL: name: test_vnmuls
     ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
-    ; CHECK: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
+    ; CHECK: [[VNMULS:%[0-9]+]]:spr = nofpexcept VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
     ; CHECK: $s0 = COPY [[VNMULS]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
     %0(s32) = COPY $s0
@@ -477,7 +477,7 @@ body:             |
     ; CHECK-LABEL: name: test_vnmuls_reassociate
     ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
-    ; CHECK: [[VNMULS:%[0-9]+]]:spr = VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
+    ; CHECK: [[VNMULS:%[0-9]+]]:spr = nofpexcept VNMULS [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
     ; CHECK: $s0 = COPY [[VNMULS]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
     %0(s32) = COPY $s0
@@ -507,7 +507,7 @@ body:             |
     ; CHECK-LABEL: name: test_vnmuld
     ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
-    ; CHECK: [[VNMULD:%[0-9]+]]:dpr = VNMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
+    ; CHECK: [[VNMULD:%[0-9]+]]:dpr = nofpexcept VNMULD [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
     ; CHECK: $d0 = COPY [[VNMULD]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
     %0(s64) = COPY $d0
@@ -539,7 +539,7 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
     ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2
-    ; CHECK: [[VFNMAS:%[0-9]+]]:spr = VFNMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
+    ; CHECK: [[VFNMAS:%[0-9]+]]:spr = nofpexcept VFNMAS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
     ; CHECK: $s0 = COPY [[VFNMAS]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
     %0(s32) = COPY $s0
@@ -573,7 +573,7 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2
-    ; CHECK: [[VFNMAD:%[0-9]+]]:dpr = VFNMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
+    ; CHECK: [[VFNMAD:%[0-9]+]]:dpr = nofpexcept VFNMAD [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
     ; CHECK: $d0 = COPY [[VFNMAD]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
     %0(s64) = COPY $d0
@@ -607,7 +607,7 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
     ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2
-    ; CHECK: [[VFMSS:%[0-9]+]]:spr = VFMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
+    ; CHECK: [[VFMSS:%[0-9]+]]:spr = nofpexcept VFMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
     ; CHECK: $s0 = COPY [[VFMSS]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
     %0(s32) = COPY $s0
@@ -640,7 +640,7 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:dpr = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:dpr = COPY $d1
     ; CHECK: [[COPY2:%[0-9]+]]:dpr = COPY $d2
-    ; CHECK: [[VFMSD:%[0-9]+]]:dpr = VFMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg
+    ; CHECK: [[VFMSD:%[0-9]+]]:dpr = nofpexcept VFMSD [[COPY2]], [[COPY1]], [[COPY]], 14 /* CC::al */, $noreg, implicit $fpscr
     ; CHECK: $d0 = COPY [[VFMSD]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $d0
     %0(s64) = COPY $d0
@@ -673,7 +673,7 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
     ; CHECK: [[COPY1:%[0-9]+]]:spr = COPY $s1
     ; CHECK: [[COPY2:%[0-9]+]]:spr = COPY $s2
-    ; CHECK: [[VFNMSS:%[0-9]+]]:spr = VFNMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
+    ; CHECK: [[VFNMSS:%[0-9]+]]:spr = nofpexcept VFNMSS [[COPY2]], [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, implicit $fpscr
     ; CHECK: $s0 = COPY [[VFNMSS]]
     ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $s0
     %0(s32) = COPY $s0

llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select-combos.mir

@@ -19,7 +19,7 @@ body:             |
   bb.1:
     ; CHECK-LABEL: name: test_fptosi
     ; CHECK: [[COPY:%[0-9]+]]:spr = COPY $s0
-    ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = VTOSIZS [[COPY]], 14 /* CC::al */, $noreg
+    ; CHECK: [[VTOSIZS:%[0-9]+]]:spr = nofpexcept VTOSIZS [[COPY]], 14 /* CC::al */, $noreg
     ; CHECK: [[COPY1:%[0-9]+]]:gpr = COPY [[VTOSIZS]]
     ; CHECK: $r0 = COPY [[COPY1]]
     ; CHECK: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0