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Automerge: AArch64: Regenerate baseline checks in loop vectorize test (#167926)
2 parents 9df9f61 + d4c8cfe commit 6f9a683

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‎llvm/test/Transforms/LoopVectorize/AArch64/multiple-result-intrinsics.ll‎

Lines changed: 41 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -27,38 +27,38 @@ define void @sincos_f32(ptr noalias %in, ptr noalias writeonly %out_a, ptr noali
2727
; CHECK: [[ENTRY:.*:]]
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; CHECK: [[VECTOR_PH:.*:]]
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; CHECK: [[VECTOR_BODY:.*:]]
30-
; CHECK: [[TMP3:%.*]] = call { <2 x float>, <2 x float> } @llvm.sincos.v2f32(<2 x float> [[WIDE_LOAD:%.*]])
31-
; CHECK: [[TMP4:%.*]] = extractvalue { <2 x float>, <2 x float> } [[TMP3]], 0
32-
; CHECK: [[TMP5:%.*]] = extractvalue { <2 x float>, <2 x float> } [[TMP3]], 1
33-
; CHECK: store <2 x float> [[TMP4]], ptr [[TMP7:%.*]], align 4
34-
; CHECK: store <2 x float> [[TMP5]], ptr [[TMP9:%.*]], align 4
30+
; CHECK: [[TMP6:%.*]] = call { <2 x float>, <2 x float> } @llvm.sincos.v2f32(<2 x float> [[WIDE_LOAD1:%.*]])
31+
; CHECK: [[TMP8:%.*]] = extractvalue { <2 x float>, <2 x float> } [[TMP6]], 0
32+
; CHECK: [[TMP10:%.*]] = extractvalue { <2 x float>, <2 x float> } [[TMP6]], 1
33+
; CHECK: store <2 x float> [[TMP8]], ptr [[TMP12:%.*]], align 4
34+
; CHECK: store <2 x float> [[TMP10]], ptr [[TMP11:%.*]], align 4
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; CHECK: [[FOR_BODY:.*:]]
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; CHECK: [[EXIT:.*:]]
3737
;
3838
; CHECK-ARMPL-LABEL: define void @sincos_f32(
3939
; CHECK-ARMPL-SAME: ptr noalias [[IN:%.*]], ptr noalias writeonly [[OUT_A:%.*]], ptr noalias writeonly [[OUT_B:%.*]]) #[[ATTR0:[0-9]+]] {
40-
; CHECK-ARMPL: [[VECTOR_PH:.*:]]
41-
; CHECK-ARMPL: [[VECTOR_BODY:.*:]]
4240
; CHECK-ARMPL: [[VECTOR_BODY1:.*:]]
43-
; CHECK-ARMPL: [[TMP12:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.sincos.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD:%.*]])
44-
; CHECK-ARMPL: [[TMP13:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.sincos.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD1:%.*]])
45-
; CHECK-ARMPL: [[TMP14:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 0
46-
; CHECK-ARMPL: [[TMP15:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP13]], 0
47-
; CHECK-ARMPL: [[TMP16:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP12]], 1
48-
; CHECK-ARMPL: [[TMP17:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP13]], 1
49-
; CHECK-ARMPL: store <vscale x 4 x float> [[TMP14]], ptr [[TMP19:%.*]], align 4
50-
; CHECK-ARMPL: store <vscale x 4 x float> [[TMP15]], ptr [[TMP22:%.*]], align 4
51-
; CHECK-ARMPL: store <vscale x 4 x float> [[TMP16]], ptr [[TMP24:%.*]], align 4
52-
; CHECK-ARMPL: store <vscale x 4 x float> [[TMP17]], ptr [[TMP27:%.*]], align 4
5341
; CHECK-ARMPL: [[VEC_EPILOG_MIDDLE_BLOCK:.*:]]
5442
; CHECK-ARMPL: [[VEC_EPILOG_SCALAR_PH:.*:]]
43+
; CHECK-ARMPL: [[TMP8:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.sincos.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD:%.*]])
44+
; CHECK-ARMPL: [[TMP9:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.sincos.nxv4f32(<vscale x 4 x float> [[WIDE_LOAD1:%.*]])
45+
; CHECK-ARMPL: [[TMP10:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP8]], 0
46+
; CHECK-ARMPL: [[TMP11:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP9]], 0
47+
; CHECK-ARMPL: [[TMP12:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP8]], 1
48+
; CHECK-ARMPL: [[TMP13:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP9]], 1
49+
; CHECK-ARMPL: store <vscale x 4 x float> [[TMP10]], ptr [[TMP14:%.*]], align 4
50+
; CHECK-ARMPL: store <vscale x 4 x float> [[TMP11]], ptr [[TMP17:%.*]], align 4
51+
; CHECK-ARMPL: store <vscale x 4 x float> [[TMP12]], ptr [[TMP18:%.*]], align 4
52+
; CHECK-ARMPL: store <vscale x 4 x float> [[TMP13]], ptr [[TMP21:%.*]], align 4
5553
; CHECK-ARMPL: [[FOR_BODY1:.*:]]
54+
; CHECK-ARMPL: [[EXIT:.*:]]
55+
; CHECK-ARMPL: [[FOR_BODY:.*:]]
5656
; CHECK-ARMPL: [[CALL:%.*]] = tail call { float, float } @llvm.sincos.f32(float [[IN_VAL:%.*]])
5757
; CHECK-ARMPL: [[EXTRACT_A:%.*]] = extractvalue { float, float } [[CALL]], 0
5858
; CHECK-ARMPL: [[EXTRACT_B:%.*]] = extractvalue { float, float } [[CALL]], 1
5959
; CHECK-ARMPL: store float [[EXTRACT_A]], ptr [[ARRAYIDX2:%.*]], align 4
6060
; CHECK-ARMPL: store float [[EXTRACT_B]], ptr [[ARRAYIDX4:%.*]], align 4
61-
; CHECK-ARMPL: [[EXIT:.*:]]
61+
; CHECK-ARMPL: [[EXIT1:.*:]]
6262
;
6363
entry:
6464
br label %for.body
@@ -100,38 +100,38 @@ define void @sincos_f64(ptr noalias %in, ptr noalias writeonly %out_a, ptr noali
100100
; CHECK: [[ENTRY:.*:]]
101101
; CHECK: [[VECTOR_PH:.*:]]
102102
; CHECK: [[VECTOR_BODY:.*:]]
103-
; CHECK: [[TMP3:%.*]] = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> [[WIDE_LOAD:%.*]])
104-
; CHECK: [[TMP4:%.*]] = extractvalue { <2 x double>, <2 x double> } [[TMP3]], 0
105-
; CHECK: [[TMP5:%.*]] = extractvalue { <2 x double>, <2 x double> } [[TMP3]], 1
106-
; CHECK: store <2 x double> [[TMP4]], ptr [[TMP7:%.*]], align 8
107-
; CHECK: store <2 x double> [[TMP5]], ptr [[TMP9:%.*]], align 8
103+
; CHECK: [[TMP6:%.*]] = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> [[WIDE_LOAD1:%.*]])
104+
; CHECK: [[TMP8:%.*]] = extractvalue { <2 x double>, <2 x double> } [[TMP6]], 0
105+
; CHECK: [[TMP10:%.*]] = extractvalue { <2 x double>, <2 x double> } [[TMP6]], 1
106+
; CHECK: store <2 x double> [[TMP8]], ptr [[TMP12:%.*]], align 8
107+
; CHECK: store <2 x double> [[TMP10]], ptr [[TMP11:%.*]], align 8
108108
; CHECK: [[FOR_BODY:.*:]]
109109
; CHECK: [[EXIT:.*:]]
110110
;
111111
; CHECK-ARMPL-LABEL: define void @sincos_f64(
112112
; CHECK-ARMPL-SAME: ptr noalias [[IN:%.*]], ptr noalias writeonly [[OUT_A:%.*]], ptr noalias writeonly [[OUT_B:%.*]]) #[[ATTR0]] {
113-
; CHECK-ARMPL: [[ENTRY:.*:]]
114-
; CHECK-ARMPL: [[VECTOR_PH:.*:]]
115113
; CHECK-ARMPL: [[VECTOR_BODY:.*:]]
116-
; CHECK-ARMPL: [[TMP12:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.sincos.nxv2f64(<vscale x 2 x double> [[WIDE_LOAD:%.*]])
117-
; CHECK-ARMPL: [[TMP13:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.sincos.nxv2f64(<vscale x 2 x double> [[WIDE_LOAD1:%.*]])
118-
; CHECK-ARMPL: [[TMP14:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 0
119-
; CHECK-ARMPL: [[TMP15:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP13]], 0
120-
; CHECK-ARMPL: [[TMP16:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP12]], 1
121-
; CHECK-ARMPL: [[TMP17:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP13]], 1
122-
; CHECK-ARMPL: store <vscale x 2 x double> [[TMP14]], ptr [[TMP19:%.*]], align 8
123-
; CHECK-ARMPL: store <vscale x 2 x double> [[TMP15]], ptr [[TMP22:%.*]], align 8
124-
; CHECK-ARMPL: store <vscale x 2 x double> [[TMP16]], ptr [[TMP24:%.*]], align 8
125-
; CHECK-ARMPL: store <vscale x 2 x double> [[TMP17]], ptr [[TMP27:%.*]], align 8
126114
; CHECK-ARMPL: [[MIDDLE_BLOCK:.*:]]
127115
; CHECK-ARMPL: [[SCALAR_PH:.*:]]
116+
; CHECK-ARMPL: [[TMP8:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.sincos.nxv2f64(<vscale x 2 x double> [[WIDE_LOAD:%.*]])
117+
; CHECK-ARMPL: [[TMP9:%.*]] = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.sincos.nxv2f64(<vscale x 2 x double> [[WIDE_LOAD1:%.*]])
118+
; CHECK-ARMPL: [[TMP10:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP8]], 0
119+
; CHECK-ARMPL: [[TMP11:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP9]], 0
120+
; CHECK-ARMPL: [[TMP12:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP8]], 1
121+
; CHECK-ARMPL: [[TMP13:%.*]] = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } [[TMP9]], 1
122+
; CHECK-ARMPL: store <vscale x 2 x double> [[TMP10]], ptr [[TMP14:%.*]], align 8
123+
; CHECK-ARMPL: store <vscale x 2 x double> [[TMP11]], ptr [[TMP17:%.*]], align 8
124+
; CHECK-ARMPL: store <vscale x 2 x double> [[TMP12]], ptr [[TMP18:%.*]], align 8
125+
; CHECK-ARMPL: store <vscale x 2 x double> [[TMP13]], ptr [[TMP21:%.*]], align 8
128126
; CHECK-ARMPL: [[FOR_BODY:.*:]]
127+
; CHECK-ARMPL: [[EXIT:.*:]]
128+
; CHECK-ARMPL: [[FOR_BODY1:.*:]]
129129
; CHECK-ARMPL: [[CALL:%.*]] = tail call { double, double } @llvm.sincos.f64(double [[IN_VAL:%.*]])
130130
; CHECK-ARMPL: [[EXTRACT_A:%.*]] = extractvalue { double, double } [[CALL]], 0
131131
; CHECK-ARMPL: [[EXTRACT_B:%.*]] = extractvalue { double, double } [[CALL]], 1
132132
; CHECK-ARMPL: store double [[EXTRACT_A]], ptr [[ARRAYIDX2:%.*]], align 8
133133
; CHECK-ARMPL: store double [[EXTRACT_B]], ptr [[ARRAYIDX4:%.*]], align 8
134-
; CHECK-ARMPL: [[EXIT:.*:]]
134+
; CHECK-ARMPL: [[EXIT1:.*:]]
135135
;
136136
entry:
137137
br label %for.body
@@ -190,11 +190,11 @@ define void @predicated_sincos(float %x, ptr noalias %in, ptr noalias writeonly
190190
; CHECK-ARMPL: [[ENTRY:.*:]]
191191
; CHECK-ARMPL: [[VECTOR_PH:.*:]]
192192
; CHECK-ARMPL: [[VECTOR_BODY:.*:]]
193-
; CHECK-ARMPL: [[TMP15:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.sincos.nxv4f32(<vscale x 4 x float> [[WIDE_MASKED_LOAD:%.*]])
194-
; CHECK-ARMPL: [[TMP16:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP15]], 0
195-
; CHECK-ARMPL: [[TMP17:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP15]], 1
196-
; CHECK-ARMPL: call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> [[TMP16]], ptr align 4 [[TMP13:%.*]], <vscale x 4 x i1> [[TMP9:%.*]])
197-
; CHECK-ARMPL: call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> [[TMP17]], ptr align 4 [[TMP14:%.*]], <vscale x 4 x i1> [[TMP9]])
193+
; CHECK-ARMPL: [[TMP10:%.*]] = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.sincos.nxv4f32(<vscale x 4 x float> [[WIDE_MASKED_LOAD:%.*]])
194+
; CHECK-ARMPL: [[TMP11:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP10]], 0
195+
; CHECK-ARMPL: [[TMP12:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP10]], 1
196+
; CHECK-ARMPL: call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> [[TMP11]], ptr align 4 [[TMP13:%.*]], <vscale x 4 x i1> [[TMP9:%.*]])
197+
; CHECK-ARMPL: call void @llvm.masked.store.nxv4f32.p0(<vscale x 4 x float> [[TMP12]], ptr align 4 [[TMP14:%.*]], <vscale x 4 x i1> [[TMP9]])
198198
; CHECK-ARMPL: [[IF_MERGE:.*:]]
199199
; CHECK-ARMPL: [[FOR_END:.*:]]
200200
;

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