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[AArch64] Treat COPY between cross-register banks as expensive (#167661)
The motivation is to allow passes such as MachineLICM to hoist trivial FMOV instructions out of loops, where previously it didn't do so even when the RHS is a constant. On most architectures, these expensive move instructions have a latency of 2-6 cycles, and certainly not cheap as a 0-1 cycle move.
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -1144,6 +1144,28 @@ static bool isCheapImmediate(const MachineInstr &MI, unsigned BitSize) {
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return Is.size() <= 2;
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}
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// Check if a COPY instruction is cheap.
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static bool isCheapCopy(const MachineInstr &MI, const AArch64RegisterInfo &RI) {
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assert(MI.isCopy() && "Expected COPY instruction");
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const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
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// Cross-bank copies (e.g., between GPR and FPR) are expensive on AArch64,
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// typically requiring an FMOV instruction with a 2-6 cycle latency.
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auto GetRegClass = [&](Register Reg) -> const TargetRegisterClass * {
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if (Reg.isVirtual())
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return MRI.getRegClass(Reg);
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if (Reg.isPhysical())
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return RI.getMinimalPhysRegClass(Reg);
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return nullptr;
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};
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const TargetRegisterClass *DstRC = GetRegClass(MI.getOperand(0).getReg());
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const TargetRegisterClass *SrcRC = GetRegClass(MI.getOperand(1).getReg());
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if (DstRC && SrcRC && !RI.getCommonSubClass(DstRC, SrcRC))
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return false;
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return MI.isAsCheapAsAMove();
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}
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// FIXME: this implementation should be micro-architecture dependent, so a
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// micro-architecture target hook should be introduced here in future.
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bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
@@ -1157,6 +1179,9 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
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default:
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return MI.isAsCheapAsAMove();
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case TargetOpcode::COPY:
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return isCheapCopy(MI, RI);
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case AArch64::ADDWrs:
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case AArch64::ADDXrs:
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case AArch64::SUBWrs:

‎llvm/test/CodeGen/AArch64/licm-regclass-copy.mir‎

Lines changed: 197 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,197 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=early-machinelicm -o - %s | FileCheck %s
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# This test verifies that cross-bank copies (e.g., GPR to FPR, FPR to GPR)
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# are hoisted out of loops by MachineLICM, as they are expensive on AArch64.
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--- |
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declare void @use_float(float)
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declare void @use_int(i32)
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define void @gpr_to_fpr_virtual_copy_hoisted() {
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ret void
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}
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define void @gpr_to_fpr_physical_copy_hoisted() {
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ret void
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}
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define void @fpr_to_gpr_virtual_copy_hoisted() {
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ret void
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}
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...
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---
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name: gpr_to_fpr_virtual_copy_hoisted
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: gpr_to_fpr_virtual_copy_hoisted
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $w0, $w1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY $wzr
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY [[COPY2]]
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:fpr32 = COPY [[COPY1]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32common = PHI [[COPY3]], %bb.0, %5, %bb.2
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; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[PHI]], [[COPY]], implicit-def $nzcv
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; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $s0 = COPY [[COPY4]]
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; CHECK-NEXT: BL @use_float, implicit-def dead $lr, implicit $sp, implicit $s0, implicit-def $sp
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; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[PHI]], 1, 0
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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liveins: $w0, $w1
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%1:gpr32 = COPY $w0
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%0:gpr32 = COPY $w1
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%3:gpr32all = COPY $wzr
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%2:gpr32all = COPY %3:gpr32all
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bb.1:
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%4:gpr32common = PHI %2:gpr32all, %bb.0, %5:gpr32all, %bb.2
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%6:gpr32 = SUBSWrr %4:gpr32common, %1:gpr32, implicit-def $nzcv
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Bcc 1, %bb.3, implicit $nzcv
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B %bb.2
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bb.2:
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%7:fpr32 = COPY %0:gpr32
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$s0 = COPY %7:fpr32
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BL @use_float, implicit-def dead $lr, implicit $sp, implicit $s0, implicit-def $sp
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%8:gpr32sp = ADDWri %4:gpr32common, 1, 0
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%5:gpr32all = COPY %8:gpr32sp
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B %bb.1
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bb.3:
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RET_ReallyLR
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...
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---
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name: gpr_to_fpr_physical_copy_hoisted
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: gpr_to_fpr_physical_copy_hoisted
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $w0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY $wzr
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $wzr
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32common = PHI [[COPY2]], %bb.0, %4, %bb.2
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; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[PHI]], [[COPY]], implicit-def $nzcv
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; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $s0 = COPY [[COPY3]]
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; CHECK-NEXT: BL @use_float, implicit-def dead $lr, implicit $sp, implicit $s0, implicit-def $sp
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; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[PHI]], 1, 0
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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liveins: $w0
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%1:gpr32 = COPY $w0
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%3:gpr32all = COPY $wzr
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%2:gpr32all = COPY %3:gpr32all
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bb.1:
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%4:gpr32common = PHI %2:gpr32all, %bb.0, %5:gpr32all, %bb.2
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%6:gpr32 = SUBSWrr %4:gpr32common, %1:gpr32, implicit-def $nzcv
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Bcc 1, %bb.3, implicit $nzcv
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B %bb.2
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bb.2:
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%7:fpr32 = COPY $wzr
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$s0 = COPY %7:fpr32
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BL @use_float, implicit-def dead $lr, implicit $sp, implicit $s0, implicit-def $sp
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%8:gpr32sp = ADDWri %4:gpr32common, 1, 0
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%5:gpr32all = COPY %8:gpr32sp
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B %bb.1
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bb.3:
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RET_ReallyLR
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...
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---
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name: fpr_to_gpr_virtual_copy_hoisted
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: fpr_to_gpr_virtual_copy_hoisted
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $w0, $s0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32all = COPY $wzr
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY [[COPY2]]
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY1]]
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32common = PHI [[COPY3]], %bb.0, %5, %bb.2
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; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[PHI]], [[COPY]], implicit-def $nzcv
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; CHECK-NEXT: Bcc 1, %bb.3, implicit $nzcv
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; CHECK-NEXT: B %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $w0 = COPY [[COPY4]]
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; CHECK-NEXT: BL @use_int, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp
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; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[PHI]], 1, 0
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; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
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; CHECK-NEXT: B %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: RET_ReallyLR
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bb.0:
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liveins: $w0, $s0
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%1:gpr32 = COPY $w0
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%0:fpr32 = COPY $s0
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%3:gpr32all = COPY $wzr
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%2:gpr32all = COPY %3:gpr32all
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bb.1:
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%4:gpr32common = PHI %2:gpr32all, %bb.0, %5:gpr32all, %bb.2
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%6:gpr32 = SUBSWrr %4:gpr32common, %1:gpr32, implicit-def $nzcv
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Bcc 1, %bb.3, implicit $nzcv
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B %bb.2
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bb.2:
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%7:gpr32 = COPY %0:fpr32
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$w0 = COPY %7:gpr32
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BL @use_int, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp
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%8:gpr32sp = ADDWri %4:gpr32common, 1, 0
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%5:gpr32all = COPY %8:gpr32sp
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B %bb.1
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bb.3:
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RET_ReallyLR
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...

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