Automerge: Revert "[SLP]Correctly schedule standalone schedule data, which is part of tree entry"

This reverts commit 57cae2b to fix
a buildbot https://lab.llvm.org/buildbot/#/builders/169/builds/14776

Author: alexey-bataev

llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

@@ -5574,22 +5574,7 @@ class BoUpSLP {
       if (auto *SD = dyn_cast<ScheduleData>(Data)) {
         SD->setScheduled(/*Scheduled=*/true);
         LLVM_DEBUG(dbgs() << "SLP:   schedule " << *SD << "\n");
-        SmallVector<ScheduleBundle> PseudoBundles;
-        SmallVector<ScheduleBundle *> Bundles;
-        Instruction *In = SD->getInst();
-        if (R.isVectorized(In)) {
-          ArrayRef<TreeEntry *> Entries = R.getTreeEntries(In);
-          for (TreeEntry *TE : Entries) {
-            if (!isa<ExtractValueInst, ExtractElementInst, CallBase>(In) &&
-                In->getNumOperands() != TE->getNumOperands())
-              continue;
-            ScheduleBundle &Bundle = PseudoBundles.emplace_back();
-            Bundle.setTreeEntry(TE);
-            Bundle.add(SD);
-            Bundles.push_back(&Bundle);
-          }
-        }
-        ProcessBundleMember(SD, Bundles);
+        ProcessBundleMember(SD, {});
       } else {
         ScheduleBundle &Bundle = *cast<ScheduleBundle>(Data);
         Bundle.setScheduled(/*Scheduled=*/true);
@@ -20868,7 +20853,23 @@ BoUpSLP::BlockScheduling::tryScheduleBundle(ArrayRef<Value *> VL, BoUpSLP *SLP,
   for (Value *V : VL) {
     if (S.isNonSchedulable(V))
       continue;
-    if (!extendSchedulingRegion(V, S)) {
+    // For copybales with parent nodes, which do not need to be scheduled, the
+    // parents should not be commutative, otherwise may incorrectly handle deps
+    // because of the potential reordering of commutative operations.
+    if ((S.isCopyableElement(V) && EI.UserTE && !EI.UserTE->isGather() &&
+         EI.UserTE->hasState() && EI.UserTE->doesNotNeedToSchedule() &&
+         any_of(EI.UserTE->Scalars,
+                [&](Value *V) {
+                  if (isa<PoisonValue>(V))
+                    return false;
+                  auto *I = dyn_cast<Instruction>(V);
+                  return isCommutative(
+                      (I && EI.UserTE->isAltShuffle())
+                          ? EI.UserTE->getMatchingMainOpOrAltOp(I)
+                          : EI.UserTE->getMainOp(),
+                      V);
+                })) ||
+        !extendSchedulingRegion(V, S)) {
       // If the scheduling region got new instructions at the lower end (or it
       // is a new region for the first bundle). This makes it necessary to
       // recalculate all dependencies.

llvm/test/Transforms/SLPVectorizer/X86/copyable-with-non-scheduled-parent-node.ll

@@ -4,15 +4,20 @@
 define i64 @test(ptr %a) {
 ; CHECK-LABEL: define i64 @test(
 ; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:    [[TMP1:%.*]] = add i64 0, 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = load i64, ptr [[A]], align 4
-; CHECK-NEXT:    [[TMP7:%.*]] = insertelement <4 x i64> <i64 poison, i64 0, i64 0, i64 0>, i64 [[TMP2]], i32 0
-; CHECK-NEXT:    [[TMP3:%.*]] = add <4 x i64> zeroinitializer, [[TMP7]]
-; CHECK-NEXT:    [[TMP4:%.*]] = add <4 x i64> <i64 0, i64 0, i64 0, i64 1>, [[TMP3]]
-; CHECK-NEXT:    [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison>
-; CHECK-NEXT:    [[TMP6:%.*]] = shufflevector <6 x i64> [[TMP5]], <6 x i64> <i64 0, i64 0, i64 undef, i64 undef, i64 undef, i64 undef>, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 6, i32 7>
+; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[TMP2]], 0
+; CHECK-NEXT:    [[TMP4:%.*]] = add i64 1, [[TMP1]]
+; CHECK-NEXT:    [[TMP5:%.*]] = ashr i64 0, 1
+; CHECK-NEXT:    [[TMP6:%.*]] = ashr i64 0, 0
 ; CHECK-NEXT:    br label %[[BB7:.*]]
 ; CHECK:       [[BB7]]:
-; CHECK-NEXT:    [[TMP8:%.*]] = phi <6 x i64> [ [[TMP6]], [[TMP0:%.*]] ]
+; CHECK-NEXT:    [[TMP8:%.*]] = phi i64 [ [[TMP3]], [[TMP0:%.*]] ]
+; CHECK-NEXT:    [[TMP9:%.*]] = phi i64 [ 0, [[TMP0]] ]
+; CHECK-NEXT:    [[TMP10:%.*]] = phi i64 [ [[TMP6]], [[TMP0]] ]
+; CHECK-NEXT:    [[TMP11:%.*]] = phi i64 [ [[TMP5]], [[TMP0]] ]
+; CHECK-NEXT:    [[TMP12:%.*]] = phi i64 [ 0, [[TMP0]] ]
+; CHECK-NEXT:    [[TMP13:%.*]] = phi i64 [ [[TMP4]], [[TMP0]] ]
 ; CHECK-NEXT:    ret i64 0
 ;
   %1 = add i64 0, 0