[gn] port 6a477f6 more

Author: nico

llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn

@@ -76,6 +76,7 @@ tablegen("AArch64GenSDNodeInfo") {
   visibility = [
     ":LLVMAArch64CodeGen",
     "//bolt/unittests/Core:CoreTests",
+    "//llvm/unittests/Target/AArch64:AArch64Tests",
   ]
   args = [ "-gen-sd-node-info" ]
   td_file = "AArch64.td"

llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn

@@ -19,7 +19,6 @@ unittest("CodeGenTests") {
     "//llvm/lib/Testing/Support",
   ]
   sources = [
-    "AArch64SelectionDAGTest.cpp",
     "AMDGPUMetadataTest.cpp",
     "AllocationOrderTest.cpp",
     "AsmPrinterDwarfTest.cpp",

llvm/utils/gn/secondary/llvm/unittests/Target/AArch64/BUILD.gn

@@ -8,6 +8,7 @@ unittest("AArch64Tests") {
     "//llvm/lib/CodeGen/SelectionDAG",
     "//llvm/lib/Support",
     "//llvm/lib/Target",
+    "//llvm/lib/Target/AArch64:AArch64GenSDNodeInfo",
     "//llvm/lib/Target/AArch64:LLVMAArch64CodeGen",
     "//llvm/lib/Target/AArch64/MCTargetDesc",
     "//llvm/lib/Target/AArch64/TargetInfo",
@@ -18,6 +19,7 @@ unittest("AArch64Tests") {
   sources = [
     "AArch64InstPrinterTest.cpp",
     "AArch64RegisterInfoTest.cpp",
+    "AArch64SelectionDAGTest.cpp",
     "AArch64SVESchedPseudoTest.cpp",
     "AddressingModes.cpp",
     "DecomposeStackOffsetTest.cpp",