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Automerge: [NVPTX] Add float to tf32 conversion intrinsics (#121507)
This patch adds the missing variants of float to tf32 conversion intrinsics, with their corresponding lit tests. PTX Spec link: https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt Signed-off-by: Durgadoss R <[email protected]>
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‎llvm/include/llvm/IR/IntrinsicsNVVM.td‎

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@@ -1438,6 +1438,16 @@ let TargetPrefix = "nvvm" in {
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def int_nvvm_f2tf32_rna : ClangBuiltin<"__nvvm_f2tf32_rna">,
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Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem, IntrNoCallback]>;
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def int_nvvm_f2tf32_rna_satfinite : ClangBuiltin<"__nvvm_f2tf32_rna_satfinite">,
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Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem, IntrNoCallback]>;
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def int_nvvm_f2tf32_rn : ClangBuiltin<"__nvvm_f2tf32_rn">,
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Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem, IntrNoCallback]>;
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def int_nvvm_f2tf32_rn_relu : ClangBuiltin<"__nvvm_f2tf32_rn_relu">,
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Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem, IntrNoCallback]>;
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def int_nvvm_f2tf32_rz : ClangBuiltin<"__nvvm_f2tf32_rz">,
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Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem, IntrNoCallback]>;
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def int_nvvm_f2tf32_rz_relu : ClangBuiltin<"__nvvm_f2tf32_rz_relu">,
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Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem, IntrNoCallback]>;
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def int_nvvm_ff_to_e4m3x2_rn : ClangBuiltin<"__nvvm_ff_to_e4m3x2_rn">,
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Intrinsic<[llvm_i16_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem, IntrNoCallback]>;

‎llvm/lib/Target/NVPTX/NVPTXInstrInfo.td‎

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@@ -725,6 +725,23 @@ let hasSideEffects = false in {
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def CVT_f16x2_e4m3x2 : CVT_f16x2_fp8<"e4m3">;
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def CVT_f16x2_e5m2x2 : CVT_f16x2_fp8<"e5m2">;
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// Float to TF32 conversions
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multiclass CVT_TO_TF32<string Modifier, list<Predicate> Preds = [hasPTX<78>, hasSM<90>]> {
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defvar Intr = !cast<Intrinsic>("int_nvvm_f2tf32_" # !subst(".", "_", Modifier));
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def NAME : NVPTXInst<(outs Int32Regs:$dst), (ins Float32Regs:$src),
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"cvt." # Modifier # ".tf32.f32 \t$dst, $src;",
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[(set i32:$dst, (Intr f32:$src))]>,
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Requires<Preds>;
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}
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defm CVT_to_tf32_rn : CVT_TO_TF32<"rn">;
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defm CVT_to_tf32_rz : CVT_TO_TF32<"rz">;
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defm CVT_to_tf32_rn_relu : CVT_TO_TF32<"rn.relu">;
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defm CVT_to_tf32_rz_relu : CVT_TO_TF32<"rz.relu">;
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defm CVT_to_tf32_rna : CVT_TO_TF32<"rna", [hasPTX<70>, hasSM<80>]>;
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defm CVT_to_tf32_rna_satf : CVT_TO_TF32<"rna.satfinite", [hasPTX<81>, hasSM<89>]>;
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}
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def fpround_oneuse : PatFrag<(ops node:$a), (fpround node:$a), [{

‎llvm/lib/Target/NVPTX/NVPTXIntrinsics.td‎

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@@ -1722,11 +1722,6 @@ def : Pat<(int_nvvm_f2bf16_rz f32:$a),
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def : Pat<(int_nvvm_f2bf16_rz_relu f32:$a),
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(CVT_bf16_f32 $a, CvtRZ_RELU)>;
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def CVT_tf32_f32 :
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NVPTXInst<(outs Int32Regs:$dest), (ins Float32Regs:$a),
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"cvt.rna.tf32.f32 \t$dest, $a;",
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[(set i32:$dest, (int_nvvm_f2tf32_rna f32:$a))]>;
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def INT_NVVM_LOHI_I2D : F_MATH_2<"mov.b64 \t$dst, {{$src0, $src1}};",
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Float64Regs, Int32Regs, Int32Regs, int_nvvm_lohi_i2d>;
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‎llvm/test/CodeGen/NVPTX/convert-sm89.ll‎

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@@ -84,3 +84,10 @@ define <2 x half> @cvt_rn_relu_f16x2_e5m2x2(i16 %in) {
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%val = call <2 x half> @llvm.nvvm.e5m2x2.to.f16x2.rn.relu(i16 %in);
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ret <2 x half> %val
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}
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; CHECK-LABEL: cvt_rna_satfinite_tf32_f32
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define i32 @cvt_rna_satfinite_tf32_f32(float %f1) {
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; CHECK: cvt.rna.satfinite.tf32.f32
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%val = call i32 @llvm.nvvm.f2tf32.rna.satfinite(float %f1)
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ret i32 %val
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}

‎llvm/test/CodeGen/NVPTX/convert-sm90.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx78| FileCheck --check-prefixes=CHECK %s
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; RUN: %if ptxas-12.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_90 -mattr=+ptx78| %ptxas-verify -arch=sm_90 %}
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declare i32 @llvm.nvvm.f2tf32.rn(float %f1)
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declare i32 @llvm.nvvm.f2tf32.rn.relu(float %f1)
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declare i32 @llvm.nvvm.f2tf32.rz(float %f1)
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declare i32 @llvm.nvvm.f2tf32.rz.relu(float %f1)
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define i32 @cvt_rn_tf32_f32(float %f1) {
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; CHECK-LABEL: cvt_rn_tf32_f32(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-NEXT: .reg .f32 %f<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.f32 %f1, [cvt_rn_tf32_f32_param_0];
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; CHECK-NEXT: cvt.rn.tf32.f32 %r1, %f1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
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; CHECK-NEXT: ret;
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%val = call i32 @llvm.nvvm.f2tf32.rn(float %f1)
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ret i32 %val
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}
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define i32 @cvt_rn_relu_tf32_f32(float %f1) {
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; CHECK-LABEL: cvt_rn_relu_tf32_f32(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-NEXT: .reg .f32 %f<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.f32 %f1, [cvt_rn_relu_tf32_f32_param_0];
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; CHECK-NEXT: cvt.rn.relu.tf32.f32 %r1, %f1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
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; CHECK-NEXT: ret;
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%val = call i32 @llvm.nvvm.f2tf32.rn.relu(float %f1)
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ret i32 %val
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}
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define i32 @cvt_rz_tf32_f32(float %f1) {
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; CHECK-LABEL: cvt_rz_tf32_f32(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-NEXT: .reg .f32 %f<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.f32 %f1, [cvt_rz_tf32_f32_param_0];
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; CHECK-NEXT: cvt.rz.tf32.f32 %r1, %f1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
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; CHECK-NEXT: ret;
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%val = call i32 @llvm.nvvm.f2tf32.rz(float %f1)
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ret i32 %val
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}
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define i32 @cvt_rz_relu_tf32_f32(float %f1) {
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; CHECK-LABEL: cvt_rz_relu_tf32_f32(
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; CHECK: {
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; CHECK-NEXT: .reg .b32 %r<2>;
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; CHECK-NEXT: .reg .f32 %f<2>;
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; CHECK-EMPTY:
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; CHECK-NEXT: // %bb.0:
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; CHECK-NEXT: ld.param.f32 %f1, [cvt_rz_relu_tf32_f32_param_0];
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; CHECK-NEXT: cvt.rz.relu.tf32.f32 %r1, %f1;
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; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
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; CHECK-NEXT: ret;
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%val = call i32 @llvm.nvvm.f2tf32.rz.relu(float %f1)
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ret i32 %val
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}

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