Skip to content

Commit 8b2c013

Browse files
tclin914tclin914
authored
[RISCV] Use print-enabled-extensions to check the extensions of Andes n45/nx45/a45/ax45 cpus. NFC. (#140979)
Similarly to what #137725 did for the SiFive P870.
1 parent bcdce98 commit 8b2c013

File tree

5 files changed

+114
-40
lines changed

5 files changed

+114
-40
lines changed

‎clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
// RUN: %clang --target=riscv32 -mcpu=andes-a45 --print-enabled-extensions | FileCheck %s
2+
// REQUIRES: riscv-registered-target
3+
4+
// CHECK: Extensions enabled for the given RISC-V target
5+
// CHECK-EMPTY:
6+
// CHECK-NEXT: Name Version Description
7+
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
8+
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
9+
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
10+
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
11+
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
12+
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
14+
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
15+
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
16+
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
17+
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
18+
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
19+
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
20+
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21+
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
22+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
23+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
24+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
25+
// CHECK-EMPTY:
26+
// CHECK-NEXT: Experimental extensions
27+
// CHECK-EMPTY:
28+
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
// RUN: %clang --target=riscv64 -mcpu=andes-ax45 --print-enabled-extensions | FileCheck %s
2+
// REQUIRES: riscv-registered-target
3+
4+
// CHECK: Extensions enabled for the given RISC-V target
5+
// CHECK-EMPTY:
6+
// CHECK-NEXT: Name Version Description
7+
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
8+
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
9+
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
10+
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
11+
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
12+
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
14+
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
15+
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
16+
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
17+
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
18+
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
19+
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
20+
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
22+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
23+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
24+
// CHECK-EMPTY:
25+
// CHECK-NEXT: Experimental extensions
26+
// CHECK-EMPTY:
27+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
// RUN: %clang --target=riscv32 -mcpu=andes-n45 --print-enabled-extensions | FileCheck %s
2+
// REQUIRES: riscv-registered-target
3+
4+
// CHECK: Extensions enabled for the given RISC-V target
5+
// CHECK-EMPTY:
6+
// CHECK-NEXT: Name Version Description
7+
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
8+
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
9+
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
10+
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
11+
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
12+
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
14+
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
15+
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
16+
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
17+
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
18+
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
19+
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
20+
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21+
// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
22+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
23+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
24+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
25+
// CHECK-EMPTY:
26+
// CHECK-NEXT: Experimental extensions
27+
// CHECK-EMPTY:
28+
// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
// RUN: %clang --target=riscv64 -mcpu=andes-nx45 --print-enabled-extensions | FileCheck %s
2+
// REQUIRES: riscv-registered-target
3+
4+
// CHECK: Extensions enabled for the given RISC-V target
5+
// CHECK-EMPTY:
6+
// CHECK-NEXT: Name Version Description
7+
// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
8+
// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
9+
// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
10+
// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
11+
// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
12+
// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
13+
// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
14+
// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
15+
// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
16+
// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
17+
// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
18+
// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
19+
// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
20+
// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
21+
// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
22+
// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
23+
// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
24+
// CHECK-EMPTY:
25+
// CHECK-NEXT: Experimental extensions
26+
// CHECK-EMPTY:
27+
// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0

‎clang/test/Driver/riscv-cpus.c‎

Lines changed: 4 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -716,68 +716,32 @@
716716
// MTUNE-ANDES-AX25: "-tune-cpu" "andes-ax25"
717717

718718
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
719+
// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-n45.c`
719720
// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
720-
// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
721-
// MCPU-ANDES-N45-SAME: "-target-feature" "+a"
722-
// MCPU-ANDES-N45-SAME: "-target-feature" "+f"
723-
// MCPU-ANDES-N45-SAME: "-target-feature" "+d"
724-
// MCPU-ANDES-N45-SAME: "-target-feature" "+c"
725-
// MCPU-ANDES-N45-SAME: "-target-feature" "+zicsr"
726-
// MCPU-ANDES-N45-SAME: "-target-feature" "+zifencei"
727-
// MCPU-ANDES-N45-SAME: "-target-feature" "+zba"
728-
// MCPU-ANDES-N45-SAME: "-target-feature" "+zbb"
729-
// MCPU-ANDES-N45-SAME: "-target-feature" "+zbs"
730721
// MCPU-ANDES-N45-SAME: "-target-abi" "ilp32d"
731722

732723
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-n45 | FileCheck -check-prefix=MTUNE-ANDES-N45 %s
733724
// MTUNE-ANDES-N45: "-tune-cpu" "andes-n45"
734725

735726
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-nx45 | FileCheck -check-prefix=MCPU-ANDES-NX45 %s
727+
// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-nx45.c`
736728
// MCPU-ANDES-NX45: "-target-cpu" "andes-nx45"
737-
// MCPU-ANDES-NX45-SAME: "-target-feature" "+m"
738-
// MCPU-ANDES-NX45-SAME: "-target-feature" "+a"
739-
// MCPU-ANDES-NX45-SAME: "-target-feature" "+f"
740-
// MCPU-ANDES-NX45-SAME: "-target-feature" "+d"
741-
// MCPU-ANDES-NX45-SAME: "-target-feature" "+c"
742-
// MCPU-ANDES-NX45-SAME: "-target-feature" "+zicsr"
743-
// MCPU-ANDES-NX45-SAME: "-target-feature" "+zifencei"
744-
// MCPU-ANDES-NX45-SAME: "-target-feature" "+zba"
745-
// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbb"
746-
// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbs"
747729
// MCPU-ANDES-NX45-SAME: "-target-abi" "lp64d"
748730

749731
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck -check-prefix=MTUNE-ANDES-NX45 %s
750732
// MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"
751733

752734
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a45 | FileCheck -check-prefix=MCPU-ANDES-A45 %s
735+
// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-a45.c`
753736
// MCPU-ANDES-A45: "-target-cpu" "andes-a45"
754-
// MCPU-ANDES-A45-SAME: "-target-feature" "+m"
755-
// MCPU-ANDES-A45-SAME: "-target-feature" "+a"
756-
// MCPU-ANDES-A45-SAME: "-target-feature" "+f"
757-
// MCPU-ANDES-A45-SAME: "-target-feature" "+d"
758-
// MCPU-ANDES-A45-SAME: "-target-feature" "+c"
759-
// MCPU-ANDES-A45-SAME: "-target-feature" "+zicsr"
760-
// MCPU-ANDES-A45-SAME: "-target-feature" "+zifencei"
761-
// MCPU-ANDES-A45-SAME: "-target-feature" "+zba"
762-
// MCPU-ANDES-A45-SAME: "-target-feature" "+zbb"
763-
// MCPU-ANDES-A45-SAME: "-target-feature" "+zbs"
764737
// MCPU-ANDES-A45-SAME: "-target-abi" "ilp32d"
765738

766739
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a45 | FileCheck -check-prefix=MTUNE-ANDES-A45 %s
767740
// MTUNE-ANDES-A45: "-tune-cpu" "andes-a45"
768741

769742
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax45 | FileCheck -check-prefix=MCPU-ANDES-AX45 %s
743+
// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-ax45.c`
770744
// MCPU-ANDES-AX45: "-target-cpu" "andes-ax45"
771-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+m"
772-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+a"
773-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+f"
774-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+d"
775-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+c"
776-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+zicsr"
777-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+zifencei"
778-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+zba"
779-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+zbb"
780-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+zbs"
781745
// MCPU-ANDES-AX45-SAME: "-target-abi" "lp64d"
782746

783747
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax45 | FileCheck -check-prefix=MTUNE-ANDES-AX45 %s

0 commit comments

Comments
 (0)