Skip to content

Commit 9011355

Browse files
toppercgithub-actions[bot]
topperc
authored and
github-actions[bot]
committed
Automerge: [RISCV] Use X0_Pair for 0.0 and -0.0 with Zdinx. (#141641)
2 parents b9a2713 + 0b75a20 commit 9011355

File tree

8 files changed

+92
-78
lines changed

8 files changed

+92
-78
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -902,18 +902,23 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
902902
case ISD::ConstantFP: {
903903
const APFloat &APF = cast<ConstantFPSDNode>(Node)->getValueAPF();
904904

905+
bool Is64Bit = Subtarget->is64Bit();
906+
bool HasZdinx = Subtarget->hasStdExtZdinx();
907+
905908
bool NegZeroF64 = APF.isNegZero() && VT == MVT::f64;
906909
SDValue Imm;
907910
// For +0.0 or f64 -0.0 we need to start from X0. For all others, we will
908911
// create an integer immediate.
909-
if (APF.isPosZero() || NegZeroF64)
910-
Imm = CurDAG->getRegister(RISCV::X0, XLenVT);
911-
else
912+
if (APF.isPosZero() || NegZeroF64) {
913+
if (VT == MVT::f64 && HasZdinx && !Is64Bit)
914+
Imm = CurDAG->getRegister(RISCV::X0_Pair, MVT::f64);
915+
else
916+
Imm = CurDAG->getRegister(RISCV::X0, XLenVT);
917+
} else {
912918
Imm = selectImm(CurDAG, DL, XLenVT, APF.bitcastToAPInt().getSExtValue(),
913919
*Subtarget);
920+
}
914921

915-
bool HasZdinx = Subtarget->hasStdExtZdinx();
916-
bool Is64Bit = Subtarget->is64Bit();
917922
unsigned Opc;
918923
switch (VT.SimpleTy) {
919924
default:
@@ -932,10 +937,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
932937
// For RV32, we can't move from a GPR, we need to convert instead. This
933938
// should only happen for +0.0 and -0.0.
934939
assert((Subtarget->is64Bit() || APF.isZero()) && "Unexpected constant");
935-
if (Is64Bit)
936-
Opc = HasZdinx ? RISCV::COPY : RISCV::FMV_D_X;
940+
if (HasZdinx)
941+
Opc = RISCV::COPY;
937942
else
938-
Opc = HasZdinx ? RISCV::FCVT_D_W_IN32X : RISCV::FCVT_D_W;
943+
Opc = Is64Bit ? RISCV::FMV_D_X : RISCV::FCVT_D_W;
939944
break;
940945
}
941946

‎llvm/test/CodeGen/RISCV/double-arith-strict.ll‎

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -379,8 +379,7 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind strictfp {
379379
;
380380
; RV32IZFINXZDINX-LABEL: fmsub_d:
381381
; RV32IZFINXZDINX: # %bb.0:
382-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
383-
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
382+
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, zero
384383
; RV32IZFINXZDINX-NEXT: fmsub.d a0, a0, a2, a4
385384
; RV32IZFINXZDINX-NEXT: ret
386385
;
@@ -470,9 +469,8 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind strictfp {
470469
;
471470
; RV32IZFINXZDINX-LABEL: fnmadd_d:
472471
; RV32IZFINXZDINX: # %bb.0:
473-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
474-
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
475-
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
472+
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, zero
473+
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, zero
476474
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a0, a2, a4
477475
; RV32IZFINXZDINX-NEXT: ret
478476
;
@@ -581,9 +579,8 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind strictfp {
581579
;
582580
; RV32IZFINXZDINX-LABEL: fnmadd_d_2:
583581
; RV32IZFINXZDINX: # %bb.0:
584-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
585-
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
586-
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
582+
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, zero
583+
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, zero
587584
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a2, a0, a4
588585
; RV32IZFINXZDINX-NEXT: ret
589586
;
@@ -691,8 +688,7 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind strictfp {
691688
;
692689
; RV32IZFINXZDINX-LABEL: fnmsub_d:
693690
; RV32IZFINXZDINX: # %bb.0:
694-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
695-
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
691+
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, zero
696692
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a0, a2, a4
697693
; RV32IZFINXZDINX-NEXT: ret
698694
;
@@ -776,8 +772,7 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind strictfp {
776772
;
777773
; RV32IZFINXZDINX-LABEL: fnmsub_d_2:
778774
; RV32IZFINXZDINX: # %bb.0:
779-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
780-
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
775+
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, zero
781776
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a2, a0, a4
782777
; RV32IZFINXZDINX-NEXT: ret
783778
;

‎llvm/test/CodeGen/RISCV/double-arith.ll‎

Lines changed: 13 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -539,8 +539,7 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
539539
;
540540
; RV32IZFINXZDINX-LABEL: fmsub_d:
541541
; RV32IZFINXZDINX: # %bb.0:
542-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
543-
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
542+
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, zero
544543
; RV32IZFINXZDINX-NEXT: fmsub.d a0, a0, a2, a4
545544
; RV32IZFINXZDINX-NEXT: ret
546545
;
@@ -630,9 +629,8 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
630629
;
631630
; RV32IZFINXZDINX-LABEL: fnmadd_d:
632631
; RV32IZFINXZDINX: # %bb.0:
633-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
634-
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
635-
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
632+
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, zero
633+
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, zero
636634
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a0, a2, a4
637635
; RV32IZFINXZDINX-NEXT: ret
638636
;
@@ -741,9 +739,8 @@ define double @fnmadd_d_2(double %a, double %b, double %c) nounwind {
741739
;
742740
; RV32IZFINXZDINX-LABEL: fnmadd_d_2:
743741
; RV32IZFINXZDINX: # %bb.0:
744-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
745-
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
746-
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
742+
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, zero
743+
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, zero
747744
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a2, a0, a4
748745
; RV32IZFINXZDINX-NEXT: ret
749746
;
@@ -941,8 +938,7 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
941938
;
942939
; RV32IZFINXZDINX-LABEL: fnmsub_d:
943940
; RV32IZFINXZDINX: # %bb.0:
944-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
945-
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
941+
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, zero
946942
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a0, a2, a4
947943
; RV32IZFINXZDINX-NEXT: ret
948944
;
@@ -1026,8 +1022,7 @@ define double @fnmsub_d_2(double %a, double %b, double %c) nounwind {
10261022
;
10271023
; RV32IZFINXZDINX-LABEL: fnmsub_d_2:
10281024
; RV32IZFINXZDINX: # %bb.0:
1029-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
1030-
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
1025+
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, zero
10311026
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a2, a0, a4
10321027
; RV32IZFINXZDINX-NEXT: ret
10331028
;
@@ -1167,8 +1162,7 @@ define double @fmsub_d_contract(double %a, double %b, double %c) nounwind {
11671162
;
11681163
; RV32IZFINXZDINX-LABEL: fmsub_d_contract:
11691164
; RV32IZFINXZDINX: # %bb.0:
1170-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
1171-
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
1165+
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, zero
11721166
; RV32IZFINXZDINX-NEXT: fmsub.d a0, a0, a2, a4
11731167
; RV32IZFINXZDINX-NEXT: ret
11741168
;
@@ -1268,10 +1262,9 @@ define double @fnmadd_d_contract(double %a, double %b, double %c) nounwind {
12681262
;
12691263
; RV32IZFINXZDINX-LABEL: fnmadd_d_contract:
12701264
; RV32IZFINXZDINX: # %bb.0:
1271-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
1272-
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
1273-
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
1274-
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, a6
1265+
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, zero
1266+
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, zero
1267+
; RV32IZFINXZDINX-NEXT: fadd.d a4, a4, zero
12751268
; RV32IZFINXZDINX-NEXT: fnmadd.d a0, a0, a2, a4
12761269
; RV32IZFINXZDINX-NEXT: ret
12771270
;
@@ -1398,9 +1391,8 @@ define double @fnmsub_d_contract(double %a, double %b, double %c) nounwind {
13981391
;
13991392
; RV32IZFINXZDINX-LABEL: fnmsub_d_contract:
14001393
; RV32IZFINXZDINX: # %bb.0:
1401-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a6, zero
1402-
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a6
1403-
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, a6
1394+
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, zero
1395+
; RV32IZFINXZDINX-NEXT: fadd.d a2, a2, zero
14041396
; RV32IZFINXZDINX-NEXT: fnmsub.d a0, a0, a2, a4
14051397
; RV32IZFINXZDINX-NEXT: ret
14061398
;

‎llvm/test/CodeGen/RISCV/double-convert.ll‎

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -987,16 +987,15 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
987987
; RV32IZFINXZDINX-NEXT: mv s1, a1
988988
; RV32IZFINXZDINX-NEXT: mv s0, a0
989989
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
990-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
991-
; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI14_0)
992-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
993-
; RV32IZFINXZDINX-NEXT: lw a6, %lo(.LCPI14_0)(a4)
994-
; RV32IZFINXZDINX-NEXT: addi a3, a4, %lo(.LCPI14_0)
995-
; RV32IZFINXZDINX-NEXT: lw a7, 4(a3)
990+
; RV32IZFINXZDINX-NEXT: fle.d a2, zero, s0
991+
; RV32IZFINXZDINX-NEXT: lui a3, %hi(.LCPI14_0)
992+
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a3)
993+
; RV32IZFINXZDINX-NEXT: addi a3, a3, %lo(.LCPI14_0)
994+
; RV32IZFINXZDINX-NEXT: lw a5, 4(a3)
996995
; RV32IZFINXZDINX-NEXT: neg a2, a2
997996
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
998997
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
999-
; RV32IZFINXZDINX-NEXT: flt.d a2, a6, s0
998+
; RV32IZFINXZDINX-NEXT: flt.d a2, a4, s0
1000999
; RV32IZFINXZDINX-NEXT: neg a2, a2
10011000
; RV32IZFINXZDINX-NEXT: or a0, a2, a0
10021001
; RV32IZFINXZDINX-NEXT: or a1, a2, a1
@@ -1860,8 +1859,7 @@ define zeroext i16 @fcvt_wu_s_sat_i16(double %a) nounwind {
18601859
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI28_0)(a2)
18611860
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI28_0)
18621861
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
1863-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
1864-
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
1862+
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, zero
18651863
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
18661864
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
18671865
; RV32IZFINXZDINX-NEXT: ret
@@ -2237,8 +2235,7 @@ define zeroext i8 @fcvt_wu_s_sat_i8(double %a) nounwind {
22372235
; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI32_0)(a2)
22382236
; RV32IZFINXZDINX-NEXT: addi a2, a2, %lo(.LCPI32_0)
22392237
; RV32IZFINXZDINX-NEXT: lw a5, 4(a2)
2240-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
2241-
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a2
2238+
; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, zero
22422239
; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
22432240
; RV32IZFINXZDINX-NEXT: fcvt.wu.d a0, a0, rtz
22442241
; RV32IZFINXZDINX-NEXT: ret

‎llvm/test/CodeGen/RISCV/double-imm.ll‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -146,8 +146,7 @@ define dso_local double @negzero_sel(i16 noundef %a, double noundef %d) nounwind
146146
; CHECKRV32ZDINX-NEXT: slli a0, a0, 16
147147
; CHECKRV32ZDINX-NEXT: beqz a0, .LBB4_2
148148
; CHECKRV32ZDINX-NEXT: # %bb.1: # %entry
149-
; CHECKRV32ZDINX-NEXT: fcvt.d.w a0, zero
150-
; CHECKRV32ZDINX-NEXT: fneg.d a2, a0
149+
; CHECKRV32ZDINX-NEXT: fneg.d a2, zero
151150
; CHECKRV32ZDINX-NEXT: j .LBB4_3
152151
; CHECKRV32ZDINX-NEXT: .LBB4_2:
153152
; CHECKRV32ZDINX-NEXT: mv a3, a2

‎llvm/test/CodeGen/RISCV/double-mem.ll‎

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -402,3 +402,34 @@ define dso_local void @fsd_trunc(ptr %a, double %b) nounwind noinline optnone {
402402
store float %1, ptr %a, align 4
403403
ret void
404404
}
405+
406+
define dso_local void @store_zero(ptr %a) {
407+
; RV32IFD-LABEL: store_zero:
408+
; RV32IFD: # %bb.0:
409+
; RV32IFD-NEXT: fcvt.d.w fa5, zero
410+
; RV32IFD-NEXT: fsd fa5, 0(a0)
411+
; RV32IFD-NEXT: ret
412+
;
413+
; RV64IFD-LABEL: store_zero:
414+
; RV64IFD: # %bb.0:
415+
; RV64IFD-NEXT: sd zero, 0(a0)
416+
; RV64IFD-NEXT: ret
417+
;
418+
; RV32IZFINXZDINX-LABEL: store_zero:
419+
; RV32IZFINXZDINX: # %bb.0:
420+
; RV32IZFINXZDINX-NEXT: sw zero, 0(a0)
421+
; RV32IZFINXZDINX-NEXT: sw zero, 4(a0)
422+
; RV32IZFINXZDINX-NEXT: ret
423+
;
424+
; RV64IZFINXZDINX-LABEL: store_zero:
425+
; RV64IZFINXZDINX: # %bb.0:
426+
; RV64IZFINXZDINX-NEXT: sd zero, 0(a0)
427+
; RV64IZFINXZDINX-NEXT: ret
428+
;
429+
; RV32IZFINXZDINXZILSD-LABEL: store_zero:
430+
; RV32IZFINXZDINXZILSD: # %bb.0:
431+
; RV32IZFINXZDINXZILSD-NEXT: sd zero, 0(a0)
432+
; RV32IZFINXZDINXZILSD-NEXT: ret
433+
store double 0.0, ptr %a
434+
ret void
435+
}

‎llvm/test/CodeGen/RISCV/double-round-conv-sat.ll‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -231,8 +231,7 @@ define i64 @test_floor_ui64(double %x) nounwind {
231231
; RV32IZFINXZDINX-NEXT: neg s2, a0
232232
; RV32IZFINXZDINX-NEXT: mv a0, s0
233233
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
234-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
235-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
234+
; RV32IZFINXZDINX-NEXT: fle.d a2, zero, s0
236235
; RV32IZFINXZDINX-NEXT: neg a2, a2
237236
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
238237
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
@@ -481,8 +480,7 @@ define i64 @test_ceil_ui64(double %x) nounwind {
481480
; RV32IZFINXZDINX-NEXT: neg s2, a0
482481
; RV32IZFINXZDINX-NEXT: mv a0, s0
483482
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
484-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
485-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
483+
; RV32IZFINXZDINX-NEXT: fle.d a2, zero, s0
486484
; RV32IZFINXZDINX-NEXT: neg a2, a2
487485
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
488486
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
@@ -731,8 +729,7 @@ define i64 @test_trunc_ui64(double %x) nounwind {
731729
; RV32IZFINXZDINX-NEXT: neg s2, a0
732730
; RV32IZFINXZDINX-NEXT: mv a0, s0
733731
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
734-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
735-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
732+
; RV32IZFINXZDINX-NEXT: fle.d a2, zero, s0
736733
; RV32IZFINXZDINX-NEXT: neg a2, a2
737734
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
738735
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
@@ -981,8 +978,7 @@ define i64 @test_round_ui64(double %x) nounwind {
981978
; RV32IZFINXZDINX-NEXT: neg s2, a0
982979
; RV32IZFINXZDINX-NEXT: mv a0, s0
983980
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
984-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
985-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
981+
; RV32IZFINXZDINX-NEXT: fle.d a2, zero, s0
986982
; RV32IZFINXZDINX-NEXT: neg a2, a2
987983
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
988984
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
@@ -1231,8 +1227,7 @@ define i64 @test_roundeven_ui64(double %x) nounwind {
12311227
; RV32IZFINXZDINX-NEXT: neg s2, a0
12321228
; RV32IZFINXZDINX-NEXT: mv a0, s0
12331229
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
1234-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
1235-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
1230+
; RV32IZFINXZDINX-NEXT: fle.d a2, zero, s0
12361231
; RV32IZFINXZDINX-NEXT: neg a2, a2
12371232
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
12381233
; RV32IZFINXZDINX-NEXT: and a1, a2, a1
@@ -1481,8 +1476,7 @@ define i64 @test_rint_ui64(double %x) nounwind {
14811476
; RV32IZFINXZDINX-NEXT: neg s2, a0
14821477
; RV32IZFINXZDINX-NEXT: mv a0, s0
14831478
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
1484-
; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero
1485-
; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0
1479+
; RV32IZFINXZDINX-NEXT: fle.d a2, zero, s0
14861480
; RV32IZFINXZDINX-NEXT: neg a2, a2
14871481
; RV32IZFINXZDINX-NEXT: and a0, a2, a0
14881482
; RV32IZFINXZDINX-NEXT: and a1, a2, a1

‎llvm/test/CodeGen/RISCV/fold-addi-loadstore-zilsd.ll‎

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,7 @@ define void @store_g_0() nounwind {
2121
; CHECK: # %bb.0: # %entry
2222
; CHECK-NEXT: .Lpcrel_hi1:
2323
; CHECK-NEXT: auipc a0, %pcrel_hi(g_0)
24-
; CHECK-NEXT: fcvt.d.w a2, zero
25-
; CHECK-NEXT: sd a2, %pcrel_lo(.Lpcrel_hi1)(a0)
24+
; CHECK-NEXT: sd zero, %pcrel_lo(.Lpcrel_hi1)(a0)
2625
; CHECK-NEXT: ret
2726
entry:
2827
store double 0.0, ptr @g_0
@@ -43,25 +42,27 @@ define double @fold_addi_from_different_bb(i32 %k, i32 %n, ptr %a) nounwind {
4342
; CHECK-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
4443
; CHECK-NEXT: blez a1, .LBB2_3
4544
; CHECK-NEXT: # %bb.1: # %for.body.lr.ph
46-
; CHECK-NEXT: mv s0, a2
47-
; CHECK-NEXT: mv s1, a1
45+
; CHECK-NEXT: mv s2, a2
46+
; CHECK-NEXT: mv s3, a1
47+
; CHECK-NEXT: li s0, 0
48+
; CHECK-NEXT: li s1, 0
4849
; CHECK-NEXT: slli a0, a0, 4
4950
; CHECK-NEXT: add s4, a2, a0
50-
; CHECK-NEXT: fcvt.d.w s2, zero
5151
; CHECK-NEXT: .LBB2_2: # %for.body
5252
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
53-
; CHECK-NEXT: mv a0, s0
53+
; CHECK-NEXT: mv a0, s2
5454
; CHECK-NEXT: call f
5555
; CHECK-NEXT: ld a0, 8(s4)
56-
; CHECK-NEXT: addi s1, s1, -1
57-
; CHECK-NEXT: fadd.d s2, a0, s2
58-
; CHECK-NEXT: bnez s1, .LBB2_2
56+
; CHECK-NEXT: addi s3, s3, -1
57+
; CHECK-NEXT: fadd.d s0, a0, s0
58+
; CHECK-NEXT: bnez s3, .LBB2_2
5959
; CHECK-NEXT: j .LBB2_4
6060
; CHECK-NEXT: .LBB2_3:
61-
; CHECK-NEXT: fcvt.d.w s2, zero
61+
; CHECK-NEXT: li s0, 0
62+
; CHECK-NEXT: li s1, 0
6263
; CHECK-NEXT: .LBB2_4: # %for.cond.cleanup
63-
; CHECK-NEXT: mv a0, s2
64-
; CHECK-NEXT: mv a1, s3
64+
; CHECK-NEXT: mv a0, s0
65+
; CHECK-NEXT: mv a1, s1
6566
; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
6667
; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
6768
; CHECK-NEXT: lw s1, 20(sp) # 4-byte Folded Reload

0 commit comments

Comments
 (0)