Automerge: [RISCV] Add scheduling info for XSfvqmaccdod/qoq and XSfvfwmaccqqq instructions (#147626)

XSfvqmaccdod/qoq and XSfvfwmaccqqq are SiFive's small-size matrix
multiplication extensions. This patches add scheduling info for their
instructions along with six new SchedReadWrite.

Author: mshockwave

llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

@@ -167,10 +167,25 @@ multiclass CustomSiFiveVCIX<string suffix, VCIXType type,
                                              InTyRs1, 1>;
 }
 
+// For XSfvqmaccdod/qoq and XSfvfwmaccqqq
+class SiFiveVMACCScheds<string name> {
+  defvar n = !tolower(name);
+  defvar prefix = !if(!ne(!find(n, "fw"), -1), "FW", "Q");
+  defvar suffix = !if(!ne(!find(n, "2x8x2"), -1), "DOD",
+                      !if(!eq(prefix, "Q"), "QOQ", "QQQ"));
+
+  string read = "ReadSF_V" # prefix # "MACC_" # suffix;
+  string write = "WriteSF_V" # prefix # "MACC_" # suffix;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr>
     : RVInstVCCustom2<funct6{5-2}, opv.Value, (outs VR:$rd), (ins VR:$rs1, VR:$rs2),
-                      opcodestr, "$rd, $rs1, $rs2"> {
+                      opcodestr, "$rd, $rs1, $rs2">,
+      SchedTernaryMC<SiFiveVMACCScheds<NAME>.write,
+                     SiFiveVMACCScheds<NAME>.read,
+                     SiFiveVMACCScheds<NAME>.read,
+                     SiFiveVMACCScheds<NAME>.read> {
   let vm = 1;
   let funct6_lo2 = funct6{1-0};
 }
@@ -374,9 +389,13 @@ multiclass VPseudoVC_XVW<LMULInfo m, DAGOperand RS1Class,
 }
 
 multiclass VPseudoSiFiveVMACC<string mx, VReg vd_type, VReg vs2_type> {
+  defvar SchedWriteName = SiFiveVMACCScheds<NAME>.write;
+  defvar SchedReadName = SiFiveVMACCScheds<NAME>.read;
   def "Pseudo" # NAME # "_" # mx
       : VPseudoTernaryNoMaskWithPolicy<vd_type, V_M1.vrclass, vs2_type,
-                                       "@earlyclobber $rd">;
+                                       "@earlyclobber $rd">,
+        SchedTernary<SchedWriteName, SchedReadName, SchedReadName,
+                     SchedReadName, mx>;
 }
 
 multiclass VPseudoSiFiveVQMACCDOD {

llvm/lib/Target/RISCV/RISCVSchedAndes45.td

@@ -332,6 +332,9 @@ defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedXSfvfnrclipxfqf;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;

llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td

@@ -499,4 +499,7 @@ defm : UnsupportedSchedZvk;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedXSfvfnrclipxfqf;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 }

llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td

@@ -275,5 +275,8 @@ defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedXSfvfnrclipxfqf;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 defm : UnsupportedSchedZvk;
 }

llvm/lib/Target/RISCV/RISCVSchedRocket.td

@@ -264,5 +264,8 @@ defm : UnsupportedSchedZfhmin;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedXSfvfnrclipxfqf;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 defm : UnsupportedSchedZvk;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

@@ -1072,6 +1072,36 @@ multiclass SiFive7WriteResBase<int VLEN,
     defm : LMULWriteResMX<"WriteSF_VFNRClipV", [VCQ, VA1], mx,
                           IsWorstCase=!eq(mx, "M2")>;
   }
+
+  // XSfvqmaccdod
+  foreach mx = ["M1", "M2", "M4", "M8"] in {
+    defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
+    let Latency = 8,
+        AcquireAtCycles = [0, 1],
+        ReleaseAtCycles = [1, !add(1, Cycles)] in
+    defm : LMULWriteResMX<"WriteSF_VQMACC_DOD", [VCQ, VA1], mx,
+                          IsWorstCase=!eq(mx, "M8")>;
+  }
+
+  // XSfvqmaccqoq
+  foreach mx = ["MF2", "M1", "M2", "M4"] in {
+    defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
+    let Latency = 8,
+        AcquireAtCycles = [0, 1],
+        ReleaseAtCycles = [1, !add(1, Cycles)] in
+    defm : LMULWriteResMX<"WriteSF_VQMACC_QOQ", [VCQ, VA1], mx,
+                          IsWorstCase=!eq(mx, "M4")>;
+  }
+
+  // XSfvfwmaccqqq
+  foreach mx = SchedMxListFW in {
+    defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
+    defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
+    let Latency = 8,
+        AcquireAtCycles = [0, 1],
+        ReleaseAtCycles = [1, !add(1, Cycles)] in
+    defm : LMULWriteResMX<"WriteSF_VFWMACC_QQQ", [VCQ, VA1], mx, IsWorstCase>;
+  }
 }
 
 //===----------------------------------------------------------------------===//
@@ -1353,6 +1383,11 @@ multiclass SiFive7ReadAdvance {
   defm : LMULReadAdvance<"ReadSF_VFNRClipV", 0>;
   defm : LMULReadAdvance<"ReadSF_VFNRClipF", 0>;
 
+  // SiFive VMACC
+  defm : LMULReadAdvance<"ReadSF_VQMACC_DOD",  0>;
+  defm : LMULReadAdvance<"ReadSF_VQMACC_QOQ",  0>;
+  defm : LMULReadAdvance<"ReadSF_VFWMACC_QQQ", 0>;
+
   // Others
   def : ReadAdvance<ReadVMask, 0>;
   def : ReadAdvance<ReadVPassthru_WorstCase, 0>;

llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

@@ -1240,4 +1240,7 @@ defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedXSfvfnrclipxfqf;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td

@@ -360,4 +360,7 @@ defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZvk;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedXSfvfnrclipxfqf;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

@@ -1496,4 +1496,7 @@ defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedXSfvfnrclipxfqf;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td

@@ -1185,4 +1185,7 @@ defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfaWithQ;
 defm : UnsupportedSchedXsfvcp;
 defm : UnsupportedSchedXSfvfnrclipxfqf;
+defm : UnsupportedSchedXSfvfwmaccqqq;
+defm : UnsupportedSchedXSfvqmaccdod;
+defm : UnsupportedSchedXSfvqmaccqoq;
 }