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Automerge: [AArch64][GlobalISel] Move special selection for aarch64_crypto_sha1h.
This appears to just need to select FPR registers.
2 parents 8fec9c5 + d4450bb commit a55d723

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+65
-65
lines changed

3 files changed

+65
-65
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp‎

Lines changed: 0 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -6608,45 +6608,6 @@ bool AArch64InstructionSelector::selectIntrinsic(MachineInstr &I,
66086608
switch (IntrinID) {
66096609
default:
66106610
break;
6611-
case Intrinsic::aarch64_crypto_sha1h: {
6612-
Register DstReg = I.getOperand(0).getReg();
6613-
Register SrcReg = I.getOperand(2).getReg();
6614-
6615-
// FIXME: Should this be an assert?
6616-
if (MRI.getType(DstReg).getSizeInBits() != 32 ||
6617-
MRI.getType(SrcReg).getSizeInBits() != 32)
6618-
return false;
6619-
6620-
// The operation has to happen on FPRs. Set up some new FPR registers for
6621-
// the source and destination if they are on GPRs.
6622-
if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() != AArch64::FPRRegBankID) {
6623-
SrcReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
6624-
MIB.buildCopy({SrcReg}, {I.getOperand(2)});
6625-
6626-
// Make sure the copy ends up getting constrained properly.
6627-
RBI.constrainGenericRegister(I.getOperand(2).getReg(),
6628-
AArch64::GPR32RegClass, MRI);
6629-
}
6630-
6631-
if (RBI.getRegBank(DstReg, MRI, TRI)->getID() != AArch64::FPRRegBankID)
6632-
DstReg = MRI.createVirtualRegister(&AArch64::FPR32RegClass);
6633-
6634-
// Actually insert the instruction.
6635-
auto SHA1Inst = MIB.buildInstr(AArch64::SHA1Hrr, {DstReg}, {SrcReg});
6636-
constrainSelectedInstRegOperands(*SHA1Inst, TII, TRI, RBI);
6637-
6638-
// Did we create a new register for the destination?
6639-
if (DstReg != I.getOperand(0).getReg()) {
6640-
// Yep. Copy the result of the instruction back into the original
6641-
// destination.
6642-
MIB.buildCopy({I.getOperand(0)}, {DstReg});
6643-
RBI.constrainGenericRegister(I.getOperand(0).getReg(),
6644-
AArch64::GPR32RegClass, MRI);
6645-
}
6646-
6647-
I.eraseFromParent();
6648-
return true;
6649-
}
66506611
case Intrinsic::ptrauth_resign: {
66516612
Register DstReg = I.getOperand(0).getReg();
66526613
Register ValReg = I.getOperand(2).getReg();

‎llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -482,6 +482,7 @@ static bool isFPIntrinsic(const MachineRegisterInfo &MRI,
482482
case Intrinsic::aarch64_neon_sqrdmulh:
483483
case Intrinsic::aarch64_neon_sqadd:
484484
case Intrinsic::aarch64_neon_sqsub:
485+
case Intrinsic::aarch64_crypto_sha1h:
485486
return true;
486487
case Intrinsic::aarch64_neon_saddlv: {
487488
const LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());

‎llvm/test/CodeGen/AArch64/arm64-crypto.ll‎

Lines changed: 64 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,11 @@
1-
; RUN: llc -mtriple=arm64-eabi -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s
2-
; RUN: llc -mtriple=arm64-eabi -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mattr=crypto -aarch64-neon-syntax=apple -o - %s 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc -mtriple=arm64-eabi -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3+
; RUN: llc -mtriple=arm64-eabi -mattr=crypto -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 -o - %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
; CHECK-GI: warning: Instruction selection used fallback path for test_sha1c
6+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sha1c_in_a_row
7+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sha1p
8+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_sha1m
39

410
declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
511
declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
@@ -8,28 +14,36 @@ declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
814

915
define <16 x i8> @test_aese(<16 x i8> %data, <16 x i8> %key) {
1016
; CHECK-LABEL: test_aese:
11-
; CHECK: aese.16b v0, v1
17+
; CHECK: // %bb.0:
18+
; CHECK-NEXT: aese.16b v0, v1
19+
; CHECK-NEXT: ret
1220
%res = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
1321
ret <16 x i8> %res
1422
}
1523

1624
define <16 x i8> @test_aesd(<16 x i8> %data, <16 x i8> %key) {
1725
; CHECK-LABEL: test_aesd:
18-
; CHECK: aesd.16b v0, v1
26+
; CHECK: // %bb.0:
27+
; CHECK-NEXT: aesd.16b v0, v1
28+
; CHECK-NEXT: ret
1929
%res = call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
2030
ret <16 x i8> %res
2131
}
2232

2333
define <16 x i8> @test_aesmc(<16 x i8> %data) {
2434
; CHECK-LABEL: test_aesmc:
25-
; CHECK: aesmc.16b v0, v0
35+
; CHECK: // %bb.0:
36+
; CHECK-NEXT: aesmc.16b v0, v0
37+
; CHECK-NEXT: ret
2638
%res = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data)
2739
ret <16 x i8> %res
2840
}
2941

3042
define <16 x i8> @test_aesimc(<16 x i8> %data) {
3143
; CHECK-LABEL: test_aesimc:
32-
; CHECK: aesimc.16b v0, v0
44+
; CHECK: // %bb.0:
45+
; CHECK-NEXT: aesimc.16b v0, v0
46+
; CHECK-NEXT: ret
3347
%res = call <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
3448
ret <16 x i8> %res
3549
}
@@ -43,19 +57,23 @@ declare <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12
4357

4458
define <4 x i32> @test_sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
4559
; CHECK-LABEL: test_sha1c:
46-
; CHECK: fmov [[HASH_E:s[0-9]+]], w0
47-
; CHECK: sha1c.4s q0, [[HASH_E]], v1
60+
; CHECK: // %bb.0:
61+
; CHECK-NEXT: fmov s2, w0
62+
; CHECK-NEXT: sha1c.4s q0, s2, v1
63+
; CHECK-NEXT: ret
4864
%res = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
4965
ret <4 x i32> %res
5066
}
5167

5268
; <rdar://problem/14742333> Incomplete removal of unnecessary FMOV instructions in intrinsic SHA1
5369
define <4 x i32> @test_sha1c_in_a_row(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
5470
; CHECK-LABEL: test_sha1c_in_a_row:
55-
; CHECK: fmov [[HASH_E:s[0-9]+]], w0
56-
; CHECK: sha1c.4s q[[SHA1RES:[0-9]+]], [[HASH_E]], v1
57-
; CHECK-NOT: fmov
58-
; CHECK: sha1c.4s q0, s[[SHA1RES]], v1
71+
; CHECK: // %bb.0:
72+
; CHECK-NEXT: fmov s2, w0
73+
; CHECK-NEXT: mov.16b v3, v0
74+
; CHECK-NEXT: sha1c.4s q3, s2, v1
75+
; CHECK-NEXT: sha1c.4s q0, s3, v1
76+
; CHECK-NEXT: ret
5977
%res = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
6078
%extract = extractelement <4 x i32> %res, i32 0
6179
%res2 = call <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %extract, <4 x i32> %wk)
@@ -64,40 +82,49 @@ define <4 x i32> @test_sha1c_in_a_row(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i3
6482

6583
define <4 x i32> @test_sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
6684
; CHECK-LABEL: test_sha1p:
67-
; CHECK: fmov [[HASH_E:s[0-9]+]], w0
68-
; CHECK: sha1p.4s q0, [[HASH_E]], v1
85+
; CHECK: // %bb.0:
86+
; CHECK-NEXT: fmov s2, w0
87+
; CHECK-NEXT: sha1p.4s q0, s2, v1
88+
; CHECK-NEXT: ret
6989
%res = call <4 x i32> @llvm.aarch64.crypto.sha1p(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
7090
ret <4 x i32> %res
7191
}
7292

7393
define <4 x i32> @test_sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) {
7494
; CHECK-LABEL: test_sha1m:
75-
; CHECK: fmov [[HASH_E:s[0-9]+]], w0
76-
; CHECK: sha1m.4s q0, [[HASH_E]], v1
95+
; CHECK: // %bb.0:
96+
; CHECK-NEXT: fmov s2, w0
97+
; CHECK-NEXT: sha1m.4s q0, s2, v1
98+
; CHECK-NEXT: ret
7799
%res = call <4 x i32> @llvm.aarch64.crypto.sha1m(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk)
78100
ret <4 x i32> %res
79101
}
80102

81-
; FALLBACK-NOT: remark{{.*}}test_sha1h
82103
define i32 @test_sha1h(i32 %hash_e) {
83104
; CHECK-LABEL: test_sha1h:
84-
; CHECK: fmov [[HASH_E:s[0-9]+]], w0
85-
; CHECK: sha1h [[RES:s[0-9]+]], [[HASH_E]]
86-
; CHECK: fmov w0, [[RES]]
105+
; CHECK: // %bb.0:
106+
; CHECK-NEXT: fmov s0, w0
107+
; CHECK-NEXT: sha1h s0, s0
108+
; CHECK-NEXT: fmov w0, s0
109+
; CHECK-NEXT: ret
87110
%res = call i32 @llvm.aarch64.crypto.sha1h(i32 %hash_e)
88111
ret i32 %res
89112
}
90113

91114
define <4 x i32> @test_sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11) {
92115
; CHECK-LABEL: test_sha1su0:
93-
; CHECK: sha1su0.4s v0, v1, v2
116+
; CHECK: // %bb.0:
117+
; CHECK-NEXT: sha1su0.4s v0, v1, v2
118+
; CHECK-NEXT: ret
94119
%res = call <4 x i32> @llvm.aarch64.crypto.sha1su0(<4 x i32> %wk0_3, <4 x i32> %wk4_7, <4 x i32> %wk8_11)
95120
ret <4 x i32> %res
96121
}
97122

98123
define <4 x i32> @test_sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15) {
99124
; CHECK-LABEL: test_sha1su1:
100-
; CHECK: sha1su1.4s v0, v1
125+
; CHECK: // %bb.0:
126+
; CHECK-NEXT: sha1su1.4s v0, v1
127+
; CHECK-NEXT: ret
101128
%res = call <4 x i32> @llvm.aarch64.crypto.sha1su1(<4 x i32> %wk0_3, <4 x i32> %wk12_15)
102129
ret <4 x i32> %res
103130
}
@@ -109,29 +136,40 @@ declare <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_
109136

110137
define <4 x i32> @test_sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk) {
111138
; CHECK-LABEL: test_sha256h:
112-
; CHECK: sha256h.4s q0, q1, v2
139+
; CHECK: // %bb.0:
140+
; CHECK-NEXT: sha256h.4s q0, q1, v2
141+
; CHECK-NEXT: ret
113142
%res = call <4 x i32> @llvm.aarch64.crypto.sha256h(<4 x i32> %hash_abcd, <4 x i32> %hash_efgh, <4 x i32> %wk)
114143
ret <4 x i32> %res
115144
}
116145

117146
define <4 x i32> @test_sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk) {
118147
; CHECK-LABEL: test_sha256h2:
119-
; CHECK: sha256h2.4s q0, q1, v2
148+
; CHECK: // %bb.0:
149+
; CHECK-NEXT: sha256h2.4s q0, q1, v2
150+
; CHECK-NEXT: ret
120151

121152
%res = call <4 x i32> @llvm.aarch64.crypto.sha256h2(<4 x i32> %hash_efgh, <4 x i32> %hash_abcd, <4 x i32> %wk)
122153
ret <4 x i32> %res
123154
}
124155

125156
define <4 x i32> @test_sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7) {
126157
; CHECK-LABEL: test_sha256su0:
127-
; CHECK: sha256su0.4s v0, v1
158+
; CHECK: // %bb.0:
159+
; CHECK-NEXT: sha256su0.4s v0, v1
160+
; CHECK-NEXT: ret
128161
%res = call <4 x i32> @llvm.aarch64.crypto.sha256su0(<4 x i32> %w0_3, <4 x i32> %w4_7)
129162
ret <4 x i32> %res
130163
}
131164

132165
define <4 x i32> @test_sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15) {
133166
; CHECK-LABEL: test_sha256su1:
134-
; CHECK: sha256su1.4s v0, v1, v2
167+
; CHECK: // %bb.0:
168+
; CHECK-NEXT: sha256su1.4s v0, v1, v2
169+
; CHECK-NEXT: ret
135170
%res = call <4 x i32> @llvm.aarch64.crypto.sha256su1(<4 x i32> %w0_3, <4 x i32> %w8_11, <4 x i32> %w12_15)
136171
ret <4 x i32> %res
137172
}
173+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
174+
; CHECK-GI: {{.*}}
175+
; CHECK-SD: {{.*}}

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