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[SLP][NFC]Cleanup undefs and the whole test, NFC
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‎llvm/test/Transforms/SLPVectorizer/X86/pr35497.ll

Lines changed: 76 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -8,119 +8,134 @@
88
%"class.3" = type { %"struct.1", i64 }
99
%"struct.1" = type { [8 x i64] }
1010

11-
$_ZN1C10SwitchModeEv = comdat any
12-
1311
; Function Attrs: uwtable
14-
define void @_ZN1C10SwitchModeEv() local_unnamed_addr #0 comdat align 2 {
12+
define void @_ZN1C10SwitchModeEv(ptr %p, i64 %c) {
1513
; SSE-LABEL: @_ZN1C10SwitchModeEv(
1614
; SSE-NEXT: for.body.lr.ph.i:
17-
; SSE-NEXT: [[OR_1:%.*]] = or i64 undef, 1
18-
; SSE-NEXT: store i64 [[OR_1]], ptr undef, align 8
19-
; SSE-NEXT: [[FOO_3:%.*]] = load i64, ptr undef, align 8
20-
; SSE-NEXT: [[FOO_2:%.*]] = getelementptr inbounds [[CLASS_1:%.*]], ptr undef, i64 0, i32 0, i32 0, i32 0, i32 0, i64 1
15+
; SSE-NEXT: [[BAR5:%.*]] = or i64 [[C:%.*]], 1
16+
; SSE-NEXT: store i64 [[BAR5]], ptr [[FOO_2:%.*]], align 8
2117
; SSE-NEXT: [[FOO_4:%.*]] = load i64, ptr [[FOO_2]], align 8
22-
; SSE-NEXT: [[BAR5:%.*]] = load i64, ptr undef, align 8
23-
; SSE-NEXT: [[AND_2:%.*]] = and i64 [[OR_1]], [[FOO_3]]
18+
; SSE-NEXT: [[FOO_3:%.*]] = getelementptr inbounds [[CLASS_1:%.*]], ptr [[FOO_2]], i64 0, i32 0, i32 0, i32 0, i32 0, i64 1
19+
; SSE-NEXT: [[FOO_5:%.*]] = load i64, ptr [[FOO_3]], align 8
20+
; SSE-NEXT: [[BAR6:%.*]] = load i64, ptr [[FOO_2]], align 8
2421
; SSE-NEXT: [[AND_1:%.*]] = and i64 [[BAR5]], [[FOO_4]]
25-
; SSE-NEXT: store i64 [[AND_2]], ptr undef, align 8
26-
; SSE-NEXT: [[BAR4:%.*]] = getelementptr inbounds [[CLASS_2:%.*]], ptr undef, i64 0, i32 0, i32 0, i32 0, i64 1
27-
; SSE-NEXT: store i64 [[AND_1]], ptr [[BAR4]], align 8
22+
; SSE-NEXT: [[AND_2:%.*]] = and i64 [[BAR6]], [[FOO_5]]
23+
; SSE-NEXT: store i64 [[AND_1]], ptr [[FOO_2]], align 8
24+
; SSE-NEXT: [[BAR4:%.*]] = getelementptr inbounds [[CLASS_2:%.*]], ptr [[FOO_2]], i64 0, i32 0, i32 0, i32 0, i64 1
25+
; SSE-NEXT: store i64 [[AND_2]], ptr [[BAR4]], align 8
2826
; SSE-NEXT: ret void
2927
;
3028
; AVX-LABEL: @_ZN1C10SwitchModeEv(
3129
; AVX-NEXT: for.body.lr.ph.i:
32-
; AVX-NEXT: [[OR_1:%.*]] = or i64 undef, 1
33-
; AVX-NEXT: store i64 [[OR_1]], ptr undef, align 8
34-
; AVX-NEXT: [[BAR5:%.*]] = load i64, ptr undef, align 8
35-
; AVX-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr undef, align 8
30+
; AVX-NEXT: [[OR_1:%.*]] = or i64 [[C:%.*]], 1
31+
; AVX-NEXT: store i64 [[OR_1]], ptr [[P:%.*]], align 8
32+
; AVX-NEXT: [[BAR5:%.*]] = load i64, ptr [[P]], align 8
33+
; AVX-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr [[P]], align 8
3634
; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> poison, i64 [[OR_1]], i32 0
3735
; AVX-NEXT: [[TMP2:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[BAR5]], i32 1
3836
; AVX-NEXT: [[TMP3:%.*]] = and <2 x i64> [[TMP2]], [[TMP0]]
39-
; AVX-NEXT: store <2 x i64> [[TMP3]], ptr undef, align 8
37+
; AVX-NEXT: store <2 x i64> [[TMP3]], ptr [[P]], align 8
4038
; AVX-NEXT: ret void
4139
;
4240
for.body.lr.ph.i:
43-
%or.1 = or i64 undef, 1
44-
store i64 %or.1, ptr undef, align 8
45-
%foo.3 = load i64, ptr undef, align 8
46-
%foo.2 = getelementptr inbounds %class.1, ptr undef, i64 0, i32 0, i32 0, i32 0, i32 0, i64 1
41+
%or.1 = or i64 %c, 1
42+
store i64 %or.1, ptr %p, align 8
43+
%foo.3 = load i64, ptr %p, align 8
44+
%foo.2 = getelementptr inbounds %class.1, ptr %p, i64 0, i32 0, i32 0, i32 0, i32 0, i64 1
4745
%foo.4 = load i64, ptr %foo.2, align 8
48-
%bar5 = load i64, ptr undef, align 8
46+
%bar5 = load i64, ptr %p, align 8
4947
%and.2 = and i64 %or.1, %foo.3
5048
%and.1 = and i64 %bar5, %foo.4
51-
store i64 %and.2, ptr undef, align 8
52-
%bar4 = getelementptr inbounds %class.2, ptr undef, i64 0, i32 0, i32 0, i32 0, i64 1
49+
store i64 %and.2, ptr %p, align 8
50+
%bar4 = getelementptr inbounds %class.2, ptr %p, i64 0, i32 0, i32 0, i32 0, i64 1
5351
store i64 %and.1, ptr %bar4, align 8
5452
ret void
5553
}
5654

5755
; Function Attrs: norecurse nounwind uwtable
58-
define void @pr35497() local_unnamed_addr #0 {
56+
define void @pr35497(ptr %p, i64 %c) {
5957
; SSE-LABEL: @pr35497(
6058
; SSE-NEXT: entry:
61-
; SSE-NEXT: [[TMP0:%.*]] = load i64, ptr undef, align 1
62-
; SSE-NEXT: [[ADD:%.*]] = add i64 undef, undef
63-
; SSE-NEXT: store i64 [[ADD]], ptr undef, align 1
64-
; SSE-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds [0 x i64], ptr undef, i64 0, i64 4
65-
; SSE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> <i64 poison, i64 undef>, i64 [[TMP0]], i32 0
66-
; SSE-NEXT: [[TMP2:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 2)
67-
; SSE-NEXT: [[TMP3:%.*]] = and <2 x i64> [[TMP2]], splat (i64 20)
68-
; SSE-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> poison, <2 x i32> <i32 1, i32 0>
69-
; SSE-NEXT: [[TMP5:%.*]] = add nuw nsw <2 x i64> [[TMP4]], zeroinitializer
70-
; SSE-NEXT: store <2 x i64> [[TMP5]], ptr undef, align 1
71-
; SSE-NEXT: [[TMP6:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> poison, <2 x i32> <i32 1, i32 poison>
72-
; SSE-NEXT: [[TMP7:%.*]] = insertelement <2 x i64> [[TMP6]], i64 [[ADD]], i32 1
73-
; SSE-NEXT: [[TMP8:%.*]] = shl <2 x i64> [[TMP7]], splat (i64 2)
74-
; SSE-NEXT: [[TMP9:%.*]] = and <2 x i64> [[TMP8]], splat (i64 20)
75-
; SSE-NEXT: [[TMP10:%.*]] = lshr <2 x i64> [[TMP5]], splat (i64 6)
76-
; SSE-NEXT: [[TMP11:%.*]] = add nuw nsw <2 x i64> [[TMP9]], [[TMP10]]
77-
; SSE-NEXT: store <2 x i64> [[TMP11]], ptr [[ARRAYIDX2_2]], align 1
59+
; SSE-NEXT: [[TMP0:%.*]] = load i64, ptr [[P:%.*]], align 1
60+
; SSE-NEXT: [[AND:%.*]] = shl i64 [[TMP0]], 2
61+
; SSE-NEXT: [[SHL:%.*]] = and i64 [[AND]], 20
62+
; SSE-NEXT: [[ADD:%.*]] = add i64 [[C:%.*]], [[C]]
63+
; SSE-NEXT: store i64 [[ADD]], ptr [[P]], align 1
64+
; SSE-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr inbounds [0 x i64], ptr [[P]], i64 0, i64 5
65+
; SSE-NEXT: [[AND_1:%.*]] = shl i64 [[C]], 2
66+
; SSE-NEXT: [[SHL_1:%.*]] = and i64 [[AND_1]], 20
67+
; SSE-NEXT: [[SHR_1:%.*]] = lshr i64 [[C]], 6
68+
; SSE-NEXT: [[ADD_1:%.*]] = add nuw nsw i64 [[SHL]], [[SHR_1]]
69+
; SSE-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds [0 x i64], ptr [[P]], i64 0, i64 4
70+
; SSE-NEXT: [[SHR_2:%.*]] = lshr i64 [[C]], 6
71+
; SSE-NEXT: [[ADD_2:%.*]] = add nuw nsw i64 [[SHL_1]], [[SHR_2]]
72+
; SSE-NEXT: [[AND_4:%.*]] = shl i64 [[ADD]], 2
73+
; SSE-NEXT: [[SHL_4:%.*]] = and i64 [[AND_4]], 20
74+
; SSE-NEXT: [[ARRAYIDX2_5:%.*]] = getelementptr inbounds [0 x i64], ptr [[P]], i64 0, i64 1
75+
; SSE-NEXT: store i64 [[ADD_1]], ptr [[ARRAYIDX2_5]], align 1
76+
; SSE-NEXT: [[AND_5:%.*]] = shl nuw nsw i64 [[ADD_1]], 2
77+
; SSE-NEXT: [[SHL_5:%.*]] = and i64 [[AND_5]], 20
78+
; SSE-NEXT: [[SHR_5:%.*]] = lshr i64 [[ADD_1]], 6
79+
; SSE-NEXT: [[ADD_5:%.*]] = add nuw nsw i64 [[SHL_4]], [[SHR_5]]
80+
; SSE-NEXT: store i64 [[ADD_5]], ptr [[ARRAYIDX2_1]], align 1
81+
; SSE-NEXT: store i64 [[ADD_2]], ptr [[P]], align 1
82+
; SSE-NEXT: [[SHR_6:%.*]] = lshr i64 [[ADD_2]], 6
83+
; SSE-NEXT: [[ADD_6:%.*]] = add nuw nsw i64 [[SHL_5]], [[SHR_6]]
84+
; SSE-NEXT: store i64 [[ADD_6]], ptr [[ARRAYIDX2_2]], align 1
7885
; SSE-NEXT: ret void
7986
;
8087
; AVX-LABEL: @pr35497(
8188
; AVX-NEXT: entry:
82-
; AVX-NEXT: [[TMP0:%.*]] = load i64, ptr undef, align 1
83-
; AVX-NEXT: [[ADD:%.*]] = add i64 undef, undef
84-
; AVX-NEXT: store i64 [[ADD]], ptr undef, align 1
85-
; AVX-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds [0 x i64], ptr undef, i64 0, i64 4
86-
; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> <i64 undef, i64 poison>, i64 [[TMP0]], i32 1
89+
; AVX-NEXT: [[TMP0:%.*]] = load i64, ptr [[P:%.*]], align 1
90+
; AVX-NEXT: [[TMP5:%.*]] = insertelement <2 x i64> poison, i64 [[C:%.*]], i32 0
91+
; AVX-NEXT: [[TMP11:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> poison, <2 x i32> zeroinitializer
92+
; AVX-NEXT: [[TMP13:%.*]] = lshr <2 x i64> [[TMP11]], splat (i64 6)
93+
; AVX-NEXT: [[ARRAYIDX2_2:%.*]] = getelementptr inbounds [0 x i64], ptr [[P]], i64 0, i64 4
94+
; AVX-NEXT: [[ARRAYIDX2_5:%.*]] = getelementptr inbounds [0 x i64], ptr [[P]], i64 0, i64 1
95+
; AVX-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP11]], i64 [[TMP0]], i32 1
8796
; AVX-NEXT: [[TMP2:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 2)
8897
; AVX-NEXT: [[TMP3:%.*]] = and <2 x i64> [[TMP2]], splat (i64 20)
89-
; AVX-NEXT: [[TMP4:%.*]] = add nuw nsw <2 x i64> [[TMP3]], zeroinitializer
90-
; AVX-NEXT: store <2 x i64> [[TMP4]], ptr undef, align 1
91-
; AVX-NEXT: [[TMP5:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> poison, <2 x i32> <i32 1, i32 poison>
92-
; AVX-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[TMP5]], i64 [[ADD]], i32 1
98+
; AVX-NEXT: [[TMP14:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP1]], <2 x i32> <i32 1, i32 2>
99+
; AVX-NEXT: [[TMP16:%.*]] = shufflevector <2 x i64> [[TMP13]], <2 x i64> [[TMP14]], <2 x i32> <i32 1, i32 3>
100+
; AVX-NEXT: [[TMP6:%.*]] = add <2 x i64> [[TMP14]], [[TMP16]]
101+
; AVX-NEXT: [[TMP17:%.*]] = extractelement <2 x i64> [[TMP6]], i32 1
102+
; AVX-NEXT: store i64 [[TMP17]], ptr [[P]], align 1
103+
; AVX-NEXT: [[TMP4:%.*]] = add nuw nsw <2 x i64> [[TMP3]], [[TMP13]]
104+
; AVX-NEXT: [[TMP12:%.*]] = extractelement <2 x i64> [[TMP6]], i32 0
105+
; AVX-NEXT: store i64 [[TMP12]], ptr [[ARRAYIDX2_5]], align 1
93106
; AVX-NEXT: [[TMP7:%.*]] = shl <2 x i64> [[TMP6]], splat (i64 2)
94107
; AVX-NEXT: [[TMP8:%.*]] = and <2 x i64> [[TMP7]], splat (i64 20)
108+
; AVX-NEXT: [[TMP15:%.*]] = extractelement <2 x i64> [[TMP4]], i32 0
109+
; AVX-NEXT: store i64 [[TMP15]], ptr [[P]], align 1
95110
; AVX-NEXT: [[TMP9:%.*]] = lshr <2 x i64> [[TMP4]], splat (i64 6)
96111
; AVX-NEXT: [[TMP10:%.*]] = add nuw nsw <2 x i64> [[TMP8]], [[TMP9]]
97112
; AVX-NEXT: store <2 x i64> [[TMP10]], ptr [[ARRAYIDX2_2]], align 1
98113
; AVX-NEXT: ret void
99114
;
100115
entry:
101-
%0 = load i64, ptr undef, align 1
116+
%0 = load i64, ptr %p, align 1
102117
%and = shl i64 %0, 2
103118
%shl = and i64 %and, 20
104-
%add = add i64 undef, undef
105-
store i64 %add, ptr undef, align 1
106-
%arrayidx2.1 = getelementptr inbounds [0 x i64], ptr undef, i64 0, i64 5
107-
%and.1 = shl i64 undef, 2
119+
%add = add i64 %c, %c
120+
store i64 %add, ptr %p, align 1
121+
%arrayidx2.1 = getelementptr inbounds [0 x i64], ptr %p, i64 0, i64 5
122+
%and.1 = shl i64 %c, 2
108123
%shl.1 = and i64 %and.1, 20
109-
%shr.1 = lshr i64 undef, 6
124+
%shr.1 = lshr i64 %c, 6
110125
%add.1 = add nuw nsw i64 %shl, %shr.1
111-
%arrayidx2.2 = getelementptr inbounds [0 x i64], ptr undef, i64 0, i64 4
112-
%shr.2 = lshr i64 undef, 6
126+
%arrayidx2.2 = getelementptr inbounds [0 x i64], ptr %p, i64 0, i64 4
127+
%shr.2 = lshr i64 %c, 6
113128
%add.2 = add nuw nsw i64 %shl.1, %shr.2
114129
%and.4 = shl i64 %add, 2
115130
%shl.4 = and i64 %and.4, 20
116-
%arrayidx2.5 = getelementptr inbounds [0 x i64], ptr undef, i64 0, i64 1
131+
%arrayidx2.5 = getelementptr inbounds [0 x i64], ptr %p, i64 0, i64 1
117132
store i64 %add.1, ptr %arrayidx2.5, align 1
118133
%and.5 = shl nuw nsw i64 %add.1, 2
119134
%shl.5 = and i64 %and.5, 20
120135
%shr.5 = lshr i64 %add.1, 6
121136
%add.5 = add nuw nsw i64 %shl.4, %shr.5
122137
store i64 %add.5, ptr %arrayidx2.1, align 1
123-
store i64 %add.2, ptr undef, align 1
138+
store i64 %add.2, ptr %p, align 1
124139
%shr.6 = lshr i64 %add.2, 6
125140
%add.6 = add nuw nsw i64 %shl.5, %shr.6
126141
store i64 %add.6, ptr %arrayidx2.2, align 1

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