[ATfE] Use new bootcode in llvmlibc-support (#394)

This eliminates the need for vector.c, as this is linked in the
bootcode. This still needs a bit of work to be bulletproof, but for the
samples, it works fine.

Author: saturn691

arm-software/embedded/llvmlibc-samples/src/baremetal-semihosting-llvmlibc/make.bat

@@ -40,6 +40,6 @@ if exist hello.hex del /q hello.hex
 @exit /B 1
 
 :build_fn
-%BIN_PATH%\clang.exe --config=llvmlibc.cfg --target=armv6m-none-eabi -mfloat-abi=soft -march=armv6m -mfpu=none -nostartfiles -lcrt0-semihost -lsemihost -fno-exceptions -fno-rtti -g -T microbit-llvmlibc.ld -lm -o hello.elf hello.c vector.c
+%BIN_PATH%\clang.exe --config=llvmlibc.cfg --target=armv6m-none-eabi -mfloat-abi=soft -march=armv6m -mfpu=none -nostartfiles -lcrt0-semihost -lsemihost -fno-exceptions -fno-rtti -g -T microbit-llvmlibc.ld -lm -o hello.elf hello.c
 %BIN_PATH%\llvm-objcopy.exe -O ihex hello.elf hello.hex
 @exit /B

arm-software/embedded/llvmlibc-samples/src/baremetal-semihosting-llvmlibc/vector.c

@@ -10,8 +10,7 @@ include ../../Makefile.conf
 build: hello.elf
 
 hello.elf: *.cpp
-	$(BIN_PATH)/clang --config=llvmlibc.cfg $(MICROBIT_TARGET) -c *.c
-	$(BIN_PATH)/clang++ --config=llvmlibc.cfg $(MICROBIT_TARGET) $(CRT_SEMIHOST) -lm -g -T microbit-llvmlibc.ld *.o -o hello.elf $^
+	$(BIN_PATH)/clang++ --config=llvmlibc.cfg $(MICROBIT_TARGET) $(CRT_SEMIHOST) -lm -g -T microbit-llvmlibc.ld -o hello.elf $^
 
 %.hex: %.elf
 	$(BIN_PATH)/llvm-objcopy -O ihex $< $@

arm-software/embedded/llvmlibc-samples/src/cpp-baremetal-semihosting-llvmlibc/Makefile

@@ -40,7 +40,6 @@ if exist hello.hex del /q hello.hex
 @exit /B 1
 
 :build_fn
-%BIN_PATH%\clang.exe --config=llvmlibc.cfg --target=armv6m-none-eabi -mfloat-abi=soft -march=armv6m -mfpu=none -g -c vector.c
-%BIN_PATH%\clang++.exe --config=llvmlibc.cfg --target=armv6m-none-eabi -mfloat-abi=soft -march=armv6m -mfpu=none -nostartfiles -lcrt0-semihost -lsemihost -fno-exceptions -fno-rtti -g -T microbit-llvmlibc.ld -lm -o hello.elf hello.cpp vector.o
+%BIN_PATH%\clang++.exe --config=llvmlibc.cfg --target=armv6m-none-eabi -mfloat-abi=soft -march=armv6m -mfpu=none -nostartfiles -lcrt0-semihost -lsemihost -fno-exceptions -fno-rtti -g -T microbit-llvmlibc.ld -lm -o hello.elf hello.cpp
 %BIN_PATH%\llvm-objcopy.exe -O ihex hello.elf hello.hex
 @exit /B

arm-software/embedded/llvmlibc-samples/src/cpp-baremetal-semihosting-llvmlibc/make.bat

@@ -6,7 +6,7 @@
 #
 
 add_library(crt0 STATIC
-  crt0.c
+  bootcode.cpp
 )
 
 target_include_directories(crt0 PRIVATE
@@ -17,7 +17,7 @@ target_include_directories(crt0 PRIVATE
 # This is the exact same implementation, kept for backwards compatibility with
 # picolibc in testing.
 add_library(crt0-semihost STATIC
-  crt0.c
+  bootcode.cpp
 )
 
 target_include_directories(crt0-semihost PRIVATE

arm-software/embedded/llvmlibc-samples/src/cpp-baremetal-semihosting-llvmlibc/vector.c

@@ -0,0 +1,90 @@
+//
+// Copyright (c) 2025, Arm Limited and affiliates.
+//
+// Part of the Arm Toolchain project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+
+#include <stdint.h>
+
+#if __ARM_ARCH_PROFILE == 'A' || __ARM_ARCH_PROFILE == 'R'
+#include "exceptions_a.h"
+#include "memory_a.h"
+#include "misc_a.h"
+#include "system_registers_a.h"
+#elif __ARM_ARCH_PROFILE == 'M'
+#include "exceptions_m.h"
+#include "memory_m.h"
+#include "misc_m.h"
+#include "system_registers_m.h"
+#endif
+
+using namespace bootcode;
+
+int main(int argc, const char **argv);
+extern "C" void __libc_init_array();
+extern "C" void _platform_init();
+
+// Required for exit() on baremetal
+// TODO: This is temporary, remove once implemented upstream
+extern "C" [[gnu::weak]] void __cxa_finalize(void *) {}
+
+extern char __data_source[];
+extern char __data_start[];
+extern char __data_size[];
+extern char __bss_start[];
+extern char __bss_size[];
+
+#ifdef __ARM_FEATURE_PAUTH
+// Disable pointer authentication, as it isn't enabled until misc::setup meaning
+// the PAC at the beginning would do nothing so the AUT at the end would fail.
+__attribute__((target("branch-protection=none")))
+#endif
+extern "C" void __startup() {
+  exceptions::setup();
+  memory::setup();
+  misc::setup();
+
+  // Perform the equivalent of scatterloading
+  memcpy(__data_start, __data_source, (uintptr_t)__data_size);
+  memset(__bss_start, '\0', (uintptr_t)__bss_size);
+
+  memory::enable_cache();
+  __libc_init_array();
+  _platform_init();
+  exit(main(0, 0));
+}
+
+// The entry point sets sp and branches to the main startup function.
+#ifdef __ARM_ARCH_ISA_ARM
+// If the target supports the A32 instruction set then the entry point has to
+// use it.
+__attribute__((target("arm")))
+#endif
+__attribute__((naked)) extern "C" void _start() {
+#if __ARM_ARCH_PROFILE != 'M' && __ARM_ARCH >= 8 && !defined(__ARM_ARCH_ISA_A64)
+  // Check if we're in hypervisor mode
+  asm("mrs r0, CPSR\n\t"
+      "and r0, r0, #0x1f\n\t"
+      "cmp r0, #0x1a\n\t"
+      "bne after_mode_switch"
+      :
+      :
+      : "r0");
+  // If so switch to svc mode, which is what we would have started execution in
+  // if we didn't have hypervisor mode.
+  asm("adr r0, after_mode_switch\n\t"
+      "msr ELR_hyp, r0"
+      :
+      :
+      : "r0");
+  asm("msr SPSR_hyp, %0" : : "r"(0x13));
+  asm("eret");
+  asm("after_mode_switch:");
+#endif
+
+  // Configured through linker script defined symbols
+  asm("mov sp, %0" : : "r"(&__stack));
+  asm("bl %0" : : "X"(__startup));
+}

arm-software/embedded/llvmlibc-support/crt0/CMakeLists.txt

@@ -0,0 +1,120 @@
+//
+// Copyright (c) 2025, Arm Limited and affiliates.
+//
+// Part of the Arm Toolchain project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+
+// ARMv7-A exception handling
+
+#ifndef BOOTCODE_EXCEPTIONS_7A_H
+#define BOOTCODE_EXCEPTIONS_7A_H
+
+#include "exceptions_common.h"
+#include "system_registers_a.h"
+#include <stdlib.h>
+
+namespace bootcode {
+namespace exceptions {
+
+using namespace sysreg;
+
+EXFN_ATTR void handle_reset() {
+  print_str("CPU Exception: Reset\n");
+  abort();
+}
+
+EXFN_ATTR void handle_undefined() {
+  unsigned pc_val = __arm_rsr("ELR_hyp");
+  unsigned instr = *(unsigned *)pc_val;
+  print_str("CPU Exception: Undefined Instruction\n");
+  print_str("  PC = ");
+  print_hex(pc_val);
+  print_str("\n");
+  print_str("  Instruction = ");
+  print_hex(instr);
+  print_str("\n");
+  abort();
+}
+
+EXFN_ATTR void handle_svc_hyp_smc() {
+  print_str("CPU Exception: SVC, HVC or SMC\n");
+  print_str("  PC = ");
+  print_hex(__arm_rsr("ELR_hyp"));
+  print_str("\n");
+  abort();
+}
+
+EXFN_ATTR void handle_prefetch_abort() {
+  print_str("CPU Exception: Prefetch Abort\n");
+  print_str("  PC = ");
+  print_hex(__arm_rsr("ELR_hyp"));
+  print_str("\n");
+  print_str("  IFSR = 0x%08x\n");
+  print_str("  IFAR = 0x%08x\n");
+  abort();
+}
+
+EXFN_ATTR void handle_data_abort() {
+  print_str("CPU Exception: Data Abort\n");
+  print_str("  PC = ");
+  print_hex(__arm_rsr("ELR_hyp"));
+  print_str("\n");
+  print_str("  DFSR = 0x%08x\n");
+  print_str("  DFAR = 0x%08x\n");
+  abort();
+}
+
+EXFN_ATTR void handle_hyp_trap() {
+  print_str("CPU Exception: Hypervisor Trap\n");
+  print_str("  PC = ");
+  print_hex(__arm_rsr("ELR_hyp"));
+  print_str("\n");
+  print_str("  HSR = 0x%08x\n");
+  abort();
+}
+
+EXFN_ATTR void handle_irq() {
+  print_str("CPU Exception: IRQ\n");
+  print_str("  PC = ");
+  print_hex(__arm_rsr("ELR_hyp"));
+  print_str("\n");
+  abort();
+}
+
+EXFN_ATTR void handle_fiq() {
+  print_str("CPU Exception: FIQ\n");
+  print_str("  PC = ");
+  print_hex(__arm_rsr("ELR_hyp"));
+  print_str("\n");
+  abort();
+}
+
+// The AArch32 exception vector table has 8 entries, each of which is 4
+// bytes long, and contains code. The whole table must be 32-byte aligned.
+// The table may also be relocated, so we make it position-independent by
+// having a table of handler addresses and loading the address to pc.
+__attribute__((naked, section(".vectors"), aligned(32))) void vector_table() {
+  asm("LDR pc, [pc, #24]");
+  asm("LDR pc, [pc, #24]");
+  asm("LDR pc, [pc, #24]");
+  asm("LDR pc, [pc, #24]");
+  asm("LDR pc, [pc, #24]");
+  asm("LDR pc, [pc, #24]");
+  asm("LDR pc, [pc, #24]");
+  asm("LDR pc, [pc, #24]");
+  asm(".word %0" : : "X"(handle_reset));
+  asm(".word %0" : : "X"(handle_undefined));
+  asm(".word %0" : : "X"(handle_svc_hyp_smc));
+  asm(".word %0" : : "X"(handle_prefetch_abort));
+  asm(".word %0" : : "X"(handle_data_abort));
+  asm(".word %0" : : "X"(handle_hyp_trap));
+  asm(".word %0" : : "X"(handle_irq));
+  asm(".word %0" : : "X"(handle_fiq));
+}
+
+} // namespace exceptions
+} // namespace bootcode
+
+#endif // BOOTCODE_EXCEPTIONS_7A_H