@@ -706,7 +706,6 @@ def V_CVT_F16_F8_Fake16_Profile : VOP3_Profile_Fake16<V_CVT_F16_F8_Profile>;
706706
707707let SubtargetPredicate = isGFX12Plus, OtherPredicates = [HasFP8ConversionInsts],
708708 mayRaiseFPException = 0, SchedRW = [WriteFloatCvt] in {
709- // FIXME: This differs from downstream due to changes that haven't been upstreamed yet.
710709 let SubtargetPredicate = isGFX12PlusNot12_50 in
711710 defm V_CVT_F32_FP8_OP_SEL : VOP1Inst<"v_cvt_f32_fp8_op_sel", VOPProfile_Base_CVT_F_F8_ByteSel<f32>>;
712711 let SubtargetPredicate = isGFX125xOnly in
@@ -731,7 +730,6 @@ class Cvt_F_F8_Pat_ByteSel<SDPatternOperator node, VOP3_Pseudo inst, bit HasOpSe
731730>;
732731
733732let OtherPredicates = [HasFP8ConversionInsts] in {
734- // FIXME: This differs from downstream due to changes that haven't been upstreamed yet.
735733 let SubtargetPredicate = isGFX12PlusNot12_50 in
736734 def : Cvt_F_F8_Pat_ByteSel<int_amdgcn_cvt_f32_fp8, V_CVT_F32_FP8_OP_SEL_e64>;
737735 let SubtargetPredicate = isGFX125xOnly in {
@@ -740,7 +738,6 @@ let OtherPredicates = [HasFP8ConversionInsts] in {
740738 def : GCNPat<(int_amdgcn_cvt_f32_fp8_e5m3 i32:$src0, timm:$byte_sel),
741739 (V_CVT_F32_FP8_gfx1250_e64 $src0, DSTCLAMP.ENABLE, (as_i32timm $byte_sel))>;
742740 }
743- // FIXME: This differs from downstream due to changes that haven't been upstreamed yet.
744741 let SubtargetPredicate = isGFX12Plus in
745742 def : Cvt_F_F8_Pat_ByteSel<int_amdgcn_cvt_f32_bf8, V_CVT_F32_BF8_OP_SEL_e64>;
746743}
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