[M68k] Fix encoding of CAS instructions (#154481)

The immediate part of memory operands was not encoded.

Author: s-barannikov

llvm/lib/Target/M68k/M68kInstrAtomics.td

@@ -67,7 +67,8 @@ class MxCASARIDOp<bits<2> size_encoding, MxType type>
              "cas."#type.Prefix#" $dc, $du, $mem"> {
   let Inst = (ascend
                 (descend 0b00001, size_encoding, 0b011, MxEncAddrMode_p<"mem">.EA),
-                (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
+                (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3)),
+                MxEncAddrMode_p<"mem">.Supplement
               );
   let Constraints = "$out = $dc";
   let mayLoad = 1;
@@ -84,7 +85,8 @@ class MxCASARIIOp<bits<2> size_encoding, MxType type>
              "cas."#type.Prefix#" $dc, $du, $mem"> {
   let Inst = (ascend
                 (descend 0b00001, size_encoding, 0b011, MxEncAddrMode_f<"mem">.EA),
-                (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
+                (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3)),
+                MxEncAddrMode_f<"mem">.Supplement
               );
   let Constraints = "$out = $dc";
   let mayLoad = 1;
@@ -100,8 +102,9 @@ class MxCASALOp<bits<2> size_encoding, MxType type>
              (ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxAL"#type.Size):$mem),
              "cas."#type.Prefix#" $dc, $du, $mem"> {
   let Inst = (ascend
-                (descend 0b00001, size_encoding, 0b011, MxEncAddrMode_abs<"mem">.EA),
-                (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
+                (descend 0b00001, size_encoding, 0b011, MxEncAddrMode_abs<"mem", true>.EA),
+                (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3)),
+                MxEncAddrMode_abs<"mem", true>.Supplement
               );
   let Constraints = "$out = $dc";
   let mayLoad = 1;

llvm/test/MC/M68k/Atomics/cas.s

@@ -15,39 +15,39 @@ cas.l %d6, %d7, (%a4)
 
 ; Address Register Indirect with Displacement
 ; CHECK: cas.b %d3, %d2, (5,%a2)
-; CHECK-SAME: ; encoding: [0x0a,0xea,0x00,0x83]
+; CHECK-SAME: ; encoding: [0x0a,0xea,0x00,0x83,0x00,0x05]
 cas.b %d3, %d2, (5, %a2)
 
 ; CHECK: cas.w %d4, %d5, (6,%a3)
-; CHECK-SAME: ; encoding: [0x0c,0xeb,0x01,0x44]
+; CHECK-SAME: ; encoding: [0x0c,0xeb,0x01,0x44,0x00,0x06]
 cas.w %d4, %d5, (6, %a3)
 
 ; CHECK: cas.l %d6, %d7, (7,%a4)
-; CHECK-SAME: ; encoding: [0x0e,0xec,0x01,0xc6]
+; CHECK-SAME: ; encoding: [0x0e,0xec,0x01,0xc6,0x00,0x07]
 cas.l %d6, %d7, (7, %a4)
 
 ; Address Register Indirect with Index (Scale = 1)
 ; CHECK: cas.b %d3, %d2, (5,%a2,%d1)
-; CHECK-SAME: ; encoding: [0x0a,0xf2,0x00,0x83]
+; CHECK-SAME: ; encoding: [0x0a,0xf2,0x00,0x83,0x18,0x05]
 cas.b %d3, %d2, (5, %a2, %d1)
 
 ; CHECK: cas.w %d4, %d5, (6,%a3,%d1)
-; CHECK-SAME: ; encoding: [0x0c,0xf3,0x01,0x44]
+; CHECK-SAME: ; encoding: [0x0c,0xf3,0x01,0x44,0x18,0x06]
 cas.w %d4, %d5, (6, %a3, %d1)
 
 ; CHECK: cas.l %d6, %d7, (7,%a4,%d1)
-; CHECK-SAME: ; encoding: [0x0e,0xf4,0x01,0xc6]
+; CHECK-SAME: ; encoding: [0x0e,0xf4,0x01,0xc6,0x18,0x07]
 cas.l %d6, %d7, (7, %a4, %d1)
 
 ; Absolute Long Address
 ; CHECK: cas.b %d3, %d2, $ffffffffffffffff
-; CHECK-SAME: ; encoding: [0x0a,0xf8,0x00,0x83]
+; CHECK-SAME: ; encoding: [0x0a,0xf9,0x00,0x83,0xff,0xff,0xff,0xff]
 cas.b %d3, %d2, $ffffffffffffffff
 
 ; CHECK: cas.w %d4, %d5, $ffffffffffffffff
-; CHECK-SAME: ; encoding: [0x0c,0xf8,0x01,0x44]
+; CHECK-SAME: ; encoding: [0x0c,0xf9,0x01,0x44,0xff,0xff,0xff,0xff]
 cas.w %d4, %d5, $ffffffffffffffff
 
 ; CHECK: cas.l %d6, %d7, $ffffffffffffffff
-; CHECK-SAME: ; encoding: [0x0e,0xf8,0x01,0xc6]
+; CHECK-SAME: ; encoding: [0x0e,0xf9,0x01,0xc6,0xff,0xff,0xff,0xff]
 cas.l %d6, %d7, $ffffffffffffffff