@@ -38,7 +38,9 @@ static cl::opt<bool>
3838 BranchRelaxation (" sparc-enable-branch-relax" , cl::Hidden, cl::init(true ),
3939 cl::desc(" Relax out of range conditional branches" ));
4040
41- static std::string computeDataLayout (const Triple &T, bool is64Bit) {
41+ static std::string computeDataLayout (const Triple &T) {
42+ const bool is64Bit = T.isSPARC64 ();
43+
4244 // Sparc is typically big endian, but some are little.
4345 std::string Ret = T.getArch () == Triple::sparcel ? " e" : " E" ;
4446 Ret += " -m:e" ;
@@ -107,15 +109,14 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
107109 const TargetOptions &Options,
108110 std::optional<Reloc::Model> RM,
109111 std::optional<CodeModel::Model> CM,
110- CodeGenOptLevel OL, bool JIT,
111- bool is64bit)
112+ CodeGenOptLevel OL, bool JIT)
112113 : CodeGenTargetMachineImpl(
113- T, computeDataLayout(TT, is64bit ), TT, CPU, FS, Options,
114+ T, computeDataLayout(TT), TT, CPU, FS, Options,
114115 getEffectiveRelocModel(RM),
115- getEffectiveSparcCodeModel(CM, getEffectiveRelocModel(RM), is64bit,
116- JIT),
116+ getEffectiveSparcCodeModel(CM, getEffectiveRelocModel(RM),
117+ TT.isSPARC64(), JIT),
117118 OL),
118- TLOF(std::make_unique<SparcELFTargetObjectFile>()), is64Bit(is64bit) {
119+ TLOF(std::make_unique<SparcELFTargetObjectFile>()) {
119120 initAsmInfo ();
120121}
121122
@@ -148,8 +149,7 @@ SparcTargetMachine::getSubtargetImpl(const Function &F) const {
148149 // creation will depend on the TM and the code generation flags on the
149150 // function that reside in TargetOptions.
150151 resetTargetOptions (F);
151- I = std::make_unique<SparcSubtarget>(CPU, TuneCPU, FS, *this ,
152- this ->is64Bit );
152+ I = std::make_unique<SparcSubtarget>(CPU, TuneCPU, FS, *this );
153153 }
154154 return I.get ();
155155}
@@ -212,7 +212,7 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
212212 std::optional<Reloc::Model> RM,
213213 std::optional<CodeModel::Model> CM,
214214 CodeGenOptLevel OL, bool JIT)
215- : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false ) {}
215+ : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT) {}
216216
217217void SparcV9TargetMachine::anchor () { }
218218
@@ -222,7 +222,7 @@ SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
222222 std::optional<Reloc::Model> RM,
223223 std::optional<CodeModel::Model> CM,
224224 CodeGenOptLevel OL, bool JIT)
225- : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true ) {}
225+ : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT) {}
226226
227227void SparcelTargetMachine::anchor () {}
228228
@@ -232,4 +232,4 @@ SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
232232 std::optional<Reloc::Model> RM,
233233 std::optional<CodeModel::Model> CM,
234234 CodeGenOptLevel OL, bool JIT)
235- : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false ) {}
235+ : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT) {}
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