|
| 1 | +; REQUIRES: asserts |
| 2 | + |
| 3 | +; RUN: opt -passes=loop-vectorize -debug-only=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -disable-output %s 2>&1 | FileCheck %s |
| 4 | + |
| 5 | +define void @test_widen_metadata(ptr noalias %A, ptr noalias %B, i32 %n) { |
| 6 | +; CHECK-LABEL: Checking a loop in 'test_widen_metadata' |
| 7 | +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { |
| 8 | +; CHECK: <x1> vector loop: { |
| 9 | +; CHECK: vector.body: |
| 10 | +; CHECK: WIDEN ir<%lv> = load vp<{{.*}}> |
| 11 | +; CHECK: WIDEN-CAST ir<%conv> = sitofp ir<%lv> to float |
| 12 | +; CHECK: WIDEN ir<%mul> = fmul ir<%conv>, ir<2.000000e+00> |
| 13 | +; CHECK: WIDEN-CAST ir<%conv.back> = fptosi ir<%mul> to i32 |
| 14 | +; CHECK: WIDEN store vp<{{.*}}>, ir<%conv.back> |
| 15 | +; |
| 16 | +entry: |
| 17 | + br label %loop |
| 18 | + |
| 19 | +loop: |
| 20 | + %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] |
| 21 | + %gep.A = getelementptr inbounds i32, ptr %A, i32 %i |
| 22 | + %lv = load i32, ptr %gep.A, align 4, !tbaa !0, !range !6 |
| 23 | + %conv = sitofp i32 %lv to float, !fpmath !5 |
| 24 | + %mul = fmul float %conv, 2.0, !fpmath !5 |
| 25 | + %conv.back = fptosi float %mul to i32 |
| 26 | + %gep.B = getelementptr inbounds i32, ptr %B, i32 %i |
| 27 | + store i32 %conv.back, ptr %gep.B, align 4, !tbaa !0 |
| 28 | + %i.next = add i32 %i, 1 |
| 29 | + %cond = icmp eq i32 %i.next, %n |
| 30 | + br i1 %cond, label %exit, label %loop |
| 31 | + |
| 32 | +exit: |
| 33 | + ret void |
| 34 | +} |
| 35 | + |
| 36 | +declare float @llvm.sqrt.f32(float) |
| 37 | + |
| 38 | +define void @test_intrinsic_with_metadata(ptr noalias %A, ptr noalias %B, i32 %n) { |
| 39 | +; CHECK-LABEL: Checking a loop in 'test_intrinsic_with_metadata' |
| 40 | +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { |
| 41 | +; CHECK: <x1> vector loop: { |
| 42 | +; CHECK: vector.body: |
| 43 | +; CHECK: WIDEN ir<%lv> = load vp<{{.*}}> |
| 44 | +; CHECK: WIDEN-INTRINSIC ir<%sqrt> = call llvm.sqrt(ir<%lv>) |
| 45 | +; CHECK: WIDEN store vp<{{.*}}>, ir<%sqrt> |
| 46 | +; |
| 47 | +entry: |
| 48 | + br label %loop |
| 49 | + |
| 50 | +loop: |
| 51 | + %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] |
| 52 | + %gep.A = getelementptr inbounds float, ptr %A, i32 %i |
| 53 | + %lv = load float, ptr %gep.A, align 4, !tbaa !0 |
| 54 | + %sqrt = call float @llvm.sqrt.f32(float %lv), !fpmath !5 |
| 55 | + %gep.B = getelementptr inbounds float, ptr %B, i32 %i |
| 56 | + store float %sqrt, ptr %gep.B, align 4, !tbaa !0 |
| 57 | + %i.next = add i32 %i, 1 |
| 58 | + %cond = icmp eq i32 %i.next, %n |
| 59 | + br i1 %cond, label %exit, label %loop |
| 60 | + |
| 61 | +exit: |
| 62 | + ret void |
| 63 | +} |
| 64 | + |
| 65 | +define void @test_widen_with_multiple_metadata(ptr noalias %A, ptr noalias %B, i32 %n) { |
| 66 | +; CHECK-LABEL: Checking a loop in 'test_widen_with_multiple_metadata' |
| 67 | +; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' { |
| 68 | +; CHECK: <x1> vector loop: { |
| 69 | +; CHECK: vector.body: |
| 70 | +; CHECK: WIDEN ir<%lv> = load vp<{{.*}}> |
| 71 | +; CHECK: WIDEN-CAST ir<%conv> = sitofp ir<%lv> to float |
| 72 | +; CHECK: WIDEN ir<%mul> = fmul ir<%conv>, ir<2.000000e+00> |
| 73 | +; CHECK: WIDEN-CAST ir<%conv.back> = fptosi ir<%mul> to i32 |
| 74 | +; CHECK: WIDEN store vp<{{.*}}>, ir<%conv.back> |
| 75 | +; |
| 76 | +entry: |
| 77 | + br label %loop |
| 78 | + |
| 79 | +loop: |
| 80 | + %i = phi i32 [ 0, %entry ], [ %i.next, %loop ] |
| 81 | + %gep.A = getelementptr inbounds i32, ptr %A, i32 %i |
| 82 | + %lv = load i32, ptr %gep.A, align 4, !tbaa !0, !range !6 |
| 83 | + %conv = sitofp i32 %lv to float |
| 84 | + %mul = fmul float %conv, 2.0 |
| 85 | + %conv.back = fptosi float %mul to i32 |
| 86 | + %gep.B = getelementptr inbounds i32, ptr %B, i32 %i |
| 87 | + store i32 %conv.back, ptr %gep.B, align 4, !tbaa !0 |
| 88 | + %i.next = add i32 %i, 1 |
| 89 | + %cond = icmp eq i32 %i.next, %n |
| 90 | + br i1 %cond, label %exit, label %loop |
| 91 | + |
| 92 | +exit: |
| 93 | + ret void |
| 94 | +} |
| 95 | + |
| 96 | +!0 = !{!1, !1, i64 0} |
| 97 | +!1 = !{!"float", !2} |
| 98 | +!2 = !{!"root"} |
| 99 | +!5 = !{float 2.500000e+00} |
| 100 | +!6 = !{i32 0, i32 100} |
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