[RISCV] Add scheduling info for XSfvfnrclipxfqf instructions (#147586)

This patch adds scheduling data for the XSfvfnrclipxfqf instruction,
which narrows / clips FP32 data to INT8 according to value range
specified by a scalar register. Three new SchedReadWrites are
introduced.

Author: mshockwave

llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

@@ -177,7 +177,8 @@ class CustomSiFiveVMACC<bits<6> funct6, RISCVVFormat opv, string opcodestr>
 }
 
 class CustomSiFiveVFNRCLIP<bits<6> funct6, RISCVVFormat opv, string opcodestr>
-    : VALUVF<funct6, opv, opcodestr> {
+    : VALUVF<funct6, opv, opcodestr>,
+      SchedBinaryMC<"WriteSF_VFNRClipV", "ReadSF_VFNRClipV", "ReadSF_VFNRClipF"> {
   let Inst{6-0} = OPC_CUSTOM_2.Value;
 }
 
@@ -403,7 +404,10 @@ multiclass VPseudoSiFiveVFNRCLIP<string Constraint = "@earlyclobber $rd"> {
                                                        MxListVF4[i].vrclass,
                                                        FPR32, MxListW[i],
                                                        Constraint, /*sew*/0,
-                                                       UsesVXRM=0>;
+                                                       UsesVXRM=0>,
+                             SchedBinary<"WriteSF_VFNRClipV", "ReadSF_VFNRClipV",
+                                         "ReadSF_VFNRClipF",
+                                         MxListW[i].MX>;
 }
 
 let Predicates = [HasVendorXSfvcp] in {

llvm/lib/Target/RISCV/RISCVSchedAndes45.td

@@ -331,6 +331,7 @@ defm : UnsupportedSchedQ;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedV;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfnrclipxfqf;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;

llvm/lib/Target/RISCV/RISCVSchedGenericOOO.td

@@ -498,4 +498,5 @@ defm : UnsupportedSchedZfaWithQ;
 defm : UnsupportedSchedZvk;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfnrclipxfqf;
 }

llvm/lib/Target/RISCV/RISCVSchedMIPSP8700.td

@@ -274,5 +274,6 @@ defm : UnsupportedSchedZfhmin;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZabha;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfnrclipxfqf;
 defm : UnsupportedSchedZvk;
 }

llvm/lib/Target/RISCV/RISCVSchedRocket.td

@@ -263,5 +263,6 @@ defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZfhmin;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfnrclipxfqf;
 defm : UnsupportedSchedZvk;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

@@ -169,6 +169,20 @@ class SiFive7GetOrderedReductionCycles<string mx, int sew, int VLEN> {
   int c = !mul(6, VLUpperBound);
 }
 
+class SiFive7GetSiFiveVFNRClipCycles<string mx, int VLEN> {
+  int latency = !cond(
+    !eq(mx, "MF8"): 7,
+    !eq(mx, "MF4"): 8,
+    !eq(mx, "MF2"): 10,
+    !eq(mx, "M1"): 13,
+    !eq(mx, "M2"): 19,
+  );
+
+  defvar DLEN = !div(VLEN, 2);
+  int occupancy = SiFive7GetCyclesOnePerElement<mx, sew=!div(DLEN, 4),
+                                                VLEN=VLEN>.c;
+}
+
 class SiFive7FPLatencies {
   int BasicFP16ALU;
   int BasicFP32ALU;
@@ -1049,6 +1063,15 @@ multiclass SiFive7WriteResBase<int VLEN,
       }
     }
   }
+
+  foreach mx = !listremove(SchedMxListW, ["M4"]) in {
+    defvar Cycles = SiFive7GetSiFiveVFNRClipCycles<mx, VLEN>;
+    let Latency = Cycles.latency,
+        AcquireAtCycles = [0, 1],
+        ReleaseAtCycles = [1, !add(1, Cycles.occupancy)] in
+    defm : LMULWriteResMX<"WriteSF_VFNRClipV", [VCQ, VA1], mx,
+                          IsWorstCase=!eq(mx, "M2")>;
+  }
 }
 
 //===----------------------------------------------------------------------===//
@@ -1326,6 +1349,10 @@ multiclass SiFive7ReadAdvance {
   def : ReadAdvance<ReadVMov4V, 0>;
   def : ReadAdvance<ReadVMov8V, 0>;
 
+  // XSfvfnrclipxfqf
+  defm : LMULReadAdvance<"ReadSF_VFNRClipV", 0>;
+  defm : LMULReadAdvance<"ReadSF_VFNRClipF", 0>;
+
   // Others
   def : ReadAdvance<ReadVMask, 0>;
   def : ReadAdvance<ReadVPassthru_WorstCase, 0>;

llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

@@ -1239,4 +1239,5 @@ defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfnrclipxfqf;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFiveP500.td

@@ -359,4 +359,5 @@ defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZvk;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfnrclipxfqf;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

@@ -1495,4 +1495,5 @@ defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfnrclipxfqf;
 }

llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td

@@ -1184,4 +1184,5 @@ defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedSFB;
 defm : UnsupportedSchedZfaWithQ;
 defm : UnsupportedSchedXsfvcp;
+defm : UnsupportedSchedXSfvfnrclipxfqf;
 }