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[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)
If I understand correctly there was a point where we used to need this before it was implied by Zvl*b. Now that it is though and we use -mattr=+v in pretty much every test we can remove it. In unroll-in-loop-vectorizer.ll we can force a VF of 1 instead by using -force-vector-width=1, and in scalable-basics.ll the two RUN lines were the same so I merged them.
1 parent 5951c44 commit df38766

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-586
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‎llvm/test/Transforms/LoopVectorize/RISCV/divrem.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=loop-vectorize -scalable-vectorization=on -mtriple riscv64-linux-gnu -mattr=+v,+f -S 2>%t | FileCheck %s
3-
; RUN: opt < %s -passes=loop-vectorize -scalable-vectorization=off -riscv-v-vector-bits-min=-1 -mtriple riscv64-linux-gnu -mattr=+v,+f -S 2>%t | FileCheck --check-prefix=FIXED %s
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; RUN: opt < %s -passes=loop-vectorize -scalable-vectorization=off -mtriple riscv64-linux-gnu -mattr=+v,+f -S 2>%t | FileCheck --check-prefix=FIXED %s
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; Tests specific to div/rem handling - both predicated and not
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‎llvm/test/Transforms/LoopVectorize/RISCV/force-vect-msg.ll‎

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; REQUIRES: asserts
2-
; RUN: opt < %s -passes=loop-vectorize -mtriple riscv64 -riscv-v-vector-bits-min=128 -mattr="+v" -debug-only=loop-vectorize --disable-output -S 2>&1 | FileCheck %s
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; RUN: opt < %s -passes=loop-vectorize -mtriple riscv64 -mattr="+v" -debug-only=loop-vectorize --disable-output -S 2>&1 | FileCheck %s
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; CHECK: LV: Loop hints: force=enabled
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; CHECK: LV: Scalar loop costs: 4.

‎llvm/test/Transforms/LoopVectorize/RISCV/low-trip-count.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=loop-vectorize -riscv-v-vector-bits-min=128 -scalable-vectorization=on -force-target-instruction-cost=1 -S < %s | FileCheck %s
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target triple = "riscv64"
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; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S < %s | FileCheck %s
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define void @trip1_i8(ptr noalias nocapture noundef %dst, ptr noalias nocapture noundef readonly %src) #0 {
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; CHECK-LABEL: @trip1_i8(

‎llvm/test/Transforms/LoopVectorize/RISCV/masked_gather_scatter.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv32 -mattr=+v,+d -riscv-v-vector-bits-min=256 -S | FileCheck %s -check-prefixes=RV32
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; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv64 -mattr=+v,+d -riscv-v-vector-bits-min=256 -S | FileCheck %s -check-prefixes=RV64
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; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv32 -mattr=+v,+zvl256b,+d -S | FileCheck %s -check-prefixes=RV32
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; RUN: opt < %s -passes=loop-vectorize -mtriple=riscv64 -mattr=+v,+zvl256b,+d -S | FileCheck %s -check-prefixes=RV64
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; The source code:
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;

‎llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll‎

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; REQUIRES: asserts
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; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
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; RUN: -mattr=+v,+d -debug-only=loop-vectorize,vplan --disable-output \
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; RUN: -riscv-v-vector-bits-min=128 -force-vector-width=1 \
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; RUN: -force-vector-width=1 \
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; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-SCALAR
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; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
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; RUN: -mattr=+v,+d -debug-only=loop-vectorize,vplan --disable-output \
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; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=1 \
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; RUN: -riscv-v-register-bit-width-lmul=1 \
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; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL1
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; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
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; RUN: -mattr=+v,+d -debug-only=loop-vectorize,vplan --disable-output \
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; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=2 \
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; RUN: -riscv-v-register-bit-width-lmul=2 \
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; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL2
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; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
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; RUN: -mattr=+v,+d -debug-only=loop-vectorize,vplan --disable-output \
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; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=4 \
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; RUN: -riscv-v-register-bit-width-lmul=4 \
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; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL4
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; RUN: opt -passes=loop-vectorize -mtriple riscv64-linux-gnu \
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; RUN: -mattr=+v,+d -debug-only=loop-vectorize,vplan --disable-output \
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; RUN: -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=8 \
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; RUN: -riscv-v-register-bit-width-lmul=8 \
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; RUN: -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL8
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define void @add(ptr noalias nocapture readonly %src1, ptr noalias nocapture readonly %src2, i32 signext %size, ptr noalias nocapture writeonly %result) {

‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-interleaved.ll‎

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; REQUIRES: asserts
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; RUN: opt -passes=loop-vectorize,dce,instcombine -mtriple riscv64-linux-gnu \
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; RUN: -mattr=+v -debug-only=loop-vectorize --disable-output \
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; RUN: -riscv-v-vector-bits-min=128 -scalable-vectorization=off -S < %s 2>&1 | FileCheck %s
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; RUN: -scalable-vectorization=off -S < %s 2>&1 | FileCheck %s
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; CHECK-LABEL: foo
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; CHECK: LV: IC is 2

‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-unroll.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=loop-vectorize -force-target-max-vector-interleave=1 -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -scalable-vectorization=off -S | FileCheck %s --check-prefix=LMUL1
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; RUN: opt < %s -passes=loop-vectorize -force-target-max-vector-interleave=1 -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -scalable-vectorization=off -S | FileCheck %s --check-prefix=LMUL1
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; RUN: opt < %s -passes=loop-vectorize -force-target-max-vector-interleave=1 -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -scalable-vectorization=off -riscv-v-register-bit-width-lmul=2 -S | FileCheck %s --check-prefix=LMUL2
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; RUN: opt < %s -passes=loop-vectorize -force-target-max-vector-interleave=1 -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -scalable-vectorization=off -riscv-v-register-bit-width-lmul=2 -S | FileCheck %s --check-prefix=LMUL2
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; RUN: opt < %s -passes=loop-vectorize -force-target-max-vector-interleave=1 -mtriple=riscv64 -mattr=+v -scalable-vectorization=off -S | FileCheck %s --check-prefix=LMUL1
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; RUN: opt < %s -passes=loop-vectorize -force-target-max-vector-interleave=1 -mtriple=riscv32 -mattr=+v -scalable-vectorization=off -S | FileCheck %s --check-prefix=LMUL1
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; RUN: opt < %s -passes=loop-vectorize -force-target-max-vector-interleave=1 -mtriple=riscv64 -mattr=+v -scalable-vectorization=off -riscv-v-register-bit-width-lmul=2 -S | FileCheck %s --check-prefix=LMUL2
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; RUN: opt < %s -passes=loop-vectorize -force-target-max-vector-interleave=1 -mtriple=riscv32 -mattr=+v -scalable-vectorization=off -riscv-v-register-bit-width-lmul=2 -S | FileCheck %s --check-prefix=LMUL2
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; Function Attrs: nounwind
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define ptr @array_add(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, ptr %c, i32 %size) {

‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse-output.ll‎

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;; for (int i = N-1; i >= 0; --i)
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;; a[i] = b[i] + 1.0;
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; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v \
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; RUN: -riscv-v-vector-bits-min=128 -S < %s \
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; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -S < %s \
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; RUN: | FileCheck --check-prefix=RV64 %s
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; RUN: opt -passes=loop-vectorize -mtriple=riscv32 -mattr=+v \
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; RUN: -riscv-v-vector-bits-min=128 -S < %s \
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; RUN: opt -passes=loop-vectorize -mtriple=riscv32 -mattr=+v -S < %s \
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; RUN: | FileCheck --check-prefix=RV32 %s
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; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v \
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; RUN: -riscv-v-vector-bits-min=128 -force-vector-interleave=2 -S < %s \
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; RUN: opt -passes=loop-vectorize -mtriple=riscv64 -mattr=+v -force-vector-interleave=2 -S < %s \
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; RUN: | FileCheck --check-prefix=RV64-UF2 %s
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define void @vector_reverse_i32(ptr noalias %A, ptr noalias %B) {

‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll‎

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; REQUIRES: asserts
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; RUN: opt -passes=loop-vectorize,dce,instcombine -mtriple riscv64-linux-gnu \
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; RUN: -mattr=+v -debug-only=loop-vectorize,vplan -scalable-vectorization=on \
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; RUN: -riscv-v-vector-bits-min=128 -disable-output < %s 2>&1 | FileCheck %s
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; RUN: -disable-output < %s 2>&1 | FileCheck %s
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define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocapture noundef readonly %B, i32 noundef signext %n) {
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; CHECK-LABEL: 'vector_reverse_i64'

‎llvm/test/Transforms/LoopVectorize/RISCV/safe-dep-distance.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=loop-vectorize -scalable-vectorization=on -riscv-v-vector-bits-min=-1 -mtriple riscv64-linux-gnu -mattr=+v,+f -S 2>%t | FileCheck %s
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; RUN: opt < %s -passes=loop-vectorize -scalable-vectorization=on -mtriple riscv64-linux-gnu -mattr=+v,+f -S 2>%t | FileCheck %s
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64"

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