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Automerge: AMDGPU: Replace undef with poison in tests using insertvalue (#130895)
perl -p -i -e 's/insertvalue (.*) undef/insertvalue \1 poison/g'
2 parents 7d96785 + 5a0a2f8 commit e84f447

31 files changed

+178
-176
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_use(i32 inreg %src0, i32 inreg
6464
; GFX11-NEXT: ; return to shader part epilog
6565
%not.src1 = xor i32 %src1, -1
6666
%and = and i32 %src0, %not.src1
67-
%insert.0 = insertvalue { i32, i32 } undef, i32 %and, 0
67+
%insert.0 = insertvalue { i32, i32 } poison, i32 %and, 0
6868
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %not.src1, 1
6969
ret { i32, i32 } %insert.1
7070
}
@@ -90,7 +90,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_foldable_use(i32 inreg %src0, i
9090
%not.src2 = xor i32 %src2, -1
9191
%and0 = and i32 %src0, %not.src2
9292
%and1 = and i32 %src1, %not.src2
93-
%insert.0 = insertvalue { i32, i32 } undef, i32 %and0, 0
93+
%insert.0 = insertvalue { i32, i32 } poison, i32 %and0, 0
9494
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %and1, 1
9595
ret { i32, i32 } %insert.1
9696
}
@@ -211,7 +211,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_foldable_use(i64 inreg %src0, i
211211
%not.src2 = xor i64 %src2, -1
212212
%and0 = and i64 %src0, %not.src2
213213
%and1 = and i64 %src1, %not.src2
214-
%insert.0 = insertvalue { i64, i64 } undef, i64 %and0, 0
214+
%insert.0 = insertvalue { i64, i64 } poison, i64 %and0, 0
215215
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %and1, 1
216216
ret { i64, i64 } %insert.1
217217
}
@@ -238,7 +238,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_use(i64 inreg %src0, i64 inreg
238238
; GFX11-NEXT: ; return to shader part epilog
239239
%not.src1 = xor i64 %src1, -1
240240
%and = and i64 %src0, %not.src1
241-
%insert.0 = insertvalue { i64, i64 } undef, i64 %and, 0
241+
%insert.0 = insertvalue { i64, i64 } poison, i64 %and, 0
242242
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %not.src1, 1
243243
ret { i64, i64 } %insert.1
244244
}
@@ -408,7 +408,7 @@ define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_use(i16 inreg %src0, i16 inreg
408408
; GFX11-NEXT: ; return to shader part epilog
409409
%not.src1 = xor i16 %src1, -1
410410
%and = and i16 %src0, %not.src1
411-
%insert.0 = insertvalue { i16, i16 } undef, i16 %and, 0
411+
%insert.0 = insertvalue { i16, i16 } poison, i16 %and, 0
412412
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1
413413
ret { i16, i16 } %insert.1
414414
}
@@ -434,7 +434,7 @@ define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_foldable_use(i16 inreg %src0, i
434434
%not.src2 = xor i16 %src2, -1
435435
%and0 = and i16 %src0, %not.src2
436436
%and1 = and i16 %src1, %not.src2
437-
%insert.0 = insertvalue { i16, i16 } undef, i16 %and0, 0
437+
%insert.0 = insertvalue { i16, i16 } poison, i16 %and0, 0
438438
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %and1, 1
439439
ret { i16, i16 } %insert.1
440440
}
@@ -601,7 +601,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_use(<2 x i16> inreg %src0, <2
601601

602602
%cast.0 = bitcast <2 x i16> %and to i32
603603
%cast.1 = bitcast <2 x i16> %not.src1 to i32
604-
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
604+
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
605605
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
606606
ret { i32, i32 } %insert.1
607607
}
@@ -646,7 +646,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_foldable_use(<2 x i16> inreg
646646

647647
%cast.0 = bitcast <2 x i16> %and0 to i32
648648
%cast.1 = bitcast <2 x i16> %and1 to i32
649-
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
649+
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
650650
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
651651
ret { i32, i32 } %insert.1
652652
}
@@ -857,7 +857,7 @@ define amdgpu_ps { i48, i48 } @s_andn2_v3i16_multi_use(<3 x i16> inreg %src0, <3
857857
%and = and <3 x i16> %src0, %not.src1
858858
%cast.0 = bitcast <3 x i16> %and to i48
859859
%cast.1 = bitcast <3 x i16> %not.src1 to i48
860-
%insert.0 = insertvalue { i48, i48 } undef, i48 %cast.0, 0
860+
%insert.0 = insertvalue { i48, i48 } poison, i48 %cast.0, 0
861861
%insert.1 = insertvalue { i48, i48 } %insert.0, i48 %cast.1, 1
862862
ret { i48, i48 } %insert.1
863863
}
@@ -1028,7 +1028,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_v4i16_multi_use(<4 x i16> inreg %src0, <4
10281028

10291029
%cast.0 = bitcast <4 x i16> %and to i64
10301030
%cast.1 = bitcast <4 x i16> %not.src1 to i64
1031-
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
1031+
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
10321032
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
10331033
ret { i64, i64 } %insert.1
10341034
}
@@ -1082,7 +1082,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_v4i16_multi_foldable_use(<4 x i16> inreg
10821082

10831083
%cast.0 = bitcast <4 x i16> %and0 to i64
10841084
%cast.1 = bitcast <4 x i16> %and1 to i64
1085-
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
1085+
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
10861086
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
10871087
ret { i64, i64 } %insert.1
10881088
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1061,6 +1061,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
10611061
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
10621062
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
10631063
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1064+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
10641065
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
10651066
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
10661067
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
@@ -1083,7 +1084,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
10831084
%insert.0 = insertelement <3 x i32> undef, i32 %load0, i32 0
10841085
%insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1
10851086
%insert.2 = insertelement <3 x i32> %insert.1, i32 %load2, i32 2
1086-
%insert.3 = insertvalue { <3 x i32>, i32 } undef, <3 x i32> %insert.2, 0
1087+
%insert.3 = insertvalue { <3 x i32>, i32 } poison, <3 x i32> %insert.2, 0
10871088
%insert.4 = insertvalue { <3 x i32>, i32 } %insert.3, i32 %load3, 1
10881089
ret { <3 x i32>, i32 } %insert.4
10891090
}
@@ -1096,6 +1097,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
10961097
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
10971098
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
10981099
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
1100+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
10991101
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
11001102
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
11011103
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
@@ -1118,7 +1120,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
11181120
%insert.0 = insertelement <3 x float> undef, float %load0, i32 0
11191121
%insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1
11201122
%insert.2 = insertelement <3 x float> %insert.1, float %load2, i32 2
1121-
%insert.3 = insertvalue { <3 x float>, i32 } undef, <3 x float> %insert.2, 0
1123+
%insert.3 = insertvalue { <3 x float>, i32 } poison, <3 x float> %insert.2, 0
11221124
%insert.4 = insertvalue { <3 x float>, i32 } %insert.3, i32 %load3, 1
11231125
ret { <3 x float>, i32 } %insert.4
11241126
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ define amdgpu_ps { i32, i32 } @sgpr_struct_return_i32_i32(i32 %vgpr0, i32 %vgpr1
104104
; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
105105
; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)
106106
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
107-
%insertvalue0 = insertvalue { i32, i32 } undef, i32 %vgpr0, 0
107+
%insertvalue0 = insertvalue { i32, i32 } poison, i32 %vgpr0, 0
108108
%value = insertvalue { i32, i32 } %insertvalue0, i32 %vgpr1, 1
109109
ret { i32, i32 } %value
110110
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ define amdgpu_vs <{ i32, i32 }> @ret_struct(i32 inreg %arg0, i32 inreg %arg1) {
8888
; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)
8989
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
9090
main_body:
91-
%tmp0 = insertvalue <{ i32, i32 }> undef, i32 %arg0, 0
91+
%tmp0 = insertvalue <{ i32, i32 }> poison, i32 %arg0, 0
9292
%tmp1 = insertvalue <{ i32, i32 }> %tmp0, i32 %arg1, 1
9393
ret <{ i32, i32 }> %tmp1
9494
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_use(i32 inreg %src0, i32 inreg %
6464
; GFX11-NEXT: ; return to shader part epilog
6565
%not.src1 = xor i32 %src1, -1
6666
%or = or i32 %src0, %not.src1
67-
%insert.0 = insertvalue { i32, i32 } undef, i32 %or, 0
67+
%insert.0 = insertvalue { i32, i32 } poison, i32 %or, 0
6868
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %not.src1, 1
6969
ret { i32, i32 } %insert.1
7070
}
@@ -90,7 +90,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_foldable_use(i32 inreg %src0, i3
9090
%not.src2 = xor i32 %src2, -1
9191
%or0 = or i32 %src0, %not.src2
9292
%or1 = or i32 %src1, %not.src2
93-
%insert.0 = insertvalue { i32, i32 } undef, i32 %or0, 0
93+
%insert.0 = insertvalue { i32, i32 } poison, i32 %or0, 0
9494
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %or1, 1
9595
ret { i32, i32 } %insert.1
9696
}
@@ -211,7 +211,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_foldable_use(i64 inreg %src0, i6
211211
%not.src2 = xor i64 %src2, -1
212212
%or0 = or i64 %src0, %not.src2
213213
%or1 = or i64 %src1, %not.src2
214-
%insert.0 = insertvalue { i64, i64 } undef, i64 %or0, 0
214+
%insert.0 = insertvalue { i64, i64 } poison, i64 %or0, 0
215215
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %or1, 1
216216
ret { i64, i64 } %insert.1
217217
}
@@ -238,7 +238,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_use(i64 inreg %src0, i64 inreg %
238238
; GFX11-NEXT: ; return to shader part epilog
239239
%not.src1 = xor i64 %src1, -1
240240
%or = or i64 %src0, %not.src1
241-
%insert.0 = insertvalue { i64, i64 } undef, i64 %or, 0
241+
%insert.0 = insertvalue { i64, i64 } poison, i64 %or, 0
242242
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %not.src1, 1
243243
ret { i64, i64 } %insert.1
244244
}
@@ -408,7 +408,7 @@ define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_use(i16 inreg %src0, i16 inreg %
408408
; GFX11-NEXT: ; return to shader part epilog
409409
%not.src1 = xor i16 %src1, -1
410410
%or = or i16 %src0, %not.src1
411-
%insert.0 = insertvalue { i16, i16 } undef, i16 %or, 0
411+
%insert.0 = insertvalue { i16, i16 } poison, i16 %or, 0
412412
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1
413413
ret { i16, i16 } %insert.1
414414
}
@@ -434,7 +434,7 @@ define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_foldable_use(i16 inreg %src0, i1
434434
%not.src2 = xor i16 %src2, -1
435435
%or0 = or i16 %src0, %not.src2
436436
%or1 = or i16 %src1, %not.src2
437-
%insert.0 = insertvalue { i16, i16 } undef, i16 %or0, 0
437+
%insert.0 = insertvalue { i16, i16 } poison, i16 %or0, 0
438438
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %or1, 1
439439
ret { i16, i16 } %insert.1
440440
}
@@ -601,7 +601,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_use(<2 x i16> inreg %src0, <2
601601

602602
%cast.0 = bitcast <2 x i16> %or to i32
603603
%cast.1 = bitcast <2 x i16> %not.src1 to i32
604-
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
604+
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
605605
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
606606
ret { i32, i32 } %insert.1
607607
}
@@ -646,7 +646,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_foldable_use(<2 x i16> inreg %
646646

647647
%cast.0 = bitcast <2 x i16> %or0 to i32
648648
%cast.1 = bitcast <2 x i16> %or1 to i32
649-
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
649+
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
650650
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
651651
ret { i32, i32 } %insert.1
652652
}
@@ -856,7 +856,7 @@ define amdgpu_ps { i48, i48 } @s_orn2_v3i16_multi_use(<3 x i16> inreg %src0, <3
856856
%or = or <3 x i16> %src0, %not.src1
857857
%cast.0 = bitcast <3 x i16> %or to i48
858858
%cast.1 = bitcast <3 x i16> %not.src1 to i48
859-
%insert.0 = insertvalue { i48, i48 } undef, i48 %cast.0, 0
859+
%insert.0 = insertvalue { i48, i48 } poison, i48 %cast.0, 0
860860
%insert.1 = insertvalue { i48, i48 } %insert.0, i48 %cast.1, 1
861861
ret { i48, i48 } %insert.1
862862
}
@@ -1027,7 +1027,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_v4i16_multi_use(<4 x i16> inreg %src0, <4
10271027

10281028
%cast.0 = bitcast <4 x i16> %or to i64
10291029
%cast.1 = bitcast <4 x i16> %not.src1 to i64
1030-
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
1030+
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
10311031
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
10321032
ret { i64, i64 } %insert.1
10331033
}
@@ -1081,7 +1081,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_v4i16_multi_foldable_use(<4 x i16> inreg %
10811081

10821082
%cast.0 = bitcast <4 x i16> %or0 to i64
10831083
%cast.1 = bitcast <4 x i16> %or1 to i64
1084-
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
1084+
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
10851085
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
10861086
ret { i64, i64 } %insert.1
10871087
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/shlN_add.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -476,7 +476,7 @@ define amdgpu_ps { i32, i32 } @s_shl4_add_u32_multi_use(i32 inreg %src0, i32 inr
476476
; GCN-NEXT: ; return to shader part epilog
477477
%shl = shl i32 %src0, 4
478478
%add = add i32 %shl, %src1
479-
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
479+
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
480480
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
481481
ret { i32, i32 } %insert1
482482
}
@@ -489,7 +489,7 @@ define amdgpu_ps { i32, i32 } @s_shl3_add_u32_multi_use(i32 inreg %src0, i32 inr
489489
; GCN-NEXT: ; return to shader part epilog
490490
%shl = shl i32 %src0, 3
491491
%add = add i32 %shl, %src1
492-
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
492+
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
493493
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
494494
ret { i32, i32 } %insert1
495495
}
@@ -502,7 +502,7 @@ define amdgpu_ps { i32, i32 } @s_shl2_add_u32_multi_use(i32 inreg %src0, i32 inr
502502
; GCN-NEXT: ; return to shader part epilog
503503
%shl = shl i32 %src0, 2
504504
%add = add i32 %shl, %src1
505-
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
505+
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
506506
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
507507
ret { i32, i32 } %insert1
508508
}
@@ -516,7 +516,7 @@ define amdgpu_ps { i32, i32 } @s_shl1_add_u32_multi_use(i32 inreg %src0, i32 inr
516516
; GCN-NEXT: ; return to shader part epilog
517517
%shl = shl i32 %src0, 1
518518
%add = add i32 %shl, %src1
519-
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
519+
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
520520
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
521521
ret { i32, i32 } %insert1
522522
}

‎llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ define amdgpu_gs { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i
6262
%56 = add i32 %55, %27
6363
%57 = add i32 %56, %28
6464
%58 = add i32 %57, %29
65-
%59 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } undef, i32 %30, 0
65+
%59 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } poison, i32 %30, 0
6666
%60 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %59, i32 %31, 1
6767
%61 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %60, i32 %32, 2
6868
%62 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %61, i32 %33, 3

‎llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ define amdgpu_gs { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i
5050
%88 = add i32 %87, %43
5151
%89 = add i32 %88, %44
5252
%90 = add i32 %89, %45
53-
%91 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } undef, i32 %46, 0
53+
%91 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } poison, i32 %46, 0
5454
%92 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %91, i32 %47, 1
5555
%93 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %92, i32 %48, 2
5656
%94 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %93, i32 %49, 3

‎llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -247,7 +247,7 @@ main_body:
247247
%34 = extractelement <4 x float> %31, i32 2
248248
%35 = extractelement <4 x float> %31, i32 3
249249
%36 = bitcast float %4 to i32
250-
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %36, 4
250+
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> poison, i32 %36, 4
251251
%38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %37, float %32, 5
252252
%39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 6
253253
%40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 7
@@ -279,7 +279,7 @@ main_body:
279279
%34 = extractelement <4 x float> %31, i32 2
280280
%35 = extractelement <4 x float> %31, i32 3
281281
%36 = bitcast float %4 to i32
282-
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %36, 4
282+
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> poison, i32 %36, 4
283283
%38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %37, float %32, 5
284284
%39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 6
285285
%40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 7

‎llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -168,7 +168,7 @@ bb1:
168168
%val1 = extractvalue { <4 x i32>, <4 x half> } %split.ret.type, 1
169169
%extract0 = extractelement <4 x i32> %val0, i32 0
170170
%extract1 = extractelement <4 x half> %val1, i32 0
171-
%ins0 = insertvalue { i32, half } undef, i32 %extract0, 0
171+
%ins0 = insertvalue { i32, half } poison, i32 %extract0, 0
172172
%ins1 = insertvalue { i32, half } %ins0, half %extract1, 1
173173
ret { i32, half } %ins1
174174
}

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