Revert "[SLP]Reduce number of alternate instruction, where possible"

This caused failures such as:

  Instruction does not dominate all uses!
  %29 = insertelement <8 x i64> %28, i64 %xor6.i.5, i64 6
  %17 = shufflevector <8 x i64> %29, <8 x i64> poison, <6 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>

see comment on llvm/llvm-project#123360

> Previous version was reviewed here llvm/llvm-project#123360
> It is mostly the same, adjusted after graph-to-tree transformation
>
> Patch tries to remove wide alternate operations.
> Currently SLP vectorizer emits something like this:
> ```
> %0 = add i32
> %1 = sub i32
> %2 = add i32
> %3 = sub i32
> %4 = add i32
> %5 = sub i32
> %6 = add i32
> %7 = sub i32
>
> transformes to
>
> %v1 = add <8 x i32>
> %v2 = sub <8 x i32>
> %res = shuffle %v1, %v2, <0, 9, 2, 11, 4, 13, 6, 15>
> ```
> i.e. half of the results are just unused. This leads to increased
> register pressure and potentially doubles number of operations.
>
> Patch introduces SplitVectorize mode, where it splits the operations by
> opcodes and produces instead something like this:
> ```
> %v1 = add <4 x i32>
> %v2 = sub <4 x i32>
> %res = shuffle %v1, %v2, <0, 4, 1, 5, 2, 6, 3, 7>
> ```
> It allows to improve the performance by reducing number of ops. Also, it
> turns on some other improvements, like improved graph reordering.
>
> [...]

This reverts commit 9d37e61 as well as
the follow-up commit 72bb0a9.

Author: zmodem

llvm/include/llvm/Analysis/TargetTransformInfo.h

@@ -1771,10 +1771,6 @@ class TargetTransformInfo {
   /// scalable version of the vectorized loop.
   bool preferFixedOverScalableIfEqualCost() const;
 
-  /// \returns True if target prefers SLP vectorizer with altermate opcode
-  /// vectorization, false - otherwise.
-  bool preferAlternateOpcodeVectorization() const;
-
   /// \returns True if the target prefers reductions in loop.
   bool preferInLoopReduction(unsigned Opcode, Type *Ty) const;
 
@@ -2329,7 +2325,6 @@ class TargetTransformInfo::Concept {
   virtual bool preferInLoopReduction(unsigned Opcode, Type *Ty) const = 0;
   virtual bool preferPredicatedReductionSelect(unsigned Opcode,
                                                Type *Ty) const = 0;
-  virtual bool preferAlternateOpcodeVectorization() const = 0;
   virtual bool preferEpilogueVectorization() const = 0;
 
   virtual bool shouldExpandReduction(const IntrinsicInst *II) const = 0;
@@ -3140,9 +3135,6 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
   bool preferInLoopReduction(unsigned Opcode, Type *Ty) const override {
     return Impl.preferInLoopReduction(Opcode, Ty);
   }
-  bool preferAlternateOpcodeVectorization() const override {
-    return Impl.preferAlternateOpcodeVectorization();
-  }
   bool preferPredicatedReductionSelect(unsigned Opcode,
                                        Type *Ty) const override {
     return Impl.preferPredicatedReductionSelect(Opcode, Ty);

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

@@ -1007,7 +1007,6 @@ class TargetTransformInfoImplBase {
   bool preferFixedOverScalableIfEqualCost() const { return false; }
 
   bool preferInLoopReduction(unsigned Opcode, Type *Ty) const { return false; }
-  bool preferAlternateOpcodeVectorization() const { return true; }
 
   bool preferPredicatedReductionSelect(unsigned Opcode, Type *Ty) const {
     return false;

llvm/lib/Analysis/TargetTransformInfo.cpp

@@ -1384,10 +1384,6 @@ bool TargetTransformInfo::preferInLoopReduction(unsigned Opcode,
   return TTIImpl->preferInLoopReduction(Opcode, Ty);
 }
 
-bool TargetTransformInfo::preferAlternateOpcodeVectorization() const {
-  return TTIImpl->preferAlternateOpcodeVectorization();
-}
-
 bool TargetTransformInfo::preferPredicatedReductionSelect(unsigned Opcode,
                                                           Type *Ty) const {
   return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty);

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

@@ -125,8 +125,6 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
 
   unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
 
-  bool preferAlternateOpcodeVectorization() const { return false; }
-
   bool preferEpilogueVectorization() const {
     // Epilogue vectorization is usually unprofitable - tail folding or
     // a smaller VF would have been better.  This a blunt hammer - we

llvm/lib/Target/X86/X86TargetTransformInfo.h

@@ -292,7 +292,6 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
 
   TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
                                                     bool IsZeroCmp) const;
-  bool preferAlternateOpcodeVectorization() const { return false; }
   bool prefersVectorizedAddressing() const;
   bool supportsEfficientVectorElementLoadStore() const;
   bool enableInterleavedAccessVectorization();