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[SLP,AArch64] Update build-vector test to actually build vectors.
Update test with all zero constant input values which get folded during IR construction to actually use different input values, which require materializing build vectors.
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‎llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll‎

Lines changed: 70 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,75 @@
11
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
22
; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
33

4-
define void @h() {
5-
; CHECK-LABEL: define void @h() {
4+
define void @h(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o) {
5+
; CHECK-LABEL: define void @h(
6+
; CHECK-SAME: i16 [[A:%.*]], i16 [[B:%.*]], i16 [[C:%.*]], i16 [[D:%.*]], i16 [[E:%.*]], i16 [[F:%.*]], i16 [[G:%.*]], i16 [[H:%.*]], i16 [[I:%.*]], i16 [[J:%.*]], i16 [[K:%.*]], i16 [[L:%.*]], i16 [[M:%.*]], i16 [[N:%.*]], i16 [[O:%.*]]) {
67
; CHECK-NEXT: entry:
8+
; CHECK-NEXT: [[CONV9:%.*]] = zext i16 [[A]] to i32
79
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16
8-
; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2
10+
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i16> poison, i16 [[E]], i32 0
11+
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> [[TMP0]], i16 [[I]], i32 1
12+
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[M]], i32 2
13+
; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[B]], i32 3
14+
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i16> [[TMP3]], i32 3
15+
; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[TMP4]] to i32
16+
; CHECK-NEXT: [[SUB:%.*]] = or i32 [[CONV9]], [[TMP5]]
17+
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[G]], i32 0
18+
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i16> [[TMP6]], i16 [[K]], i32 1
19+
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i16> [[TMP7]], i16 [[O]], i32 2
20+
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i16> [[TMP8]], i16 [[C]], i32 3
21+
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 0, 0
22+
; CHECK-NEXT: [[CONV19:%.*]] = sext i16 [[D]] to i32
23+
; CHECK-NEXT: [[SUB20:%.*]] = or i32 [[SHR]], [[CONV19]]
24+
; CHECK-NEXT: [[SUB39:%.*]] = or i32 [[SUB]], [[SUB20]]
25+
; CHECK-NEXT: [[CONV40:%.*]] = trunc i32 [[SUB39]] to i16
26+
; CHECK-NEXT: store i16 [[CONV40]], ptr [[ARRAYIDX2]], align 2
27+
; CHECK-NEXT: [[ARRAYIDX2_1:%.*]] = getelementptr i8, ptr null, i64 18
28+
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i16> [[TMP3]], i32 0
29+
; CHECK-NEXT: [[TMP11:%.*]] = zext i16 [[TMP10]] to i32
30+
; CHECK-NEXT: [[ADD4_1:%.*]] = or i32 [[TMP11]], 0
31+
; CHECK-NEXT: [[CONV15_1:%.*]] = sext i16 [[F]] to i32
32+
; CHECK-NEXT: [[ARRAYIDX18_1:%.*]] = getelementptr i8, ptr null, i64 26
33+
; CHECK-NEXT: [[SHR29_1:%.*]] = ashr i32 0, 0
34+
; CHECK-NEXT: [[ADD30_1:%.*]] = or i32 [[SHR29_1]], [[CONV15_1]]
35+
; CHECK-NEXT: [[SUB44_1:%.*]] = or i32 [[ADD4_1]], [[ADD30_1]]
36+
; CHECK-NEXT: [[CONV45_1:%.*]] = trunc i32 [[SUB44_1]] to i16
37+
; CHECK-NEXT: store i16 [[CONV45_1]], ptr [[ARRAYIDX18_1]], align 2
38+
; CHECK-NEXT: [[CONV_213:%.*]] = zext i16 [[H]] to i32
39+
; CHECK-NEXT: [[ADD4_2:%.*]] = or i32 0, [[CONV_213]]
40+
; CHECK-NEXT: [[CONV15_2:%.*]] = sext i16 [[J]] to i32
41+
; CHECK-NEXT: [[ARRAYIDX18_2:%.*]] = getelementptr i8, ptr null, i64 28
42+
; CHECK-NEXT: [[SHR29_2:%.*]] = ashr i32 0, 0
43+
; CHECK-NEXT: [[ADD30_2:%.*]] = or i32 [[SHR29_2]], [[CONV15_2]]
44+
; CHECK-NEXT: [[SUB44_2:%.*]] = or i32 [[ADD4_2]], [[ADD30_2]]
45+
; CHECK-NEXT: [[CONV45_2:%.*]] = trunc i32 [[SUB44_2]] to i16
46+
; CHECK-NEXT: store i16 [[CONV45_2]], ptr [[ARRAYIDX18_2]], align 2
47+
; CHECK-NEXT: [[CONV_315:%.*]] = zext i16 [[L]] to i32
48+
; CHECK-NEXT: [[ADD4_3:%.*]] = or i32 0, [[CONV_315]]
49+
; CHECK-NEXT: [[CONV15_3:%.*]] = sext i16 [[N]] to i32
50+
; CHECK-NEXT: [[ARRAYIDX18_3:%.*]] = getelementptr i8, ptr null, i64 30
51+
; CHECK-NEXT: [[SHR29_3:%.*]] = ashr i32 0, 0
52+
; CHECK-NEXT: [[ADD30_3:%.*]] = or i32 [[SHR29_3]], [[CONV15_3]]
53+
; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i16> <i16 0, i16 0, i16 0, i16 poison>, i16 [[A]], i32 3
54+
; CHECK-NEXT: [[TMP13:%.*]] = or <4 x i16> [[TMP3]], [[TMP12]]
55+
; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i16> zeroinitializer, [[TMP9]]
56+
; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i16> [[TMP13]], [[TMP14]]
57+
; CHECK-NEXT: store <4 x i16> [[TMP15]], ptr [[ARRAYIDX2_1]], align 2
58+
; CHECK-NEXT: [[SUB44_3:%.*]] = or i32 [[ADD4_3]], [[ADD30_3]]
59+
; CHECK-NEXT: [[CONV45_3:%.*]] = trunc i32 [[SUB44_3]] to i16
60+
; CHECK-NEXT: store i16 [[CONV45_3]], ptr [[ARRAYIDX18_3]], align 2
961
; CHECK-NEXT: ret void
1062
;
1163
entry:
12-
%conv9 = zext i16 0 to i32
64+
%conv9 = zext i16 %a to i32
1365
%arrayidx2 = getelementptr i8, ptr null, i64 16
14-
%conv310 = zext i16 0 to i32
66+
%conv310 = zext i16 %b to i32
1567
%add4 = or i32 %conv310, %conv9
1668
%sub = or i32 %conv9, %conv310
17-
%conv15 = sext i16 0 to i32
69+
%conv15 = sext i16 %c to i32
1870
%shr = ashr i32 0, 0
1971
%arrayidx18 = getelementptr i8, ptr null, i64 24
20-
%conv19 = sext i16 0 to i32
72+
%conv19 = sext i16 %d to i32
2173
%sub20 = or i32 %shr, %conv19
2274
%shr29 = ashr i32 0, 0
2375
%add30 = or i32 %shr29, %conv15
@@ -28,13 +80,13 @@ entry:
2880
%conv45 = trunc i32 %sub44 to i16
2981
store i16 %conv45, ptr %arrayidx18, align 2
3082
%arrayidx2.1 = getelementptr i8, ptr null, i64 18
31-
%conv3.112 = zext i16 0 to i32
83+
%conv3.112 = zext i16 %e to i32
3284
%add4.1 = or i32 %conv3.112, 0
3385
%sub.1 = or i32 0, %conv3.112
34-
%conv15.1 = sext i16 0 to i32
86+
%conv15.1 = sext i16 %f to i32
3587
%shr.1 = ashr i32 0, 0
3688
%arrayidx18.1 = getelementptr i8, ptr null, i64 26
37-
%conv19.1 = sext i16 0 to i32
89+
%conv19.1 = sext i16 %g to i32
3890
%sub20.1 = or i32 %shr.1, %conv19.1
3991
%shr29.1 = ashr i32 0, 0
4092
%add30.1 = or i32 %shr29.1, %conv15.1
@@ -44,15 +96,15 @@ entry:
4496
%sub44.1 = or i32 %add4.1, %add30.1
4597
%conv45.1 = trunc i32 %sub44.1 to i16
4698
store i16 %conv45.1, ptr %arrayidx18.1, align 2
47-
%conv.213 = zext i16 0 to i32
99+
%conv.213 = zext i16 %h to i32
48100
%arrayidx2.2 = getelementptr i8, ptr null, i64 20
49-
%conv3.214 = zext i16 0 to i32
101+
%conv3.214 = zext i16 %i to i32
50102
%add4.2 = or i32 0, %conv.213
51103
%sub.2 = or i32 0, %conv3.214
52-
%conv15.2 = sext i16 0 to i32
104+
%conv15.2 = sext i16 %j to i32
53105
%shr.2 = ashr i32 0, 0
54106
%arrayidx18.2 = getelementptr i8, ptr null, i64 28
55-
%conv19.2 = sext i16 0 to i32
107+
%conv19.2 = sext i16 %k to i32
56108
%sub20.2 = or i32 %shr.2, %conv19.2
57109
%shr29.2 = ashr i32 0, 0
58110
%add30.2 = or i32 %shr29.2, %conv15.2
@@ -62,15 +114,15 @@ entry:
62114
%sub44.2 = or i32 %add4.2, %add30.2
63115
%conv45.2 = trunc i32 %sub44.2 to i16
64116
store i16 %conv45.2, ptr %arrayidx18.2, align 2
65-
%conv.315 = zext i16 0 to i32
117+
%conv.315 = zext i16 %l to i32
66118
%arrayidx2.3 = getelementptr i8, ptr null, i64 22
67-
%conv3.316 = zext i16 0 to i32
119+
%conv3.316 = zext i16 %m to i32
68120
%add4.3 = or i32 0, %conv.315
69121
%sub.3 = or i32 0, %conv3.316
70-
%conv15.3 = sext i16 0 to i32
122+
%conv15.3 = sext i16 %n to i32
71123
%shr.3 = ashr i32 0, 0
72124
%arrayidx18.3 = getelementptr i8, ptr null, i64 30
73-
%conv19.3 = sext i16 0 to i32
125+
%conv19.3 = sext i16 %o to i32
74126
%sub20.3 = or i32 %shr.3, %conv19.3
75127
%shr29.3 = ashr i32 0, 0
76128
%add30.3 = or i32 %shr29.3, %conv15.3

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