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Automerge: [ARM] Add neon vector support for floor (#142559)
This marks ffloor as legal providing that armv8 and neon is present (or fullfp16 for the fp16 instructions). The existing arm_neon_vrintm intrinsics are auto-upgraded to llvm.floor. If this is OK I will update the other vrint intrinsics.
2 parents 6aabc6a + dcc9e36 commit ec5bf52

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8 files changed

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‎clang/lib/CodeGen/TargetBuiltins/ARM.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -843,8 +843,8 @@ static const ARMVectorIntrinsicInfo ARMSIMDIntrinsicMap [] = {
843843
NEONMAP1(vrndaq_v, arm_neon_vrinta, Add1ArgType),
844844
NEONMAP0(vrndi_v),
845845
NEONMAP0(vrndiq_v),
846-
NEONMAP1(vrndm_v, arm_neon_vrintm, Add1ArgType),
847-
NEONMAP1(vrndmq_v, arm_neon_vrintm, Add1ArgType),
846+
NEONMAP1(vrndm_v, floor, Add1ArgType),
847+
NEONMAP1(vrndmq_v, floor, Add1ArgType),
848848
NEONMAP1(vrndn_v, arm_neon_vrintn, Add1ArgType),
849849
NEONMAP1(vrndnq_v, arm_neon_vrintn, Add1ArgType),
850850
NEONMAP1(vrndp_v, arm_neon_vrintp, Add1ArgType),

‎clang/test/CodeGen/arm-neon-directed-rounding.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ float32x4_t test_vrndaq_f32(float32x4_t a) {
6666
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <2 x float> [[A]] to <2 x i32>
6767
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[TMP0]] to <8 x i8>
6868
// CHECK-A32-NEXT: [[VRNDM_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x float>
69-
// CHECK-A32-NEXT: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintm.v2f32(<2 x float> [[VRNDM_V_I]])
69+
// CHECK-A32-NEXT: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[VRNDM_V_I]])
7070
// CHECK-A32-NEXT: [[VRNDM_V2_I:%.*]] = bitcast <2 x float> [[VRNDM_V1_I]] to <8 x i8>
7171
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRNDM_V2_I]] to <2 x i32>
7272
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[TMP2]] to <2 x float>
@@ -91,7 +91,7 @@ float32x2_t test_vrndm_f32(float32x2_t a) {
9191
// CHECK-A32-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A]] to <4 x i32>
9292
// CHECK-A32-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[TMP0]] to <16 x i8>
9393
// CHECK-A32-NEXT: [[VRNDMQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x float>
94-
// CHECK-A32-NEXT: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintm.v4f32(<4 x float> [[VRNDMQ_V_I]])
94+
// CHECK-A32-NEXT: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.floor.v4f32(<4 x float> [[VRNDMQ_V_I]])
9595
// CHECK-A32-NEXT: [[VRNDMQ_V2_I:%.*]] = bitcast <4 x float> [[VRNDMQ_V1_I]] to <16 x i8>
9696
// CHECK-A32-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDMQ_V2_I]] to <4 x i32>
9797
// CHECK-A32-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP2]] to <4 x float>

‎clang/test/CodeGen/arm-v8.2a-neon-intrinsics.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -586,7 +586,7 @@ float16x8_t test_vrndaq_f16(float16x8_t a) {
586586
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <4 x i16>
587587
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
588588
// CHECK-NEXT: [[VRNDM_V_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>
589-
// CHECK-NEXT: [[VRNDM_V1_I:%.*]] = call <4 x half> @llvm.arm.neon.vrintm.v4f16(<4 x half> [[VRNDM_V_I]])
589+
// CHECK-NEXT: [[VRNDM_V1_I:%.*]] = call <4 x half> @llvm.floor.v4f16(<4 x half> [[VRNDM_V_I]])
590590
// CHECK-NEXT: [[VRNDM_V2_I:%.*]] = bitcast <4 x half> [[VRNDM_V1_I]] to <8 x i8>
591591
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[VRNDM_V2_I]] to <4 x i16>
592592
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to <4 x half>
@@ -602,7 +602,7 @@ float16x4_t test_vrndm_f16(float16x4_t a) {
602602
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <8 x i16>
603603
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[TMP0]] to <16 x i8>
604604
// CHECK-NEXT: [[VRNDMQ_V_I:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>
605-
// CHECK-NEXT: [[VRNDMQ_V1_I:%.*]] = call <8 x half> @llvm.arm.neon.vrintm.v8f16(<8 x half> [[VRNDMQ_V_I]])
605+
// CHECK-NEXT: [[VRNDMQ_V1_I:%.*]] = call <8 x half> @llvm.floor.v8f16(<8 x half> [[VRNDMQ_V_I]])
606606
// CHECK-NEXT: [[VRNDMQ_V2_I:%.*]] = bitcast <8 x half> [[VRNDMQ_V1_I]] to <16 x i8>
607607
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[VRNDMQ_V2_I]] to <8 x i16>
608608
// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP2]] to <8 x half>

‎llvm/include/llvm/IR/IntrinsicsARM.td‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -682,7 +682,6 @@ def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
682682
def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
683683
def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
684684
def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
685-
def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
686685
def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
687686

688687
// De-interleaving vector loads from N-element structures.

‎llvm/lib/IR/AutoUpgrade.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -719,6 +719,7 @@ static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F,
719719
.StartsWith("vqaddu.", Intrinsic::uadd_sat)
720720
.StartsWith("vqsubs.", Intrinsic::ssub_sat)
721721
.StartsWith("vqsubu.", Intrinsic::usub_sat)
722+
.StartsWith("vrintm.", Intrinsic::floor)
722723
.Default(Intrinsic::not_intrinsic);
723724
if (ID != Intrinsic::not_intrinsic) {
724725
NewFn = Intrinsic::getOrInsertDeclaration(F->getParent(), ID,

‎llvm/lib/Target/ARM/ARMISelLowering.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1543,6 +1543,11 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
15431543
setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal);
15441544
setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);
15451545

1546+
if (Subtarget->hasV8Ops()) {
1547+
setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal);
1548+
setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1549+
}
1550+
15461551
if (Subtarget->hasFullFP16()) {
15471552
setOperationAction(ISD::FMINNUM, MVT::v4f16, Legal);
15481553
setOperationAction(ISD::FMAXNUM, MVT::v4f16, Legal);
@@ -1553,6 +1558,9 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
15531558
setOperationAction(ISD::FMAXIMUM, MVT::v4f16, Legal);
15541559
setOperationAction(ISD::FMINIMUM, MVT::v8f16, Legal);
15551560
setOperationAction(ISD::FMAXIMUM, MVT::v8f16, Legal);
1561+
1562+
setOperationAction(ISD::FFLOOR, MVT::v4f16, Legal);
1563+
setOperationAction(ISD::FFLOOR, MVT::v8f16, Legal);
15561564
}
15571565
}
15581566

‎llvm/lib/Target/ARM/ARMInstrNEON.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7316,7 +7316,7 @@ defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
73167316
defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
73177317
defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
73187318
defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
7319-
defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
7319+
defm VRINTMN : VRINT_FPI<"m", 0b101, ffloor>;
73207320
defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
73217321

73227322
// Cryptography instructions

‎llvm/test/CodeGen/ARM/vrint.ll‎

Lines changed: 4 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -813,21 +813,7 @@ define <4 x half> @frintm_4h(<4 x half> %A) nounwind {
813813
;
814814
; CHECK-FP16-LABEL: frintm_4h:
815815
; CHECK-FP16: @ %bb.0:
816-
; CHECK-FP16-NEXT: vmovx.f16 s2, s0
817-
; CHECK-FP16-NEXT: vrintm.f16 s2, s2
818-
; CHECK-FP16-NEXT: vmov r0, s2
819-
; CHECK-FP16-NEXT: vrintm.f16 s2, s0
820-
; CHECK-FP16-NEXT: vmov r1, s2
821-
; CHECK-FP16-NEXT: vrintm.f16 s2, s1
822-
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
823-
; CHECK-FP16-NEXT: vrintm.f16 s0, s0
824-
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
825-
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
826-
; CHECK-FP16-NEXT: vmov r0, s2
827-
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
828-
; CHECK-FP16-NEXT: vmov r0, s0
829-
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
830-
; CHECK-FP16-NEXT: vorr d0, d16, d16
816+
; CHECK-FP16-NEXT: vrintm.f16 d0, d0
831817
; CHECK-FP16-NEXT: bx lr
832818
%tmp3 = call <4 x half> @llvm.floor.v4f16(<4 x half> %A)
833819
ret <4 x half> %tmp3
@@ -977,35 +963,7 @@ define <8 x half> @frintm_8h(<8 x half> %A) nounwind {
977963
;
978964
; CHECK-FP16-LABEL: frintm_8h:
979965
; CHECK-FP16: @ %bb.0:
980-
; CHECK-FP16-NEXT: vmovx.f16 s4, s2
981-
; CHECK-FP16-NEXT: vrintm.f16 s4, s4
982-
; CHECK-FP16-NEXT: vmov r0, s4
983-
; CHECK-FP16-NEXT: vrintm.f16 s4, s2
984-
; CHECK-FP16-NEXT: vmov r1, s4
985-
; CHECK-FP16-NEXT: vrintm.f16 s4, s3
986-
; CHECK-FP16-NEXT: vmov.16 d17[0], r1
987-
; CHECK-FP16-NEXT: vmov.16 d17[1], r0
988-
; CHECK-FP16-NEXT: vmov r0, s4
989-
; CHECK-FP16-NEXT: vmovx.f16 s4, s3
990-
; CHECK-FP16-NEXT: vrintm.f16 s4, s4
991-
; CHECK-FP16-NEXT: vmov.16 d17[2], r0
992-
; CHECK-FP16-NEXT: vmov r0, s4
993-
; CHECK-FP16-NEXT: vmovx.f16 s4, s0
994-
; CHECK-FP16-NEXT: vrintm.f16 s4, s4
995-
; CHECK-FP16-NEXT: vmov.16 d17[3], r0
996-
; CHECK-FP16-NEXT: vmov r0, s4
997-
; CHECK-FP16-NEXT: vrintm.f16 s4, s0
998-
; CHECK-FP16-NEXT: vmovx.f16 s0, s1
999-
; CHECK-FP16-NEXT: vmov r1, s4
1000-
; CHECK-FP16-NEXT: vrintm.f16 s4, s1
1001-
; CHECK-FP16-NEXT: vrintm.f16 s0, s0
1002-
; CHECK-FP16-NEXT: vmov.16 d16[0], r1
1003-
; CHECK-FP16-NEXT: vmov.16 d16[1], r0
1004-
; CHECK-FP16-NEXT: vmov r0, s4
1005-
; CHECK-FP16-NEXT: vmov.16 d16[2], r0
1006-
; CHECK-FP16-NEXT: vmov r0, s0
1007-
; CHECK-FP16-NEXT: vmov.16 d16[3], r0
1008-
; CHECK-FP16-NEXT: vorr q0, q8, q8
966+
; CHECK-FP16-NEXT: vrintm.f16 q0, q0
1009967
; CHECK-FP16-NEXT: bx lr
1010968
%tmp3 = call <8 x half> @llvm.floor.v8f16(<8 x half> %A)
1011969
ret <8 x half> %tmp3
@@ -1031,9 +989,7 @@ define <2 x float> @frintm_2s(<2 x float> %A) nounwind {
1031989
;
1032990
; CHECK-LABEL: frintm_2s:
1033991
; CHECK: @ %bb.0:
1034-
; CHECK-NEXT: vrintm.f32 s3, s1
1035-
; CHECK-NEXT: vrintm.f32 s2, s0
1036-
; CHECK-NEXT: vmov.f64 d0, d1
992+
; CHECK-NEXT: vrintm.f32 d0, d0
1037993
; CHECK-NEXT: bx lr
1038994
%tmp3 = call <2 x float> @llvm.floor.v2f32(<2 x float> %A)
1039995
ret <2 x float> %tmp3
@@ -1065,11 +1021,7 @@ define <4 x float> @frintm_4s(<4 x float> %A) nounwind {
10651021
;
10661022
; CHECK-LABEL: frintm_4s:
10671023
; CHECK: @ %bb.0:
1068-
; CHECK-NEXT: vrintm.f32 s7, s3
1069-
; CHECK-NEXT: vrintm.f32 s6, s2
1070-
; CHECK-NEXT: vrintm.f32 s5, s1
1071-
; CHECK-NEXT: vrintm.f32 s4, s0
1072-
; CHECK-NEXT: vorr q0, q1, q1
1024+
; CHECK-NEXT: vrintm.f32 q0, q0
10731025
; CHECK-NEXT: bx lr
10741026
%tmp3 = call <4 x float> @llvm.floor.v4f32(<4 x float> %A)
10751027
ret <4 x float> %tmp3

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