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Automerge: Sparc: Remove fixup kinds and specifiers for GOT10/GOT13/GOT22/PC10/PC22
Similar to f39696e
2 parents 89dd821 + b3e8b21 commit fe7cb8b

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9 files changed

+70
-66
lines changed

9 files changed

+70
-66
lines changed

‎llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@
1111
#include "TargetInfo/SparcTargetInfo.h"
1212
#include "llvm/ADT/SmallVector.h"
1313
#include "llvm/ADT/StringRef.h"
14+
#include "llvm/BinaryFormat/ELF.h"
1415
#include "llvm/MC/MCAsmMacro.h"
1516
#include "llvm/MC/MCContext.h"
1617
#include "llvm/MC/MCExpr.h"
@@ -1677,12 +1678,12 @@ SparcAsmParser::adjustPICRelocation(SparcMCExpr::Specifier VK,
16771678
switch(VK) {
16781679
default: break;
16791680
case SparcMCExpr::VK_LO:
1680-
VK = (hasGOTReference(subExpr) ? SparcMCExpr::VK_PC10
1681-
: SparcMCExpr::VK_GOT10);
1681+
VK = SparcMCExpr::Specifier(
1682+
hasGOTReference(subExpr) ? ELF::R_SPARC_PC10 : ELF::R_SPARC_GOT10);
16821683
break;
16831684
case SparcMCExpr::VK_HI:
1684-
VK = (hasGOTReference(subExpr) ? SparcMCExpr::VK_PC22
1685-
: SparcMCExpr::VK_GOT22);
1685+
VK = SparcMCExpr::Specifier(
1686+
hasGOTReference(subExpr) ? ELF::R_SPARC_PC22 : ELF::R_SPARC_GOT22);
16861687
break;
16871688
}
16881689
}

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp‎

Lines changed: 23 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
5353
case Sparc::fixup_sparc_hix22:
5454
return (~Value >> 10) & 0x3fffff;
5555

56-
case Sparc::fixup_sparc_pc22:
56+
case ELF::R_SPARC_PC22:
5757
case Sparc::fixup_sparc_hi22:
5858
case Sparc::fixup_sparc_lm:
5959
return (Value >> 10) & 0x3fffff;
@@ -64,7 +64,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
6464
case Sparc::fixup_sparc_lox10:
6565
return (Value & 0x3ff) | 0x1c00;
6666

67-
case Sparc::fixup_sparc_pc10:
67+
case ELF::R_SPARC_PC10:
6868
case Sparc::fixup_sparc_lo10:
6969
return Value & 0x3ff;
7070

@@ -136,8 +136,6 @@ namespace {
136136
{ "fixup_sparc_hh", 10, 22, 0 },
137137
{ "fixup_sparc_hm", 22, 10, 0 },
138138
{ "fixup_sparc_lm", 10, 22, 0 },
139-
{ "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
140-
{ "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
141139
{ "fixup_sparc_hix22", 10, 22, 0 },
142140
{ "fixup_sparc_lox10", 19, 13, 0 },
143141
};
@@ -154,28 +152,35 @@ namespace {
154152
{ "fixup_sparc_hh", 0, 22, 0 },
155153
{ "fixup_sparc_hm", 0, 10, 0 },
156154
{ "fixup_sparc_lm", 0, 22, 0 },
157-
{ "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
158-
{ "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
159155
{ "fixup_sparc_hix22", 0, 22, 0 },
160156
{ "fixup_sparc_lox10", 0, 13, 0 },
161157
};
162158
// clang-format on
163159

164-
// Fixup kinds from .reloc directive are like R_SPARC_NONE. They do
165-
// not require any extra processing.
166-
if (mc::isRelocation(Kind))
167-
return MCAsmBackend::getFixupKindInfo(FK_NONE);
160+
if (!mc::isRelocation(Kind)) {
161+
if (Kind < FirstTargetFixupKind)
162+
return MCAsmBackend::getFixupKindInfo(Kind);
163+
assert(unsigned(Kind - FirstTargetFixupKind) <
164+
Sparc::NumTargetFixupKinds &&
165+
"Invalid kind!");
166+
if (Endian == llvm::endianness::little)
167+
return InfosLE[Kind - FirstTargetFixupKind];
168168

169-
if (Kind < FirstTargetFixupKind)
170-
return MCAsmBackend::getFixupKindInfo(Kind);
169+
return InfosBE[Kind - FirstTargetFixupKind];
170+
}
171171

172-
assert(unsigned(Kind - FirstTargetFixupKind) <
173-
Sparc::NumTargetFixupKinds &&
174-
"Invalid kind!");
172+
MCFixupKindInfo Info{};
173+
switch (uint16_t(Kind)) {
174+
case ELF::R_SPARC_PC10:
175+
Info = {"", 22, 10, MCFixupKindInfo::FKF_IsPCRel};
176+
break;
177+
case ELF::R_SPARC_PC22:
178+
Info = {"", 10, 22, MCFixupKindInfo::FKF_IsPCRel};
179+
break;
180+
}
175181
if (Endian == llvm::endianness::little)
176-
return InfosLE[Kind - FirstTargetFixupKind];
177-
178-
return InfosBE[Kind - FirstTargetFixupKind];
182+
Info.TargetOffset = 32 - Info.TargetOffset - Info.TargetSize;
183+
return Info;
179184
}
180185

181186
bool shouldForceRelocation(const MCAssembler &, const MCFixup &,

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -95,8 +95,6 @@ unsigned SparcELFObjectWriter::getRelocType(MCContext &Ctx,
9595
case Sparc::fixup_sparc_br19: return ELF::R_SPARC_WDISP19;
9696
case Sparc::fixup_sparc_br16:
9797
return ELF::R_SPARC_WDISP16;
98-
case Sparc::fixup_sparc_pc22: return ELF::R_SPARC_PC22;
99-
case Sparc::fixup_sparc_pc10: return ELF::R_SPARC_PC10;
10098
}
10199
}
102100

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -48,12 +48,6 @@ namespace llvm {
4848
/// fixup_sparc_lm - 22-bit fixup corresponding to %lm(foo)
4949
fixup_sparc_lm,
5050

51-
/// fixup_sparc_pc22 - 22-bit fixup corresponding to %pc22(foo)
52-
fixup_sparc_pc22,
53-
54-
/// fixup_sparc_pc10 - 10-bit fixup corresponding to %pc10(foo)
55-
fixup_sparc_pc10,
56-
5751
/// 22-bit fixup corresponding to %hix(foo)
5852
fixup_sparc_hix22,
5953
/// 13-bit fixup corresponding to %lox(foo)

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp‎

Lines changed: 10 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -51,11 +51,11 @@ StringRef SparcMCExpr::getSpecifierName(SparcMCExpr::Specifier S) {
5151
case VK_HM: return "hm";
5252
case VK_LM: return "lm";
5353
// FIXME: use %pc22/%pc10, if system assembler supports them.
54-
case VK_PC22: return "hi";
55-
case VK_PC10: return "lo";
56-
case VK_GOT22: return "hi";
57-
case VK_GOT10: return "lo";
58-
case VK_GOT13: return {};
54+
case ELF::R_SPARC_PC22: return "hi";
55+
case ELF::R_SPARC_PC10: return "lo";
56+
case ELF::R_SPARC_GOT22: return "hi";
57+
case ELF::R_SPARC_GOT10: return "lo";
58+
case ELF::R_SPARC_GOT13: return {};
5959
case VK_R_DISP32: return "r_disp32";
6060
case VK_TLS_GD_HI22: return "tgd_hi22";
6161
case VK_TLS_GD_LO10: return "tgd_lo10";
@@ -97,11 +97,11 @@ SparcMCExpr::Specifier SparcMCExpr::parseSpecifier(StringRef name) {
9797
.Case("hm", VK_HM)
9898
.Case("ulo", VK_HM) // Nonstandard GNU extension
9999
.Case("lm", VK_LM)
100-
.Case("pc22", VK_PC22)
101-
.Case("pc10", VK_PC10)
102-
.Case("got22", VK_GOT22)
103-
.Case("got10", VK_GOT10)
104-
.Case("got13", VK_GOT13)
100+
.Case("pc22", (SparcMCExpr::Specifier)ELF::R_SPARC_PC22)
101+
.Case("pc10", (SparcMCExpr::Specifier)ELF::R_SPARC_PC10)
102+
.Case("got22", (SparcMCExpr::Specifier)ELF::R_SPARC_GOT22)
103+
.Case("got10", (SparcMCExpr::Specifier)ELF::R_SPARC_GOT10)
104+
.Case("got13", (SparcMCExpr::Specifier)ELF::R_SPARC_GOT13)
105105
.Case("r_disp32", VK_R_DISP32)
106106
.Case("tgd_hi22", VK_TLS_GD_HI22)
107107
.Case("tgd_lo10", VK_TLS_GD_LO10)
@@ -140,11 +140,6 @@ uint16_t SparcMCExpr::getFixupKind() const {
140140
case VK_HH: return Sparc::fixup_sparc_hh;
141141
case VK_HM: return Sparc::fixup_sparc_hm;
142142
case VK_LM: return Sparc::fixup_sparc_lm;
143-
case VK_PC22: return Sparc::fixup_sparc_pc22;
144-
case VK_PC10: return Sparc::fixup_sparc_pc10;
145-
case VK_GOT22: return ELF::R_SPARC_GOT22;
146-
case VK_GOT10: return ELF::R_SPARC_GOT10;
147-
case VK_GOT13: return ELF::R_SPARC_GOT13;
148143
case VK_TLS_GD_HI22: return ELF::R_SPARC_TLS_GD_HI22;
149144
case VK_TLS_GD_LO10: return ELF::R_SPARC_TLS_GD_LO10;
150145
case VK_TLS_GD_ADD: return ELF::R_SPARC_TLS_GD_ADD;

‎llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -29,11 +29,6 @@ class SparcMCExpr : public MCTargetExpr {
2929
VK_HH,
3030
VK_HM,
3131
VK_LM,
32-
VK_PC22,
33-
VK_PC10,
34-
VK_GOT22,
35-
VK_GOT10,
36-
VK_GOT13,
3732
VK_R_DISP32,
3833
VK_TLS_GD_HI22,
3934
VK_TLS_GD_LO10,

‎llvm/lib/Target/Sparc/SparcAsmPrinter.cpp‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -88,9 +88,9 @@ static MCOperand createPCXCallOP(MCSymbol *Label,
8888
return MCOperand::createExpr(MCSymbolRefExpr::create(Label, OutContext));
8989
}
9090

91-
static MCOperand createPCXRelExprOp(SparcMCExpr::Specifier Kind,
92-
MCSymbol *GOTLabel, MCSymbol *StartLabel,
93-
MCSymbol *CurLabel, MCContext &OutContext) {
91+
static MCOperand createPCXRelExprOp(uint16_t Spec, MCSymbol *GOTLabel,
92+
MCSymbol *StartLabel, MCSymbol *CurLabel,
93+
MCContext &OutContext) {
9494
const MCSymbolRefExpr *GOT = MCSymbolRefExpr::create(GOTLabel, OutContext);
9595
const MCSymbolRefExpr *Start = MCSymbolRefExpr::create(StartLabel,
9696
OutContext);
@@ -99,8 +99,8 @@ static MCOperand createPCXRelExprOp(SparcMCExpr::Specifier Kind,
9999

100100
const MCBinaryExpr *Sub = MCBinaryExpr::createSub(Cur, Start, OutContext);
101101
const MCBinaryExpr *Add = MCBinaryExpr::createAdd(GOT, Sub, OutContext);
102-
const SparcMCExpr *expr = SparcMCExpr::create(Kind,
103-
Add, OutContext);
102+
const SparcMCExpr *expr =
103+
SparcMCExpr::create(SparcMCExpr::Specifier(Spec), Add, OutContext);
104104
return MCOperand::createExpr(expr);
105105
}
106106

@@ -249,12 +249,12 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
249249
EmitRDPC(*OutStreamer, RegO7, STI);
250250
}
251251
OutStreamer->emitLabel(SethiLabel);
252-
MCOperand hiImm = createPCXRelExprOp(SparcMCExpr::VK_PC22, GOTLabel,
253-
StartLabel, SethiLabel, OutContext);
252+
MCOperand hiImm = createPCXRelExprOp(ELF::R_SPARC_PC22, GOTLabel, StartLabel,
253+
SethiLabel, OutContext);
254254
EmitSETHI(*OutStreamer, hiImm, MCRegOP, STI);
255255
OutStreamer->emitLabel(EndLabel);
256-
MCOperand loImm = createPCXRelExprOp(SparcMCExpr::VK_PC10, GOTLabel,
257-
StartLabel, EndLabel, OutContext);
256+
MCOperand loImm = createPCXRelExprOp(ELF::R_SPARC_PC10, GOTLabel, StartLabel,
257+
EndLabel, OutContext);
258258
EmitOR(*OutStreamer, MCRegOP, loImm, MCRegOP, STI);
259259
EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
260260
}

‎llvm/lib/Target/Sparc/SparcISelLowering.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2180,10 +2180,10 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
21802180
if (picLevel == PICLevel::SmallPIC) {
21812181
// This is the pic13 code model, the GOT is known to be smaller than 8KiB.
21822182
Idx = DAG.getNode(SPISD::Lo, DL, Op.getValueType(),
2183-
withTargetFlags(Op, SparcMCExpr::VK_GOT13, DAG));
2183+
withTargetFlags(Op, ELF::R_SPARC_GOT13, DAG));
21842184
} else {
21852185
// This is the pic32 code model, the GOT is known to be smaller than 4GB.
2186-
Idx = makeHiLoPair(Op, SparcMCExpr::VK_GOT22, SparcMCExpr::VK_GOT10, DAG);
2186+
Idx = makeHiLoPair(Op, ELF::R_SPARC_GOT22, ELF::R_SPARC_GOT10, DAG);
21872187
}
21882188

21892189
SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);

‎llvm/test/MC/Sparc/relocation-specifier.s‎

Lines changed: 21 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,8 @@
2424
# READELF: TLS GLOBAL DEFAULT UND s_tgd_lo10
2525
# READELF: TLS GLOBAL DEFAULT UND s_tgd_add
2626

27+
main:
28+
2729
# ASM: or %g1, %lo(sym), %g3
2830
# ASM-NEXT: sethi %hi(sym), %l0
2931
# ASM-NEXT: sethi %h44(sym), %l0
@@ -40,16 +42,30 @@ sethi %h44(sym), %l0
4042
or %g1, %m44(sym), %g3
4143
or %g1, %l44(sym), %g3
4244

45+
## FIXME: Emit %pc22/%pc10
46+
# ASM: sethi %hi(sym), %o1
47+
# ASM-NEXT: or %o1, %lo(sym), %o1
48+
# OBJDUMP: sethi 0x0, %o1
49+
# OBJDUMP-NEXT: R_SPARC_PC22 sym
50+
# OBJDUMP-NEXT: or %o1, 0x0, %o1
51+
# OBJDUMP-NEXT: R_SPARC_PC10 sym
52+
# OBJDUMP-NEXT: sethi 0x3fffff, %o1
53+
# OBJDUMP-NEXT: or %o1, 0x3e0, %o1
54+
sethi %pc22(sym), %o1
55+
or %o1, %pc10(sym), %o1
56+
sethi %pc22(main), %o1
57+
or %o1, %pc10(main), %o1
58+
4359
# ASM: sethi %hh(sym), %l0
4460
# ASM-NEXT: sethi %hh(sym), %l0
4561
# ASM-NEXT: or %g1, %hm(sym), %g3
4662
# ASM-NEXT: or %g1, %hm(sym), %g3
4763
# ASM-NEXT: sethi %lm(sym), %l0
48-
# OBJDUMP: 0000014: R_SPARC_HH22 sym
49-
# OBJDUMP: 0000018: R_SPARC_HH22 sym
50-
# OBJDUMP: 000001c: R_SPARC_HM10 sym
51-
# OBJDUMP: 0000020: R_SPARC_HM10 sym
52-
# OBJDUMP: 0000024: R_SPARC_LM22 sym
64+
# OBJDUMP: R_SPARC_HH22 sym
65+
# OBJDUMP: R_SPARC_HH22 sym
66+
# OBJDUMP: R_SPARC_HM10 sym
67+
# OBJDUMP: R_SPARC_HM10 sym
68+
# OBJDUMP: R_SPARC_LM22 sym
5369
sethi %hh(sym), %l0
5470
sethi %uhi(sym), %l0
5571
or %g1, %hm(sym), %g3

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