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| 1 | +From ccfc44521cb9133569b1ace1c51efb80a4aaf925 Mon Sep 17 00:00:00 2001 |
| 2 | +From: Alex Ling <ling_kasim@hotmail.com> |
| 3 | +Date: Mon, 16 Mar 2026 16:02:50 +0800 |
| 4 | +Subject: [PATCH 3/3] arm64: dts: Switch to downstream sdhc driver for Odin2 |
| 5 | + |
| 6 | +Signed-off-by: Alex Ling <ling_kasim@hotmail.com> |
| 7 | +--- |
| 8 | + .../arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts | 86 +++++++++++++++++ |
| 9 | + .../boot/dts/qcom/qcs8550-ayn-odin2portal.dts | 95 +++++++++++++++++++ |
| 10 | + 2 files changed, 181 insertions(+) |
| 11 | + |
| 12 | +diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts |
| 13 | +index 98cf638b24f4..08fbffc250b3 100644 |
| 14 | +--- a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts |
| 15 | ++++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2.dts |
| 16 | +@@ -321,3 +321,89 @@ &spk_amp_r { |
| 17 | + firmware-name = "qcom/sm8550/ayn/odin2/aw883xx_acf.bin"; |
| 18 | + }; |
| 19 | + |
| 20 | ++/delete-node/ &sdhc_2; |
| 21 | ++ |
| 22 | ++&soc { |
| 23 | ++ sdhc_2: sdhci@8804000 { |
| 24 | ++ compatible = "qcom,sdhci-msm-v5-downstream"; |
| 25 | ++ reg = <0 0x08804000 0 0x1000>; |
| 26 | ++ reg-names = "hc_mem"; |
| 27 | ++ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, |
| 28 | ++ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; |
| 29 | ++ interrupt-names = "hc_irq", "pwr_irq"; |
| 30 | ++ bus-width = <4>; |
| 31 | ++ no-sdio; |
| 32 | ++ no-mmc; |
| 33 | ++ qcom,restore-after-cx-collapse; |
| 34 | ++ qcom,uses_level_shifter; |
| 35 | ++ qcom,dll_lock_bist_fail_wa; |
| 36 | ++ clocks = <&gcc GCC_SDCC2_AHB_CLK>, |
| 37 | ++ <&gcc GCC_SDCC2_APPS_CLK>; |
| 38 | ++ clock-names = "iface", "core"; |
| 39 | ++ |
| 40 | ++ /* |
| 41 | ++ * DLL HSR settings. Refer go/hsr - <Target> DLL settings. |
| 42 | ++ * Note that the DLL_CONFIG_2 value is not passed from the |
| 43 | ++ * device tree, 0 but it is calculated in the driver. |
| 44 | ++ */ |
| 45 | ++ qcom,dll-hsr-list = <0x0007442C 0x0 0x10 |
| 46 | ++ 0x090106C0 0x80040868>; |
| 47 | ++ |
| 48 | ++ iommus = <&apps_smmu 0x540 0x0>; |
| 49 | ++ dma-coherent; |
| 50 | ++ interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, |
| 51 | ++ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; |
| 52 | ++ interconnect-names = "sdhc-ddr", "cpu-sdhc"; |
| 53 | ++ |
| 54 | ++ qcom,msm-bus,name = "sdhc2"; |
| 55 | ++ qcom,msm-bus,num-cases = <0x07>; |
| 56 | ++ qcom,msm-bus,num-paths = <0x02>; |
| 57 | ++ qcom,msm-bus,vectors-KBps = <0x00 0x00 0x00 0x00 0x416 0xc80 0x640 0x640 0xff50 0x3d090 0x186a0 0x208c8 0x1fe9e 0x3d090 0x208c8 0x208c8 0x3fd3e 0x3d090 0x249f0 0x208c8 0x3fd3e 0xc3500 0x493e0 0x493e0 0x146cc2 0x3e8000 0x146cc2 0x3e8000>; |
| 58 | ++ qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; |
| 59 | ++ |
| 60 | ++ operating-points-v2 = <&sdhc2_opp_table>; |
| 61 | ++ |
| 62 | ++ vdd-supply = <&vreg_l9b_2p9>; |
| 63 | ++ qcom,vdd-voltage-level = <0x2d0370 0x2d2a80>; |
| 64 | ++ qcom,vdd-current-level = <0x00 0xc3500>; |
| 65 | ++ |
| 66 | ++ vdd-io-supply = <&vreg_l8b_1p8>; |
| 67 | ++ qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; |
| 68 | ++ qcom,vdd-io-current-level = <0x00 0x15e0>; |
| 69 | ++ |
| 70 | ++ pinctrl-names = "default", "sleep"; |
| 71 | ++ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; |
| 72 | ++ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; |
| 73 | ++ |
| 74 | ++ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; |
| 75 | ++ resets = <&gcc GCC_SDCC2_BCR>; |
| 76 | ++ reset-names = "core_reset"; |
| 77 | ++ |
| 78 | ++ qos0 { |
| 79 | ++ mask = <0xf0>; |
| 80 | ++ vote = <0x2c>; |
| 81 | ++ }; |
| 82 | ++ |
| 83 | ++ qos1 { |
| 84 | ++ mask = <0x0f>; |
| 85 | ++ vote = <0x2c>; |
| 86 | ++ }; |
| 87 | ++ |
| 88 | ++ sdhc2_opp_table: opp-table { |
| 89 | ++ compatible = "operating-points-v2"; |
| 90 | ++ |
| 91 | ++ opp-100000000 { |
| 92 | ++ opp-hz = <0x00 0x5f5e100>; |
| 93 | ++ opp-peak-kBps = <0x27100 0x186a0>; |
| 94 | ++ opp-avg-kBps = <0xc350 0x00>; |
| 95 | ++ }; |
| 96 | ++ |
| 97 | ++ opp-202000000 { |
| 98 | ++ opp-hz = <0x00 0xc0a4680>; |
| 99 | ++ opp-peak-kBps = <0x30d40 0x1d4c0>; |
| 100 | ++ opp-avg-kBps = <0x19640 0x00>; |
| 101 | ++ }; |
| 102 | ++ }; |
| 103 | ++ }; |
| 104 | ++}; |
| 105 | ++ |
| 106 | +diff --git a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2portal.dts b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2portal.dts |
| 107 | +index 70e7e64dc879..c0daa80caa31 100644 |
| 108 | +--- a/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2portal.dts |
| 109 | ++++ b/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2portal.dts |
| 110 | +@@ -292,3 +292,98 @@ &spk_amp_r { |
| 111 | + firmware-name = "qcom/sm8550/ayn/odin2portal/aw883xx_acf.bin"; |
| 112 | + }; |
| 113 | + |
| 114 | ++/delete-node/ &sdhc2_opp_table; |
| 115 | ++/delete-node/ &sdhc_2; |
| 116 | ++ |
| 117 | ++&soc { |
| 118 | ++ qcom_tzlog: qcom_tzlog { |
| 119 | ++ status = "disabled"; |
| 120 | ++ }; |
| 121 | ++ |
| 122 | ++ arch_timer: arch_timer { |
| 123 | ++ status = "disabled"; |
| 124 | ++ }; |
| 125 | ++ |
| 126 | ++ sdhc_2: sdhci@8804000 { |
| 127 | ++ compatible = "qcom,sdhci-msm-v5-downstream"; |
| 128 | ++ reg = <0 0x08804000 0 0x1000>; |
| 129 | ++ reg-names = "hc_mem"; |
| 130 | ++ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH 0>, |
| 131 | ++ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH 0>; |
| 132 | ++ interrupt-names = "hc_irq", "pwr_irq"; |
| 133 | ++ bus-width = <4>; |
| 134 | ++ no-sdio; |
| 135 | ++ no-mmc; |
| 136 | ++ qcom,restore-after-cx-collapse; |
| 137 | ++ qcom,uses_level_shifter; |
| 138 | ++ qcom,dll_lock_bist_fail_wa; |
| 139 | ++ clocks = <&gcc GCC_SDCC2_AHB_CLK>, |
| 140 | ++ <&gcc GCC_SDCC2_APPS_CLK>; |
| 141 | ++ clock-names = "iface", "core"; |
| 142 | ++ |
| 143 | ++ /* |
| 144 | ++ * DLL HSR settings. Refer go/hsr - <Target> DLL settings. |
| 145 | ++ * Note that the DLL_CONFIG_2 value is not passed from the |
| 146 | ++ * device tree, but it is calculated in the driver. |
| 147 | ++ */ |
| 148 | ++ qcom,dll-hsr-list = <0x0007442C 0x0 0x10 |
| 149 | ++ 0x090106C0 0x80040868>; |
| 150 | ++ |
| 151 | ++ iommus = <&apps_smmu 0x540 0x0>; |
| 152 | ++ dma-coherent; |
| 153 | ++ interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, |
| 154 | ++ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; |
| 155 | ++ interconnect-names = "sdhc-ddr", "cpu-sdhc"; |
| 156 | ++ |
| 157 | ++ qcom,msm-bus,name = "sdhc2"; |
| 158 | ++ qcom,msm-bus,num-cases = <0x07>; |
| 159 | ++ qcom,msm-bus,num-paths = <0x02>; |
| 160 | ++ qcom,msm-bus,vectors-KBps = <0x00 0x00 0x00 0x00 0x416 0xc80 0x640 0x640 0xff50 0x3d090 0x186a0 0x208c8 0x1fe9e 0x3d090 0x208c8 0x208c8 0x3fd3e 0x3d090 0x249f0 0x208c8 0x3fd3e 0xc3500 0x493e0 0x493e0 0x146cc2 0x3e8000 0x146cc2 0x3e8000>; |
| 161 | ++ qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>; |
| 162 | ++ |
| 163 | ++ operating-points-v2 = <&sdhc2_opp_table>; |
| 164 | ++ |
| 165 | ++ vdd-supply = <&vreg_l9b_2p9>; |
| 166 | ++ qcom,vdd-voltage-level = <0x2d0370 0x2d2a80>; |
| 167 | ++ qcom,vdd-current-level = <0x00 0xc3500>; |
| 168 | ++ |
| 169 | ++ vdd-io-supply = <&vreg_l8b_1p8>; |
| 170 | ++ qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>; |
| 171 | ++ qcom,vdd-io-current-level = <0x00 0x15e0>; |
| 172 | ++ |
| 173 | ++ pinctrl-names = "default", "sleep"; |
| 174 | ++ pinctrl-0 = <&sdc2_default &sdc2_card_det_n>; |
| 175 | ++ pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>; |
| 176 | ++ |
| 177 | ++ cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; |
| 178 | ++ resets = <&gcc GCC_SDCC2_BCR>; |
| 179 | ++ reset-names = "core_reset"; |
| 180 | ++ |
| 181 | ++ qos0 { |
| 182 | ++ mask = <0xf0>; |
| 183 | ++ vote = <0x2c>; |
| 184 | ++ }; |
| 185 | ++ |
| 186 | ++ qos1 { |
| 187 | ++ mask = <0x0f>; |
| 188 | ++ vote = <0x2c>; |
| 189 | ++ }; |
| 190 | ++ |
| 191 | ++ sdhc2_opp_table: opp-table { |
| 192 | ++ compatible = "operating-points-v2"; |
| 193 | ++ |
| 194 | ++ opp-100000000 { |
| 195 | ++ opp-hz = <0x00 0x5f5e100>; |
| 196 | ++ opp-peak-kBps = <0x27100 0x186a0>; |
| 197 | ++ opp-avg-kBps = <0xc350 0x00>; |
| 198 | ++ }; |
| 199 | ++ |
| 200 | ++ opp-202000000 { |
| 201 | ++ opp-hz = <0x00 0xc0a4680>; |
| 202 | ++ opp-peak-kBps = <0x30d40 0x1d4c0>; |
| 203 | ++ opp-avg-kBps = <0x19640 0x00>; |
| 204 | ++ }; |
| 205 | ++ }; |
| 206 | ++ }; |
| 207 | ++}; |
| 208 | ++ |
| 209 | +-- |
| 210 | +2.43.0 |
| 211 | + |
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