patch: sm8250: current: add Retroid Pocket SM8250 Patch series

Signed-off-by: CodeChenL <2540735020@qq.com>

Author: CodeChenL

patch/kernel/archive/sm8250-6.18/0064-arm64-dts-qcom-sm8250-add-uart16-Signed-off-by-Teguh.patch

@@ -0,0 +1,53 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Teguh Sobirin <teguh@sobir.in>
+Date: Wed, 20 Nov 2024 22:58:09 +0700
+Subject: arm64: dts: qcom: sm8250: add uart16 Signed-off-by: Teguh Sobirin
+ <teguh@sobir.in>
+
+---
+ arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 ++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
++++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
+@@ -1153,6 +1153,23 @@ spi16: spi@888000 {
+ 				status = "disabled";
+ 			};
+ 
++			uart16: serial@888000 {
++				compatible = "qcom,geni-uart";
++				reg = <0 0x00888000 0 0x4000>;
++				clock-names = "se";
++				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
++				pinctrl-names = "default";
++				pinctrl-0 = <&qup_uart16_default>;
++				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
++				power-domains = <&rpmhpd RPMHPD_CX>;
++				operating-points-v2 = <&qup_opp_table>;
++				interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
++						<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
++				interconnect-names = "qup-core",
++						     "qup-config";
++				status = "disabled";
++			};
++
+ 			i2c17: i2c@88c000 {
+ 				compatible = "qcom,geni-i2c";
+ 				reg = <0 0x0088c000 0 0x4000>;
+@@ -5725,6 +5742,11 @@ qup_uart12_default: qup-uart12-default-state {
+ 				function = "qup12";
+ 			};
+ 
++			qup_uart16_default: qup-uart16-default-state {
++				pins = "gpio50", "gpio51";
++				function = "qup16";
++			};
++
+ 			qup_uart17_default: qup-uart17-default-state {
+ 				pins = "gpio52", "gpio53", "gpio54", "gpio55";
+ 				function = "qup17";
+-- 
+Armbian
+