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| 1 | +From f9aa935084d24fbbe5e7b2c62948a8f08b228f18 Mon Sep 17 00:00:00 2001 |
| 2 | +From: voapilro < [email protected]> |
| 3 | +Date: Mon, 6 May 2024 11:36:47 +0200 |
| 4 | +Subject: [PATCH 1/3] Fix memory size detection for 1.5GB Orange Pi Zero 3 |
| 5 | + board |
| 6 | + |
| 7 | +--- |
| 8 | + arch/arm/include/asm/arch-sunxi/dram.h | 1 + |
| 9 | + arch/arm/mach-sunxi/dram_helpers.c | 20 ++++++++++++++++++++ |
| 10 | + arch/arm/mach-sunxi/dram_sun50i_h616.c | 9 ++++++++- |
| 11 | + 3 files changed, 29 insertions(+), 1 deletion(-) |
| 12 | + |
| 13 | +diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h |
| 14 | +index 682daae6b1a..a1379631d62 100644 |
| 15 | +--- a/arch/arm/include/asm/arch-sunxi/dram.h |
| 16 | ++++ b/arch/arm/include/asm/arch-sunxi/dram.h |
| 17 | +@@ -41,5 +41,6 @@ |
| 18 | + void mctl_await_completion(u32 *reg, u32 mask, u32 val); |
| 19 | + bool mctl_mem_matches(u32 offset); |
| 20 | + bool mctl_mem_matches_base(u32 offset, ulong base); |
| 21 | ++bool mctl_mem_matches_top(ulong offset); |
| 22 | + |
| 23 | + #endif /* _SUNXI_DRAM_H */ |
| 24 | +diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c |
| 25 | +index cdf2750f1c5..36fabb3bcd5 100644 |
| 26 | +--- a/arch/arm/mach-sunxi/dram_helpers.c |
| 27 | ++++ b/arch/arm/mach-sunxi/dram_helpers.c |
| 28 | +@@ -40,4 +40,24 @@ bool mctl_mem_matches(u32 offset) |
| 29 | + return readl(CFG_SYS_SDRAM_BASE) == |
| 30 | + readl((ulong)CFG_SYS_SDRAM_BASE + offset); |
| 31 | + } |
| 32 | ++ |
| 33 | ++/* |
| 34 | ++ * Test if memory at offset matches memory at top of DRAM |
| 35 | ++ */ |
| 36 | ++bool mctl_mem_matches_top(ulong offset) |
| 37 | ++{ |
| 38 | ++ static const unsigned value= 0xaa55aa55; |
| 39 | ++ |
| 40 | ++ /* Take last usable memory address */ |
| 41 | ++ offset -= sizeof(unsigned); |
| 42 | ++ dsb(); |
| 43 | ++ /* Set zero at last usable memory address */ |
| 44 | ++ writel(0, (ulong)CONFIG_SYS_SDRAM_BASE + offset); |
| 45 | ++ dsb(); |
| 46 | ++ /* Set other value at last usable memory address */ |
| 47 | ++ writel(value, (ulong)CONFIG_SYS_SDRAM_BASE + offset); |
| 48 | ++ dsb(); |
| 49 | ++ /* Check if the same value is actually observed when reading back */ |
| 50 | ++ return readl((ulong)CONFIG_SYS_SDRAM_BASE + offset) == value; |
| 51 | ++} |
| 52 | + #endif |
| 53 | +diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c |
| 54 | +index c5c1331a4c3..5287ef79c43 100644 |
| 55 | +--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c |
| 56 | ++++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c |
| 57 | +@@ -1350,9 +1350,16 @@ static void mctl_auto_detect_dram_size(const struct dram_para *para, |
| 58 | + static unsigned long mctl_calc_size(const struct dram_config *config) |
| 59 | + { |
| 60 | + u8 width = config->bus_full_width ? 4 : 2; |
| 61 | ++ unsigned long size; |
| 62 | + |
| 63 | + /* 8 banks */ |
| 64 | +- return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; |
| 65 | ++ size = (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; |
| 66 | ++ |
| 67 | ++ /* Fix size if last usable memory address is not valid */ |
| 68 | ++ if (!mctl_mem_matches_top(size)) |
| 69 | ++ size = (size * 3) / 4; |
| 70 | ++ |
| 71 | ++ return size; |
| 72 | + } |
| 73 | + |
| 74 | + static const struct dram_para para = { |
| 75 | + |
| 76 | +From 371388504b9b67459dfd13d2585090961ad51cc5 Mon Sep 17 00:00:00 2001 |
| 77 | +From: voapilro < [email protected]> |
| 78 | +Date: Mon, 6 May 2024 15:13:29 +0200 |
| 79 | +Subject: [PATCH 2/3] Added some logs regarding memory size detection |
| 80 | + |
| 81 | +--- |
| 82 | + arch/arm/include/asm/arch-sunxi/dram.h | 1 + |
| 83 | + arch/arm/mach-sunxi/dram_helpers.c | 10 +++++++++- |
| 84 | + arch/arm/mach-sunxi/dram_sun50i_h616.c | 10 +++++++++- |
| 85 | + board/sunxi/board.c | 3 +-- |
| 86 | + 4 files changed, 20 insertions(+), 4 deletions(-) |
| 87 | + |
| 88 | +diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h |
| 89 | +index a1379631d62..c7543d35698 100644 |
| 90 | +--- a/arch/arm/include/asm/arch-sunxi/dram.h |
| 91 | ++++ b/arch/arm/include/asm/arch-sunxi/dram.h |
| 92 | +@@ -42,5 +42,6 @@ unsigned long sunxi_dram_init(void); |
| 93 | + bool mctl_mem_matches(u32 offset); |
| 94 | + bool mctl_mem_matches_base(u32 offset, ulong base); |
| 95 | + bool mctl_mem_matches_top(ulong offset); |
| 96 | ++ulong mctl_mem_address(ulong offset); |
| 97 | + |
| 98 | + #endif /* _SUNXI_DRAM_H */ |
| 99 | +diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c |
| 100 | +index 36fabb3bcd5..5a80159759c 100644 |
| 101 | +--- a/arch/arm/mach-sunxi/dram_helpers.c |
| 102 | ++++ b/arch/arm/mach-sunxi/dram_helpers.c |
| 103 | +@@ -49,7 +49,7 @@ bool mctl_mem_matches_top(ulong offset) |
| 104 | + static const unsigned value= 0xaa55aa55; |
| 105 | + |
| 106 | + /* Take last usable memory address */ |
| 107 | +- offset -= sizeof(unsigned); |
| 108 | ++ offset -= sizeof(value); |
| 109 | + dsb(); |
| 110 | + /* Set zero at last usable memory address */ |
| 111 | + writel(0, (ulong)CONFIG_SYS_SDRAM_BASE + offset); |
| 112 | +@@ -60,4 +60,12 @@ bool mctl_mem_matches_top(ulong offset) |
| 113 | + /* Check if the same value is actually observed when reading back */ |
| 114 | + return readl((ulong)CONFIG_SYS_SDRAM_BASE + offset) == value; |
| 115 | + } |
| 116 | ++ |
| 117 | ++/* |
| 118 | ++ * Get memory address at offset of DRAM |
| 119 | ++ */ |
| 120 | ++ulong mctl_mem_address(ulong offset) |
| 121 | ++{ |
| 122 | ++ return (ulong)CONFIG_SYS_SDRAM_BASE + offset; |
| 123 | ++} |
| 124 | + #endif |
| 125 | +diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c |
| 126 | +index 5287ef79c43..6a247ecaa05 100644 |
| 127 | +--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c |
| 128 | ++++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c |
| 129 | +@@ -1355,9 +1355,17 @@ static unsigned long mctl_calc_size(const struct dram_config *config) |
| 130 | + /* 8 banks */ |
| 131 | + size = (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; |
| 132 | + |
| 133 | ++ printf("DRAM base address is defined as 0x%lx\n", mctl_mem_address(0)); |
| 134 | ++ printf("DRAM has %u b/raw, %u b/col, %u B/width, %u #rank and 8 #bank\n", |
| 135 | ++ (unsigned)config->rows, (unsigned)config->cols, |
| 136 | ++ (unsigned)width, (unsigned)config->ranks); |
| 137 | ++ printf("DRAM top address must be less than 0x%lx\n", size); |
| 138 | ++ |
| 139 | + /* Fix size if last usable memory address is not valid */ |
| 140 | +- if (!mctl_mem_matches_top(size)) |
| 141 | ++ if (!mctl_mem_matches_top(size)) { |
| 142 | + size = (size * 3) / 4; |
| 143 | ++ printf("DRAM top address must be less than 0x%lx\n", size); |
| 144 | ++ } |
| 145 | + |
| 146 | + return size; |
| 147 | + } |
| 148 | +diff --git a/board/sunxi/board.c b/board/sunxi/board.c |
| 149 | +index 8c12c8deade..62228936774 100644 |
| 150 | +--- a/board/sunxi/board.c |
| 151 | ++++ b/board/sunxi/board.c |
| 152 | +@@ -632,9 +632,8 @@ void sunxi_board_init(void) |
| 153 | + power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON)); |
| 154 | + #endif |
| 155 | + #endif /* CONFIG_AXPxxx_POWER */ |
| 156 | +- printf("DRAM:"); |
| 157 | + gd->ram_size = sunxi_dram_init(); |
| 158 | +- printf(" %d MiB\n", (int)(gd->ram_size >> 20)); |
| 159 | ++ printf("DRAM: %d MiB\n", (int)(gd->ram_size >> 20)); |
| 160 | + if (!gd->ram_size) |
| 161 | + hang(); |
| 162 | + |
| 163 | + |
| 164 | +From 4b5089810e7adac0801185e82a39c5849bf2bb91 Mon Sep 17 00:00:00 2001 |
| 165 | +From: voapilro < [email protected]> |
| 166 | +Date: Mon, 6 May 2024 19:36:47 +0200 |
| 167 | +Subject: [PATCH 3/3] Updated name from CONFIG_SYS_SDRAM_BASE to |
| 168 | + CFG_SYS_SDRAM_BASE |
| 169 | + |
| 170 | +--- |
| 171 | + arch/arm/mach-sunxi/dram_helpers.c | 8 ++++---- |
| 172 | + 1 file changed, 4 insertions(+), 4 deletions(-) |
| 173 | + |
| 174 | +diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c |
| 175 | +index 5a80159759c..0d7fbac61bf 100644 |
| 176 | +--- a/arch/arm/mach-sunxi/dram_helpers.c |
| 177 | ++++ b/arch/arm/mach-sunxi/dram_helpers.c |
| 178 | +@@ -52,13 +52,13 @@ bool mctl_mem_matches_top(ulong offset) |
| 179 | + offset -= sizeof(value); |
| 180 | + dsb(); |
| 181 | + /* Set zero at last usable memory address */ |
| 182 | +- writel(0, (ulong)CONFIG_SYS_SDRAM_BASE + offset); |
| 183 | ++ writel(0, (ulong)CFG_SYS_SDRAM_BASE + offset); |
| 184 | + dsb(); |
| 185 | + /* Set other value at last usable memory address */ |
| 186 | +- writel(value, (ulong)CONFIG_SYS_SDRAM_BASE + offset); |
| 187 | ++ writel(value, (ulong)CFG_SYS_SDRAM_BASE + offset); |
| 188 | + dsb(); |
| 189 | + /* Check if the same value is actually observed when reading back */ |
| 190 | +- return readl((ulong)CONFIG_SYS_SDRAM_BASE + offset) == value; |
| 191 | ++ return readl((ulong)CFG_SYS_SDRAM_BASE + offset) == value; |
| 192 | + } |
| 193 | + |
| 194 | + /* |
| 195 | +@@ -66,6 +66,6 @@ bool mctl_mem_matches_top(ulong offset) |
| 196 | + */ |
| 197 | + ulong mctl_mem_address(ulong offset) |
| 198 | + { |
| 199 | +- return (ulong)CONFIG_SYS_SDRAM_BASE + offset; |
| 200 | ++ return (ulong)CFG_SYS_SDRAM_BASE + offset; |
| 201 | + } |
| 202 | + #endif |
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