diff --git a/config/kernel/linux-rockchip64-edge.config b/config/kernel/linux-rockchip64-edge.config index b26e00ae3bff..3e0dc3864eee 100644 --- a/config/kernel/linux-rockchip64-edge.config +++ b/config/kernel/linux-rockchip64-edge.config @@ -239,18 +239,22 @@ CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m CONFIG_NETFILTER_XT_TARGET_HMARK=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m CONFIG_NETFILTER_XT_TARGET_LED=m CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m @@ -347,19 +351,9 @@ CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m CONFIG_IP_NF_MATCH_RPFILTER=m CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m CONFIG_IP_NF_TARGET_REJECT=m CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_MANGLE=m CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_SECURITY=m -CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m @@ -374,24 +368,14 @@ CONFIG_IP6_NF_MATCH_MH=m CONFIG_IP6_NF_MATCH_RPFILTER=m CONFIG_IP6_NF_MATCH_RT=m CONFIG_IP6_NF_MATCH_SRH=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_SECURITY=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_AMONG=m CONFIG_BRIDGE_EBT_ARP=m @@ -1097,8 +1081,10 @@ CONFIG_RTW88_8821CS=m CONFIG_RTW88_8821CU=m CONFIG_RTW89=m CONFIG_RTW89_8851BE=m +CONFIG_RTW89_8851BU=m CONFIG_RTW89_8852AE=m CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852BU=m CONFIG_RTW89_8852BTE=m CONFIG_RTW89_8852CE=m CONFIG_RTW89_8922AE=m @@ -1701,7 +1687,6 @@ CONFIG_MFD_QCOM_PM8008=m CONFIG_RAVE_SP_CORE=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m -CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_88PG86X=m CONFIG_REGULATOR_ACT8865=y @@ -1977,10 +1962,7 @@ CONFIG_VIDEO_S5K5BAF=m CONFIG_VIDEO_S5K6A3=m CONFIG_VIDEO_CCS=m CONFIG_VIDEO_ET8EK8=m -CONFIG_VIDEO_AD5820=m -CONFIG_VIDEO_AK7375=m -CONFIG_VIDEO_DW9714=m -CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_CAMERA_LENS is not set CONFIG_VIDEO_ADP1653=m CONFIG_VIDEO_LM3560=m CONFIG_VIDEO_LM3646=m @@ -2111,7 +2093,6 @@ CONFIG_DRM_TIDSS=m CONFIG_DRM_GUD=m CONFIG_FB=y CONFIG_FB_UVESA=m -CONFIG_FIRMWARE_EDID=y CONFIG_LCD_CLASS_DEVICE=m CONFIG_LCD_OTM3225A=m CONFIG_BACKLIGHT_LM3533=m @@ -2164,7 +2145,6 @@ CONFIG_SND_USB_TONEPORT=m CONFIG_SND_USB_VARIAX=m CONFIG_SND_SOC=y CONFIG_SND_SOC_UTILS_KUNIT_TEST=m -CONFIG_SND_SOC_ADI=m CONFIG_SND_SOC_ADI_AXI_I2S=m CONFIG_SND_SOC_ADI_AXI_SPDIF=m CONFIG_SND_AMD_ACP_CONFIG=m @@ -2173,14 +2153,12 @@ CONFIG_SND_DESIGNWARE_I2S=m CONFIG_SND_SOC_FSL_AUDMIX=m CONFIG_SND_SOC_FSL_MICFIL=m CONFIG_SND_SOC_FSL_XCVR=m -CONFIG_SND_SOC_ROCKCHIP=y CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y CONFIG_SND_SOC_ROCKCHIP_PDM=y CONFIG_SND_SOC_ROCKCHIP_SAI=y CONFIG_SND_SOC_ROCKCHIP_SPDIF=y CONFIG_SND_SOC_ROCKCHIP_MAX98090=y CONFIG_SND_SOC_ROCKCHIP_RT5645=y -CONFIG_SND_SOC_ROCKCHIP_RT5651=y CONFIG_SND_SOC_RK3288_HDMI_ANALOG=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m CONFIG_SND_SOC_XILINX_I2S=m @@ -2691,7 +2669,6 @@ CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_ISL12026=m CONFIG_RTC_DRV_X1205=m CONFIG_RTC_DRV_PCF8523=m -CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_PCF85363=m CONFIG_RTC_DRV_PCF8563=m CONFIG_RTC_DRV_PCF8583=m @@ -2726,6 +2703,7 @@ CONFIG_RTC_DRV_PCF2123=m CONFIG_RTC_DRV_MCP795=m CONFIG_RTC_DRV_DS3232=m CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_RV3029C2=m CONFIG_RTC_DRV_RX6110=m CONFIG_RTC_DRV_EFI=y @@ -3150,7 +3128,6 @@ CONFIG_XFS_FS=m # CONFIG_XFS_SUPPORT_ASCII_CI is not set CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y -CONFIG_XFS_RT=y CONFIG_GFS2_FS=m CONFIG_GFS2_FS_LOCKING_DLM=y CONFIG_OCFS2_FS=m @@ -3400,9 +3377,6 @@ CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m CONFIG_CRYPTO_NHPOLY1305_NEON=m CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_SHA1_ARM64_CE=y -CONFIG_CRYPTO_SHA512_ARM64=y -CONFIG_CRYPTO_SHA512_ARM64_CE=m CONFIG_CRYPTO_SHA3_ARM64=m CONFIG_CRYPTO_SM3_NEON=m CONFIG_CRYPTO_SM3_ARM64_CE=m @@ -3451,6 +3425,7 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_MEMORY_INIT=y CONFIG_TEST_LOCKUP=m CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_TRACEFS_AUTOMOUNT_DEPRECATED is not set CONFIG_FTRACE_SYSCALLS=y CONFIG_BPF_KPROBE_OVERRIDE=y CONFIG_KUNIT=m diff --git a/config/sources/families/include/rockchip64_common.inc b/config/sources/families/include/rockchip64_common.inc index 508ac1fa8c39..7abe372c0108 100644 --- a/config/sources/families/include/rockchip64_common.inc +++ b/config/sources/families/include/rockchip64_common.inc @@ -33,7 +33,7 @@ case $BRANCH in ;; edge) - declare -g KERNEL_MAJOR_MINOR="6.16" + declare -g KERNEL_MAJOR_MINOR="6.17" declare -g LINUXFAMILY=rockchip64 declare -g LINUXCONFIG='linux-rockchip64-'$BRANCH ;; diff --git a/lib/functions/compilation/patch/drivers_network.sh b/lib/functions/compilation/patch/drivers_network.sh index cca1b31c4f8b..eeac583d064a 100644 --- a/lib/functions/compilation/patch/drivers_network.sh +++ b/lib/functions/compilation/patch/drivers_network.sh @@ -373,7 +373,7 @@ driver_rtl8852bs() { if linux-version compare "${version}" ge 6.1 && [[ "${LINUXFAMILY}" == spacemit || "${LINUXFAMILY}" == rk35xx || "${LINUXFAMILY}" == rockchip64 ]]; then # Attach to specific commit - local rtl8852bs_ver='commit:1515f70506fb4d916323addaf5b410d14ed962e9' # Commit date: Sept 8, 2025 (please update when updating commit ref) + local rtl8852bs_ver='commit:15811ffdf575baabbd1cd46a306e9544a7f02846' # Commit date: Oct 2, 2025 (please update when updating commit ref) display_alert "Adding" "Wireless drivers for Realtek 8852BS SDIO chipset ${rtl8852bs_ver}" "info" @@ -559,6 +559,11 @@ driver_uwe5622() { if linux-version compare "${version}" ge 6.16; then process_patch_file "${SRC}/patch/misc/wireless-uwe5622/uwe5622-v6.16.patch" "applying" fi + + if linux-version compare "${version}" ge 6.17; then + process_patch_file "${SRC}/patch/misc/wireless-uwe5622/uwe5622-v6.17.patch" "applying" + fi + fi } @@ -660,7 +665,7 @@ driver_rtl8723DS() { if linux-version compare "${version}" ge 5.0; then # Attach to specific commit (was "branch:master") - local rtl8723dsver='commit:09a2b3e94d14cc2a0012d5b74101c6acf1ef0872' # Commit date: 2025-06-28 (please update when updating commit ref) + local rtl8723dsver='commit:39d0eedf4eaedfcf6e133413a389c5f8a70a7d1f' # Commit date: 2025-10-02 (please update when updating commit ref) display_alert "Adding" "Wireless drivers for Realtek 8723DS chipsets ${rtl8723dsver}" "info" diff --git a/patch/kernel/archive/rockchip64-6.16/general-v4l2-rkvdec-00-fixes.disabled b/patch/kernel/archive/rockchip64-6.16/general-v4l2-rkvdec-00-fixes.disabled deleted file mode 100644 index 2ea35eb27dcb..000000000000 --- a/patch/kernel/archive/rockchip64-6.16/general-v4l2-rkvdec-00-fixes.disabled +++ /dev/null @@ -1,157 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Mon, 6 Jul 2020 21:54:37 +0000 -Subject: media: rkvdec: Lock capture pixel format in s_ctrl and s_fmt - -Add an optional valid_fmt operation that should return the valid -pixelformat of CAPTURE buffers. - -This is used in next patch to ensure correct pixelformat is used for 10-bit -and 4:2:2 content. - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 67 ++++++++-- - drivers/staging/media/rkvdec/rkvdec.h | 2 + - 2 files changed, 61 insertions(+), 8 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -38,19 +38,56 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - pix_mp->field = V4L2_FIELD_NONE; - } - -+static u32 rkvdec_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc; -+ -+ if (coded_desc->ops->valid_fmt) -+ return coded_desc->ops->valid_fmt(ctx, ctrl); -+ -+ return ctx->valid_fmt; -+} -+ - static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); - const struct rkvdec_coded_fmt_desc *desc = ctx->coded_fmt_desc; - -- if (desc->ops->try_ctrl) -- return desc->ops->try_ctrl(ctx, ctrl); -+ if (desc->ops->try_ctrl) { -+ int ret; -+ ret = desc->ops->try_ctrl(ctx, ctrl); -+ if (ret) -+ return ret; -+ } -+ -+ if (ctx->valid_fmt && ctx->valid_fmt != rkvdec_valid_fmt(ctx, ctrl)) -+ /* Only current valid format */ -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) -+{ -+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); -+ -+ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { -+ ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); -+ if (ctx->valid_fmt) { -+ struct v4l2_pix_format_mplane *pix_mp; -+ -+ pix_mp = &ctx->decoded_fmt.fmt.pix_mp; -+ pix_mp->pixelformat = ctx->valid_fmt; -+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp); -+ } -+ } - - return 0; - } - - static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { - .try_ctrl = rkvdec_try_ctrl, -+ .s_ctrl = rkvdec_s_ctrl, - }; - - static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { -@@ -201,6 +238,7 @@ static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx) - { - struct v4l2_format *f = &ctx->decoded_fmt; - -+ ctx->valid_fmt = 0; - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); - f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; - f->fmt.pix_mp.width = ctx->coded_fmt.fmt.pix_mp.width; -@@ -256,13 +294,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv, - if (WARN_ON(!coded_desc)) - return -EINVAL; - -- for (i = 0; i < coded_desc->num_decoded_fmts; i++) { -- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) -- break; -- } -+ if (ctx->valid_fmt) { -+ pix_mp->pixelformat = ctx->valid_fmt; -+ } else { -+ for (i = 0; i < coded_desc->num_decoded_fmts; i++) { -+ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) -+ break; -+ } - -- if (i == coded_desc->num_decoded_fmts) -- pix_mp->pixelformat = coded_desc->decoded_fmts[0]; -+ if (i == coded_desc->num_decoded_fmts) -+ pix_mp->pixelformat = coded_desc->decoded_fmts[0]; -+ } - - /* Always apply the frmsize constraint of the coded end. */ - pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width); -@@ -326,6 +368,7 @@ static int rkvdec_s_capture_fmt(struct file *file, void *priv, - return ret; - - ctx->decoded_fmt = *f; -+ ctx->valid_fmt = f->fmt.pix_mp.pixelformat; - return 0; - } - -@@ -429,6 +472,14 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv, - if (WARN_ON(!ctx->coded_fmt_desc)) - return -EINVAL; - -+ if (ctx->valid_fmt) { -+ if (f->index) -+ return -EINVAL; -+ -+ f->pixelformat = ctx->valid_fmt; -+ return 0; -+ } -+ - if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) - return -EINVAL; - -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - struct rkvdec_coded_fmt_ops { - int (*adjust_fmt)(struct rkvdec_ctx *ctx, - struct v4l2_format *f); -+ u32 (*valid_fmt)(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); - int (*start)(struct rkvdec_ctx *ctx); - void (*stop)(struct rkvdec_ctx *ctx); - int (*run)(struct rkvdec_ctx *ctx); -@@ -101,6 +102,7 @@ struct rkvdec_ctx { - struct v4l2_fh fh; - struct v4l2_format coded_fmt; - struct v4l2_format decoded_fmt; -+ u32 valid_fmt; - const struct rkvdec_coded_fmt_desc *coded_fmt_desc; - struct v4l2_ctrl_handler ctrl_hdl; - struct rkvdec_dev *dev; --- -Armbian \ No newline at end of file diff --git a/patch/kernel/archive/rockchip64-6.16/general-v4l2-rkvdec-01-vp9.patch.disabled b/patch/kernel/archive/rockchip64-6.16/general-v4l2-rkvdec-01-vp9.patch.disabled deleted file mode 100644 index ef7526e0ad25..000000000000 --- a/patch/kernel/archive/rockchip64-6.16/general-v4l2-rkvdec-01-vp9.patch.disabled +++ /dev/null @@ -1,495 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 10:16:01 +0000 -Subject: WIP: media: rkvdec: pm runtime dont use autosuspend before disable - and cleanup - -Signed-off-by: Jonas Karlman ---- - drivers/staging/media/rkvdec/rkvdec.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1176,9 +1176,9 @@ static void rkvdec_remove(struct platform_device *pdev) - - cancel_delayed_work_sync(&rkvdec->watchdog_work); - -- rkvdec_v4l2_cleanup(rkvdec); -- pm_runtime_disable(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); -+ pm_runtime_disable(&pdev->dev); -+ rkvdec_v4l2_cleanup(rkvdec); - } - - #ifdef CONFIG_PM --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Randy Li -Date: Sun, 6 Jan 2019 01:48:37 +0800 -Subject: soc: rockchip: power-domain: export idle request - -We need to put the power status of HEVC IP into IDLE unless -we can't reset that IP or the SoC would crash down. -rockchip_pmu_idle_request(dev, true)---> enter idle -rockchip_pmu_idle_request(dev, false)---> exit idle - -Signed-off-by: Caesar Wang -Signed-off-by: Jeffy Chen -Signed-off-by: Randy Li ---- - drivers/pmdomain/rockchip/pm-domains.c | 23 ++++++++++ - include/linux/rockchip_pmu.h | 15 ++++++ - include/soc/rockchip/pm_domains.h | 6 +++ - 3 files changed, 44 insertions(+) - -diff --git a/drivers/pmdomain/rockchip/pm-domains.c b/drivers/pmdomain/rockchip/pm-domains.c -index 111111111111..222222222222 100644 ---- a/drivers/pmdomain/rockchip/pm-domains.c -+++ b/drivers/pmdomain/rockchip/pm-domains.c -@@ -417,6 +417,29 @@ static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, - return 0; - } - -+int rockchip_pmu_idle_request(struct device *dev, bool idle) -+{ -+ struct generic_pm_domain *genpd; -+ struct rockchip_pm_domain *pd; -+ int ret; -+ -+ if (IS_ERR_OR_NULL(dev)) -+ return -EINVAL; -+ -+ if (IS_ERR_OR_NULL(dev->pm_domain)) -+ return -EINVAL; -+ -+ genpd = pd_to_genpd(dev->pm_domain); -+ pd = to_rockchip_pd(genpd); -+ -+ mutex_lock(&pd->pmu->mutex); -+ ret = rockchip_pmu_set_idle_request(pd, idle); -+ mutex_unlock(&pd->pmu->mutex); -+ -+ return ret; -+} -+EXPORT_SYMBOL(rockchip_pmu_idle_request); -+ - static int rockchip_pmu_save_qos(struct rockchip_pm_domain *pd) - { - int i; -diff --git a/include/linux/rockchip_pmu.h b/include/linux/rockchip_pmu.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/include/linux/rockchip_pmu.h -@@ -0,0 +1,15 @@ -+/* -+ * pm_domain.h - Definitions and headers related to device power domains. -+ * -+ * Copyright (C) 2017 Randy Li . -+ * -+ * This file is released under the GPLv2. -+ */ -+ -+#ifndef _LINUX_ROCKCHIP_PM_H -+#define _LINUX_ROCKCHIP_PM_H -+#include -+ -+int rockchip_pmu_idle_request(struct device *dev, bool idle); -+ -+#endif /* _LINUX_ROCKCHIP_PM_H */ -diff --git a/include/soc/rockchip/pm_domains.h b/include/soc/rockchip/pm_domains.h -index 111111111111..222222222222 100644 ---- a/include/soc/rockchip/pm_domains.h -+++ b/include/soc/rockchip/pm_domains.h -@@ -10,6 +10,7 @@ - - int rockchip_pmu_block(void); - void rockchip_pmu_unblock(void); -+int rockchip_pmu_idle_request(struct device *dev, bool idle); - - #else /* CONFIG_ROCKCHIP_PM_DOMAINS */ - -@@ -20,6 +21,11 @@ static inline int rockchip_pmu_block(void) - - static inline void rockchip_pmu_unblock(void) { } - -+static inline int rockchip_pmu_idle_request(struct device *dev, bool idle) -+{ -+ return -ENOTSUPP; -+} -+ - #endif /* CONFIG_ROCKCHIP_PM_DOMAINS */ - - #endif /* __SOC_ROCKCHIP_PM_DOMAINS_H__ */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Wed, 20 May 2020 17:04:47 +0200 -Subject: WIP: media: rkvdec: implement reset controls - ---- - Documentation/devicetree/bindings/media/rockchip,vdec.yaml | 19 ++++ - drivers/staging/media/rkvdec/rkvdec-regs.h | 5 + - drivers/staging/media/rkvdec/rkvdec.c | 53 ++++++++++ - drivers/staging/media/rkvdec/rkvdec.h | 11 +- - 4 files changed, 87 insertions(+), 1 deletion(-) - -diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -53,6 +53,18 @@ properties: - iommus: - maxItems: 1 - -+ resets: -+ maxItems: 6 -+ -+ reset-names: -+ items: -+ - const: video_h -+ - const: video_a -+ - const: video_core -+ - const: video_cabac -+ - const: niu_a -+ - const: niu_h -+ - required: - - compatible - - reg -@@ -60,6 +72,8 @@ required: - - clocks - - clock-names - - power-domains -+ - resets -+ - reset-names - - additionalProperties: false - -@@ -78,6 +92,11 @@ examples: - clock-names = "axi", "ahb", "cabac", "core"; - power-domains = <&power RK3399_PD_VDU>; - iommus = <&vdec_mmu>; -+ resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, -+ <&cru SRST_VDU_CORE>, <&cru SRST_VDU_CA>, -+ <&cru SRST_A_VDU_NOC>, <&cru SRST_H_VDU_NOC>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; - }; - - ... -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-regs.h -+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h -@@ -28,6 +28,11 @@ - #define RKVDEC_SOFTRST_EN_P BIT(20) - #define RKVDEC_FORCE_SOFTRESET_VALID BIT(21) - #define RKVDEC_SOFTRESET_RDY BIT(22) -+#define RKVDEC_ERR_MASK (RKVDEC_BUS_STA \ -+ | RKVDEC_ERR_STA \ -+ | RKVDEC_TIMEOUT_STA \ -+ | RKVDEC_BUF_EMPTY_STA \ -+ | RKVDEC_COLMV_REF_ERR_STA ) - - #define RKVDEC_REG_SYSCTRL 0x008 - #define RKVDEC_IN_ENDIAN BIT(0) -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -10,12 +10,15 @@ - */ - - #include -+#include - #include - #include - #include - #include - #include - #include -+#include -+#include - #include - #include - #include -@@ -766,6 +769,11 @@ static void rkvdec_job_finish(struct rkvdec_ctx *ctx, - - pm_runtime_mark_last_busy(rkvdec->dev); - pm_runtime_put_autosuspend(rkvdec->dev); -+ -+ if (result == VB2_BUF_STATE_ERROR && -+ rkvdec->reset_mask == RESET_NONE) -+ rkvdec->reset_mask |= RESET_SOFT; -+ - rkvdec_job_finish_no_pm(ctx, result); - } - -@@ -803,6 +811,33 @@ static void rkvdec_device_run(void *priv) - - if (WARN_ON(!desc)) - return; -+ if (rkvdec->reset_mask != RESET_NONE) { -+ -+ if (rkvdec->reset_mask & RESET_SOFT) { -+ writel(RKVDEC_SOFTRST_EN_P, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ udelay(RKVDEC_RESET_DELAY); -+ if (readl(rkvdec->regs + RKVDEC_REG_INTERRUPT) -+ & RKVDEC_SOFTRESET_RDY) -+ dev_info_ratelimited(rkvdec->dev, -+ "softreset failed\n"); -+ } -+ -+ if (rkvdec->reset_mask & RESET_HARD) { -+ rockchip_pmu_idle_request(rkvdec->dev, true); -+ ret = reset_control_assert(rkvdec->rstc); -+ if (!ret) { -+ udelay(RKVDEC_RESET_DELAY); -+ ret = reset_control_deassert(rkvdec->rstc); -+ } -+ rockchip_pmu_idle_request(rkvdec->dev, false); -+ if (ret) -+ dev_notice_ratelimited(rkvdec->dev, -+ "hardreset failed\n"); -+ } -+ rkvdec->reset_mask = RESET_NONE; -+ pm_runtime_suspend(rkvdec->dev); -+ } - - ret = pm_runtime_resume_and_get(rkvdec->dev); - if (ret < 0) { -@@ -1069,6 +1104,11 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - if (cancel_delayed_work(&rkvdec->watchdog_work)) { - struct rkvdec_ctx *ctx; - -+ if (state == VB2_BUF_STATE_ERROR) { -+ rkvdec->reset_mask |= (status & RKVDEC_ERR_MASK) ? -+ RESET_HARD : RESET_SOFT; -+ } -+ - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - rkvdec_job_finish(ctx, state); - } -@@ -1086,6 +1126,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) - ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - if (ctx) { - dev_err(rkvdec->dev, "Frame processing timed out!\n"); -+ rkvdec->reset_mask |= RESET_HARD; - writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); - writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); - rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); -@@ -1154,6 +1195,18 @@ static int rkvdec_probe(struct platform_device *pdev) - return ret; - } - -+ -+ rkvdec->rstc = devm_reset_control_array_get_optional_exclusive(&pdev->dev); -+ if (IS_ERR(rkvdec->rstc)) { -+ dev_err(&pdev->dev, -+ "get resets failed %ld\n", PTR_ERR(rkvdec->rstc)); -+ return PTR_ERR(rkvdec->rstc); -+ } else { -+ dev_dbg(&pdev->dev, -+ "requested %d resets\n", -+ reset_control_get_count(&pdev->dev)); -+ } -+ - pm_runtime_set_autosuspend_delay(&pdev->dev, 100); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(&pdev->dev); -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -11,10 +11,11 @@ - #ifndef RKVDEC_H_ - #define RKVDEC_H_ - -+#include - #include -+#include - #include - #include --#include - - #include - #include -@@ -22,6 +23,12 @@ - #include - #include - -+#define RESET_NONE 0 -+#define RESET_SOFT BIT(0) -+#define RESET_HARD BIT(1) -+ -+#define RKVDEC_RESET_DELAY 5 -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -110,6 +117,8 @@ struct rkvdec_dev { - void __iomem *regs; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; -+ struct reset_control *rstc; -+ u8 reset_mask; - }; - - struct rkvdec_ctx { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 21 Aug 2021 16:12:36 +0200 -Subject: media: hantro: rockchip: Increase RK3288's max ACLK - -Required to proper decode H.264@4K - -Signed-off-by: Alex Bee ---- - drivers/media/platform/verisilicon/rockchip_vpu_hw.c | 14 ++++++++-- - 1 file changed, 11 insertions(+), 3 deletions(-) - -diff --git a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/verisilicon/rockchip_vpu_hw.c -+++ b/drivers/media/platform/verisilicon/rockchip_vpu_hw.c -@@ -14,11 +14,13 @@ - #include "hantro_h1_regs.h" - #include "rockchip_vpu2_regs.h" - #include "rockchip_vpu981_regs.h" - - #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000) --#define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000) -+#define RK3288_ACLK_MAX_FREQ (600 * 1000 * 1000) -+#define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000) -+#define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000) - - #define ROCKCHIP_VPU981_MIN_SIZE 64 - - /* - * Supported formats.@ -461,13 +462,20 @@ static int rk3588_vpu981_hw_init(struct hantro_dev *vpu) - return 0; - } - --static int rockchip_vpu_hw_init(struct hantro_dev *vpu) -+static int rk3288_vpu_hw_init(struct hantro_dev *vpu) - { - /* Bump ACLK to max. possible freq. to improve performance. */ - clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ); - return 0; - } - -+static int rockchip_vpu_hw_init(struct hantro_dev *vpu) -+{ -+ /* Bump ACLK to max. possible freq. to improve performance. */ -+ clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ); -+ return 0; -+} -+ - static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx) - { - struct hantro_dev *vpu = ctx->dev; -@@ -723,7 +731,7 @@ const struct hantro_variant rk3288_vpu_variant = { - .codec_ops = rk3288_vpu_codec_ops, - .irqs = rockchip_vpu1_irqs, - .num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs), -- .init = rockchip_vpu_hw_init, -+ .init = rk3288_vpu_hw_init, - .clk_names = rockchip_vpu_clk_names, - .num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names) - }; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 4 Jul 2021 15:19:44 +0200 -Subject: media: rkvdec: disable QoS for VP9 (corruptions on RK3328 otherwise) - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec-regs.h | 2 ++ - drivers/staging/media/rkvdec/rkvdec-vp9.c | 8 ++++++++ - 2 files changed, 10 insertions(+) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-regs.h -+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h -@@ -222,6 +222,8 @@ - #define RKVDEC_REG_H264_ERR_E 0x134 - #define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff) - -+#define RKVDEC_QOS_CTRL 0x18C -+ - #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410 - #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 - -diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/staging/media/rkvdec/rkvdec-vp9.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-vp9.c -+++ b/drivers/staging/media/rkvdec/rkvdec-vp9.c -@@ -803,6 +803,7 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) - struct rkvdec_dev *rkvdec = ctx->dev; - struct rkvdec_vp9_run run = { }; - int ret; -+ u32 reg; - - ret = rkvdec_vp9_run_preamble(ctx, &run); - if (ret) { -@@ -824,6 +825,13 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - - writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ -+ /* disable QOS for RK3328 - no effect on other SoCs */ -+ reg = readl(rkvdec->regs + RKVDEC_QOS_CTRL); -+ reg |= 0xFFFF; -+ reg &= (~BIT(12)); -+ writel(reg, rkvdec->regs + RKVDEC_QOS_CTRL); -+ - /* Start decoding! */ - writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | - RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Thu, 16 Jun 2022 13:18:22 +0200 -Subject: WIP: arm64: dts: add resets to vdec for RK3328 - ---- - arch/arm64/boot/dts/rockchip/rk3328.dtsi | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi -@@ -705,6 +705,11 @@ vdec: video-codec@ff360000 { - assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - assigned-clock-rates = <400000000>, <400000000>, <300000000>; -+ resets = <&cru SRST_VDEC_H>, <&cru SRST_VDEC_A>, -+ <&cru SRST_VDEC_CORE>, <&cru SRST_VDEC_CABAC>, -+ <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>; -+ reset-names = "video_h", "video_a", "video_core", "video_cabac", -+ "niu_a", "niu_h"; - iommus = <&vdec_mmu>; - power-domains = <&power RK3328_PD_VIDEO>; - }; --- -Armbian - diff --git a/patch/kernel/archive/rockchip64-6.16/general-v4l2-rkvdec-02-hevc.disabled b/patch/kernel/archive/rockchip64-6.16/general-v4l2-rkvdec-02-hevc.disabled deleted file mode 100644 index 8bc6fe7af43e..000000000000 --- a/patch/kernel/archive/rockchip64-6.16/general-v4l2-rkvdec-02-hevc.disabled +++ /dev/null @@ -1,3238 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sat, 23 May 2020 15:17:45 +0000 -Subject: WIP: media: rkvdec: add HEVC backend - -NOTE: cabac table and scailing list code is copied 1:1 from mpp -TODO: fix lowdelay flag and rework the scaling list part - -Signed-off-by: Jonas Karlman -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/Makefile | 2 +- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 2572 ++++++++++ - drivers/staging/media/rkvdec/rkvdec-regs.h | 1 + - drivers/staging/media/rkvdec/rkvdec.c | 73 +- - drivers/staging/media/rkvdec/rkvdec.h | 1 + - 5 files changed, 2647 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/Makefile -+++ b/drivers/staging/media/rkvdec/Makefile -@@ -1,3 +1,3 @@ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o - --rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o -+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -0,0 +1,2572 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder HEVC backend -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Jeffy Chen -+ */ -+ -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-regs.h" -+ -+/* Size in u8/u32 units. */ -+#define RKV_CABAC_TABLE_SIZE 27456 -+#define RKV_SCALING_LIST_SIZE 1360 -+#define RKV_PPS_SIZE (80 / 4) -+#define RKV_PPS_LEN 64 -+#define RKV_RPS_SIZE (32 / 4) -+#define RKV_RPS_LEN 600 -+ -+struct rkvdec_sps_pps_packet { -+ u32 info[RKV_PPS_SIZE]; -+}; -+ -+struct rkvdec_rps_packet { -+ u32 info[RKV_RPS_SIZE]; -+}; -+ -+struct rkvdec_ps_field { -+ u16 offset; -+ u8 len; -+}; -+ -+#define PS_FIELD(_offset, _len) \ -+ ((struct rkvdec_ps_field){ _offset, _len }) -+ -+/* SPS */ -+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4) -+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4) -+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2) -+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13) -+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13) -+#define BIT_DEPTH_LUMA PS_FIELD(36, 4) -+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4) -+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5) -+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2) -+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3) -+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3) -+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3) -+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1) -+#define AMP_ENABLED_FLAG PS_FIELD(66, 1) -+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1) -+#define PCM_ENABLED_FLAG PS_FIELD(68, 1) -+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4) -+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4) -+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1) -+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3) -+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3) -+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7) -+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1) -+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6) -+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1) -+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1) -+/* PPS */ -+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6) -+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4) -+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1) -+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1) -+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13) -+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1) -+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1) -+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4) -+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4) -+#define INIT_QP_MINUS26 PS_FIELD(163, 7) -+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1) -+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1) -+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1) -+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3) -+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5) -+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5) -+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1) -+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1) -+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1) -+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1) -+#define TILES_ENABLED_FLAG PS_FIELD(190, 1) -+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1) -+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1) -+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1) -+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1) -+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1) -+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4) -+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4) -+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1) -+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3) -+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1) -+#define NUM_TILE_COLUMNS PS_FIELD(212, 5) -+#define NUM_TILE_ROWS PS_FIELD(217, 5) -+#define COLUMN_WIDTH(i) PS_FIELD(256 + (i * 8), 8) -+#define ROW_HEIGHT(i) PS_FIELD(416 + (i * 8), 8) -+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32) -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_hevc_priv_tbl { -+ u8 cabac_table[RKV_CABAC_TABLE_SIZE]; -+ u8 scaling_list[RKV_SCALING_LIST_SIZE]; -+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; -+ struct rkvdec_rps_packet rps[RKV_RPS_LEN]; -+}; -+ -+struct rkvdec_hevc_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -+ int num_slices; -+}; -+ -+struct rkvdec_hevc_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+}; -+ -+// TODO: refactor scaling list code, was copied 1:1 from mpp -+ -+typedef struct ScalingList { -+ /* This is a little wasteful, since sizeID 0 only needs 8 coeffs, -+ * and size ID 3 only has 2 arrays, not 6. */ -+ u8 sl[4][6][64]; -+ u8 sl_dc[2][6]; -+} scalingList_t; -+ -+typedef struct ScalingFactor_Model { -+ u8 scalingfactor0[1248]; -+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ -+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/ -+ u8 reserverd[4]; /*16Bytes align*/ -+} scalingFactor_t; -+ -+#define SCALING_LIST_SIZE_NUM 4 -+ -+static void -+hal_record_scaling_list(scalingFactor_t *pScalingFactor_out, -+ scalingList_t *pScalingList) -+{ -+ int i; -+ u32 g_scalingListNum_model[SCALING_LIST_SIZE_NUM] = {6, 6, 6, 2}; // from C Model -+ u32 nIndex = 0; -+ u32 sizeId, matrixId, listId; -+ u8 *p = pScalingFactor_out->scalingfactor0; -+ u8 tmpBuf[8 * 8]; -+ -+ //output non-default scalingFactor Table (1248 BYTES) -+ for (sizeId = 0; sizeId < SCALING_LIST_SIZE_NUM; sizeId++) { -+ for (listId = 0; listId < g_scalingListNum_model[sizeId]; listId++) { -+ if (sizeId < 3) { -+ for (i = 0; i < (sizeId == 0 ? 16 : 64); i++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i]; -+ } -+ } else { -+ for (i = 0; i < 64; i ++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = (u8)pScalingList->sl[sizeId][listId][i]; -+ } -+ for (i = 0; i < 128; i ++) { -+ pScalingFactor_out->scalingfactor0[nIndex++] = 0; -+ } -+ } -+ } -+ } -+ //output non-default scalingFactor Table Rotation(96 Bytes) -+ nIndex = 0; -+ for (listId = 0; listId < g_scalingListNum_model[0]; listId++) { -+ u8 temp16[16] = {0}; -+ for (i = 0; i < 16; i ++) { -+ temp16[i] = (u8)pScalingList->sl[0][listId][i]; -+ } -+ for (i = 0; i < 4; i ++) { -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 4]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 8]; -+ pScalingFactor_out->scalingfactor1[nIndex++] = temp16[i + 12]; -+ } -+ } -+ //output non-default ScalingList_DC_Coeff (12 BYTES) -+ nIndex = 0; -+ for (listId = 0; listId < g_scalingListNum_model[2]; listId++) { //sizeId = 2 -+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[0][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC -+ } -+ for (listId = 0; listId < g_scalingListNum_model[3]; listId++) { //sizeId = 3 -+ pScalingFactor_out->scalingdc[nIndex++] = (u8)pScalingList->sl_dc[1][listId];// zrh warning: sl_dc differed from scalingList->getScalingListDC -+ pScalingFactor_out->scalingdc[nIndex++] = 0; -+ pScalingFactor_out->scalingdc[nIndex++] = 0; -+ } -+ -+ //align 16X address -+ nIndex = 0; -+ for (i = 0; i < 4; i ++) { -+ pScalingFactor_out->reserverd[nIndex++] = 0; -+ } -+ -+ //----------------------All above code show the normal store way in HM-------------------------- -+ //--------from now on, the scalingfactor0 is rotated 90', the scalingfactor1 is also rotated 90' -+ -+ //sizeId == 0 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + matrixId * 16; -+ -+ for (i = 0; i < 4; i++) { -+ tmpBuf[4 * 0 + i] = p[i * 4 + 0]; -+ tmpBuf[4 * 1 + i] = p[i * 4 + 1]; -+ tmpBuf[4 * 2 + i] = p[i * 4 + 2]; -+ tmpBuf[4 * 3 + i] = p[i * 4 + 3]; -+ } -+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8)); -+ } -+ //sizeId == 1 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ //sizeId == 2 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ //sizeId == 3 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor0 + 6 * 16 + 6 * 64 + 6 * 64 + matrixId * 64; -+ -+ for (i = 0; i < 8; i++) { -+ tmpBuf[8 * 0 + i] = p[i * 8 + 0]; -+ tmpBuf[8 * 1 + i] = p[i * 8 + 1]; -+ tmpBuf[8 * 2 + i] = p[i * 8 + 2]; -+ tmpBuf[8 * 3 + i] = p[i * 8 + 3]; -+ tmpBuf[8 * 4 + i] = p[i * 8 + 4]; -+ tmpBuf[8 * 5 + i] = p[i * 8 + 5]; -+ tmpBuf[8 * 6 + i] = p[i * 8 + 6]; -+ tmpBuf[8 * 7 + i] = p[i * 8 + 7]; -+ } -+ memcpy(p, tmpBuf, 8 * 8 * sizeof(u8)); -+ } -+ -+ //sizeId == 0 -+ for (matrixId = 0; matrixId < 6; matrixId++) { -+ p = pScalingFactor_out->scalingfactor1 + matrixId * 16; -+ -+ for (i = 0; i < 4; i++) { -+ tmpBuf[4 * 0 + i] = p[i * 4 + 0]; -+ tmpBuf[4 * 1 + i] = p[i * 4 + 1]; -+ tmpBuf[4 * 2 + i] = p[i * 4 + 2]; -+ tmpBuf[4 * 3 + i] = p[i * 4 + 3]; -+ } -+ memcpy(p, tmpBuf, 4 * 4 * sizeof(u8)); -+ } -+} -+ -+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { -+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x68, -+ 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x68, -+ 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, 0x60, 0x50, 0x58, -+ 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, 0x60, 0x60, -+ 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, 0x48, 0x68, -+ 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, -+ 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, -+ 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, -+ 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, -+ 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x0f, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, -+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, -+ 0x57, 0x5e, 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, -+ 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f, -+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, -+ 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, 0x57, 0x57, -+ 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x4f, -+ 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, 0x47, 0x67, 0x40, 0x40, -+ 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, 0x4e, 0x47, 0x47, 0x00, 0x0f, -+ 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64, -+ 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66, -+ 0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56, -+ 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e, -+ 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, -+ 0x45, 0x48, 0x20, 0x57, 0x66, 0x66, 0x56, 0x5e, 0x5e, 0x5d, 0x4e, 0x4e, 0x4e, 0x46, 0x56, 0x57, -+ 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f, -+ 0x47, 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x66, 0x10, 0x47, 0x66, 0x40, 0x40, -+ 0x4f, 0x4d, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x03, 0x27, 0x4d, 0x47, 0x46, 0x01, 0x0f, -+ 0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x34, 0x01, 0x26, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x11, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x07, 0x3e, 0x27, 0x07, 0x40, 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, -+ 0x07, 0x27, 0x40, 0x17, 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, -+ 0x07, 0x27, 0x2f, 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f, -+ 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f, -+ 0x0f, 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, -+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, 0x40, -+ 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, -+ 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, -+ 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f, -+ 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, 0x27, 0x27, 0x08, 0x40, 0x40, -+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+}; -+ -+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) -+{ -+ u8 bit = field.offset % 32, word = field.offset / 32; -+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit); -+ u64 val = ((u64)value << bit) & mask; -+ -+ buf[word] &= ~mask; -+ buf[word] |= val; -+ if (bit + field.len > 32) { -+ buf[word + 1] &= ~(mask >> 32); -+ buf[word + 1] |= val >> 32; -+ } -+} -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps_packet *hw_ps; -+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y; -+ u32 log2_min_cu_qp_delta_size; -+ dma_addr_t scaling_list_address; -+ u32 scaling_distance; -+ int i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 80 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ ctb_log2_size_y = min_cb_log2_size_y + -+ sps->log2_diff_max_min_luma_coding_block_size; -+ ctb_size_y = 1 << ctb_log2_size_y; -+ -+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) -+ /* write sps */ -+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); -+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); -+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4, -+ LOG2_MAX_PIC_ORDER_CNT_LSB); -+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2, -+ LOG2_MIN_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED), -+ SCALING_LIST_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED), -+ AMP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET), -+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG); -+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) { -+ WRITE_PPS(1, PCM_ENABLED_FLAG); -+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_CHROMA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED), -+ PCM_LOOP_FILTER_DISABLED_FLAG); -+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ } -+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT), -+ LONG_TERM_REF_PICS_PRESENT_FLAG); -+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED), -+ SPS_TEMPORAL_MVP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), -+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG); -+ -+ /* write pps */ -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), -+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), -+ OUTPUT_FLAG_PRESENT_FLAG); -+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), -+ SIGN_DATA_HIDING_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), -+ CABAC_INIT_PRESENT_FLAG); -+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, -+ NUM_REF_IDX_L0_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, -+ NUM_REF_IDX_L1_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED), -+ CONSTRAINED_INTRA_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED), -+ TRANSFORM_SKIP_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED), -+ CU_QP_DELTA_ENABLED_FLAG); -+ -+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; -+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE); -+ -+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET); -+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT), -+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED), -+ WEIGHTED_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED), -+ WEIGHTED_BIPRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED), -+ TRANSQUANT_BYPASS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED), -+ TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED), -+ ENTROPY_CODING_SYNC_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED), -+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED), -+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED), -+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER), -+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG); -+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2); -+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT), -+ LISTS_MODIFICATION_PRESENT_FLAG); -+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), -+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); -+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); -+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); -+ -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { -+ for (i = 0; i <= pps->num_tile_columns_minus1; i++) -+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i)); -+ for (i = 0; i <= pps->num_tile_rows_minus1; i++) -+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); -+ } else { -+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ COLUMN_WIDTH(0)); -+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ ROW_HEIGHT(0)); -+ } -+ -+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); -+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; -+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); -+} -+ -+static void assemble_hw_rps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params; -+ const struct v4l2_hevc_dpb_entry *dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_rps_packet *hw_ps; -+ int i, j; -+ unsigned int lowdelay; -+ -+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) -+ -+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD(i * 5, 1) -+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + (i * 5), 4) -+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD((i < 5 ? 75 : 132) + (i * 5), 1) -+#define REF_PIC_IDX_L1(i) PS_FIELD((i < 4 ? 76 : 128) + (i * 5), 4) -+ -+#define LOWDELAY PS_FIELD(182, 1) -+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) -+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) -+#define NUM_RPS_POC PS_FIELD(202, 4) -+ -+ for (j = 0; j < run->num_slices; j++) { -+ sl_params = &run->slices_params[j]; -+ dpb = decode_params->dpb; -+ lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; -+ -+ hw_ps = &priv_tbl->rps[j]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L0(i)); -+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -+ -+ if (dpb[sl_params->ref_idx_l0[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ -+ } -+ -+ for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -+ WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L1(i)); -+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); -+ -+ if (dpb[sl_params->ref_idx_l1[i]].pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ } -+ -+ WRITE_RPS(lowdelay, LOWDELAY); -+ -+ WRITE_RPS(sl_params->long_term_ref_pic_set_size + -+ sl_params->short_term_ref_pic_set_size, -+ LONG_TERM_RPS_BIT_OFFSET); -+ WRITE_RPS(sl_params->short_term_ref_pic_set_size, -+ SHORT_TERM_RPS_BIT_OFFSET); -+ -+ WRITE_RPS(decode_params->num_poc_st_curr_before + -+ decode_params->num_poc_st_curr_after + -+ decode_params->num_poc_lt_curr, -+ NUM_RPS_POC); -+ } -+} -+ -+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -+ u8 *dst; -+ scalingList_t sl; -+ int i, j; -+ -+ if (!memcmp((void*)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) -+ return; -+ -+ memset(&sl, 0, sizeof(scalingList_t)); -+ -+ for (i = 0; i < 6; i++) { -+ for (j = 0; j < 16; j++) -+ sl.sl[0][i][j] = scaling->scaling_list_4x4[i][j]; -+ for (j = 0; j < 64; j++) { -+ sl.sl[1][i][j] = scaling->scaling_list_8x8[i][j]; -+ sl.sl[2][i][j] = scaling->scaling_list_16x16[i][j]; -+ if (i < 2) -+ sl.sl[3][i][j] = scaling->scaling_list_32x32[i][j]; -+ } -+ sl.sl_dc[0][i] = scaling->scaling_list_dc_coef_16x16[i]; -+ if (i < 2) -+ sl.sl_dc[1][i] = scaling->scaling_list_dc_coef_32x32[i]; -+ } -+ -+ dst = tbl->scaling_list; -+ hal_record_scaling_list((scalingFactor_t *)dst, &sl); -+ -+ memcpy((void*)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); -+} -+ -+static struct vb2_buffer * -+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *vb2_buf = NULL; -+ -+ if (dpb_idx < decode_params->num_active_dpb_entries) -+ vb2_buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); -+ -+ /* -+ * If a DPB entry is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ if (!vb2_buf) -+ return &run->base.bufs.dst->vb2_buf; -+ -+ return vb2_buf; -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t refer_addr; -+ u32 rlc_len; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; -+ u32 uv_virstride; -+ u32 yuv_virstride; -+ u32 offset; -+ dma_addr_t dst_addr; -+ u32 reg, i; -+ -+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ uv_virstride = y_virstride / 2; -+ yuv_virstride = y_virstride + uv_virstride; -+ -+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); -+ -+ /* config rlc base address */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -+ -+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ -+ /* config cabac table */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ -+ /* config output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ -+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ -+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ -+ /* config ref pic address */ -+ for (i = 0; i < 15; i++) { -+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); -+ -+ if (i < 4 && decode_params->num_active_dpb_entries) { -+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); -+ reg = (reg >> (i * 4)) & 0xf; -+ } else -+ reg = 0; -+ -+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ writel_relaxed(refer_addr | reg, -+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ -+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? dpb[i].pic_order_cnt_val : 0); -+ writel_relaxed(reg, -+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); -+ } -+ -+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); -+ -+ /* config hw pps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ -+ /* config hw rps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_RPS_BASE); -+ -+ reg = RKVDEC_AXI_DDR_RDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); -+ -+ reg = RKVDEC_AXI_DDR_WDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+} -+ -+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -+ -+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; -+ return 0; -+} -+ -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (sps->bit_depth_luma_minus8 == 2) -+ return V4L2_PIX_FMT_NV15; -+ else -+ return V4L2_PIX_FMT_NV12; -+} -+ -+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_priv_tbl *priv_tbl; -+ struct rkvdec_hevc_ctx *hevc_ctx; -+ struct v4l2_ctrl *ctrl; -+ int ret; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ if (ret) -+ return ret; -+ -+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); -+ if (!hevc_ctx) -+ return -ENOMEM; -+ -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ hevc_ctx->priv_tbl.cpu = priv_tbl; -+ memset(priv_tbl, 0, sizeof(*priv_tbl)); -+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, -+ sizeof(rkvdec_hevc_cabac_table)); -+ -+ ctx->priv = hevc_ctx; -+ return 0; -+ -+err_free_ctx: -+ kfree(hevc_ctx); -+ return ret; -+} -+ -+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, -+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); -+ kfree(hevc_ctx); -+} -+ -+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct v4l2_ctrl *ctrl; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); -+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -+ run->num_slices = ctrl->new_elems; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ run->sps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_PPS); -+ run->pps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); -+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ -+ rkvdec_run_preamble(ctx, &run->base); -+} -+ -+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_run run; -+ -+ rkvdec_hevc_run_preamble(ctx, &run); -+ -+ assemble_hw_scaling_list(ctx, &run); -+ assemble_hw_pps(ctx, &run); -+ assemble_hw_rps(ctx, &run); -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ // sw_cabac_error_e - cabac error enable -+ writel_relaxed(0xfdfffffd, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ // slice end error enable = BIT(28) -+ // frame end error enable = BIT(29) -+ writel_relaxed(0x30000000, rkvdec->regs + RKVDEC_REG_H264_ERR_E); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); -+ -+ /* Start decoding! */ -+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | -+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { -+ .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .start = rkvdec_hevc_start, -+ .stop = rkvdec_hevc_stop, -+ .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .valid_fmt = rkvdec_hevc_valid_fmt, -+}; -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-regs.h -+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h -@@ -48,6 +48,7 @@ - #define RKVDEC_RLC_MODE BIT(11) - #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) - #define RKVDEC_MODE(x) (((x) & 0x03) << 20) -+#define RKVDEC_MODE_HEVC 0 - #define RKVDEC_MODE_H264 1 - #define RKVDEC_MODE_VP9 2 - #define RKVDEC_RPS_MODE BIT(24) -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -74,7 +74,7 @@ static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl) - { - struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl); - -- if (ctrl->id == V4L2_CID_STATELESS_H264_SPS && !ctx->valid_fmt) { -+ if (!ctx->valid_fmt) { - ctx->valid_fmt = rkvdec_valid_fmt(ctx, ctrl); - if (ctx->valid_fmt) { - struct v4l2_pix_format_mplane *pix_mp; -@@ -134,6 +134,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { - }, - }; - -+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, -+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, -+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, -+ .cfg.dims = { 600 }, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, -+ .cfg.ops = &rkvdec_ctrl_ops, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, -+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, -+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, -+ }, -+}; -+ -+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { -+ .ctrls = rkvdec_hevc_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), -+}; -+ -+static const u32 rkvdec_hevc_decoded_fmts[] = { -+ V4L2_PIX_FMT_NV12, -+ V4L2_PIX_FMT_NV15, -+}; -+ -+ - static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .ctrls = rkvdec_h264_ctrl_descs, - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), -@@ -187,6 +243,21 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_hevc_ctrls, -+ .ops = &rkvdec_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, - .frmsize = { -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -133,6 +133,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; - - #endif /* RKVDEC_H_ */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 30 Jan 2021 18:16:39 +0100 -Subject: media: rkvdec: add variants support - -rkvdec IP has different versions which among others differ in -the supported decoding formats. -This adds an variant implementation in order support other -than the currently supported RK3399 version. - -Note: Since matching of supported codecs is index-based the -available codec options have been reordered here: from -supported by all versions to not commonly supported. This seems -the better soultion than duplicatiing code for every newly added IP. - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec.c | 105 +++++++--- - drivers/staging/media/rkvdec/rkvdec.h | 10 + - 2 files changed, 85 insertions(+), 30 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -227,6 +228,22 @@ static const u32 rkvdec_vp9_decoded_fmts[] = { - }; - - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_hevc_ctrls, -+ .ops = &rkvdec_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_HEVC, -+ }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, - .frmsize = { -@@ -242,21 +259,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), - .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -- }, -- { -- .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -- .frmsize = { -- .min_width = 64, -- .max_width = 4096, -- .step_width = 64, -- .min_height = 64, -- .max_height = 2304, -- .step_height = 16, -- }, -- .ctrls = &rkvdec_hevc_ctrls, -- .ops = &rkvdec_hevc_fmt_ops, -- .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -- .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_H264, - }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -272,16 +275,31 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .ops = &rkvdec_vp9_fmt_ops, - .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), - .decoded_fmts = rkvdec_vp9_decoded_fmts, -- } -+ .capability = RKVDEC_CAPABILITY_VP9, -+ }, - }; - - static const struct rkvdec_coded_fmt_desc * --rkvdec_find_coded_fmt_desc(u32 fourcc) -+rkvdec_default_coded_fmt_desc(unsigned int capabilities) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -+ if (rkvdec_coded_fmts[i].capability & capabilities) -+ return &rkvdec_coded_fmts[i]; -+ } -+ -+ return NULL; -+} -+ -+static const struct rkvdec_coded_fmt_desc * -+rkvdec_find_coded_fmt_desc(u32 fourcc, unsigned int capabilities) - { - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- if (rkvdec_coded_fmts[i].fourcc == fourcc) -+ if (rkvdec_coded_fmts[i].fourcc == fourcc && -+ (rkvdec_coded_fmts[i].capability & capabilities)) - return &rkvdec_coded_fmts[i]; - } - -@@ -304,7 +322,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) - { - struct v4l2_format *f = &ctx->coded_fmt; - -- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0]; -+ ctx->coded_fmt_desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); - - f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -@@ -331,11 +349,13 @@ static int rkvdec_enum_framesizes(struct file *file, void *priv, - struct v4l2_frmsizeenum *fsize) - { - const struct rkvdec_coded_fmt_desc *fmt; -+ struct rkvdec_dev *rkvdec = video_drvdata(file); - - if (fsize->index != 0) - return -EINVAL; - -- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format); -+ fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format, -+ rkvdec->capabilities); - if (!fmt) - return -EINVAL; - -@@ -406,10 +426,11 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, - struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); - const struct rkvdec_coded_fmt_desc *desc; - -- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat, -+ ctx->dev->capabilities); - if (!desc) { -- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc; -- desc = &rkvdec_coded_fmts[0]; -+ desc = rkvdec_default_coded_fmt_desc(ctx->dev->capabilities); -+ pix_mp->pixelformat = desc->fourcc; - } - - v4l2_apply_frmsize_constraints(&pix_mp->width, -@@ -487,7 +508,8 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, - if (ret) - return ret; - -- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat, -+ ctx->dev->capabilities); - if (!desc) - return -EINVAL; - ctx->coded_fmt_desc = desc; -@@ -538,7 +560,10 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, - static int rkvdec_enum_output_fmt(struct file *file, void *priv, - struct v4l2_fmtdesc *f) - { -- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts)) -+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); -+ -+ if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts) || -+ !(ctx->dev->capabilities & rkvdec_coded_fmts[f->index].capability)) - return -EINVAL; - - f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; -@@ -947,14 +972,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) - int ret; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) -- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; -+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) -+ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; - - v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -- if (ret) -- goto err_free_handler; -+ if (rkvdec_coded_fmts[i].capability & ctx->dev->capabilities) { -+ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -+ if (ret) -+ goto err_free_handler; -+ } - } - - ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); -@@ -1156,8 +1184,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+static const struct rkvdec_variant rk3399_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_HEVC | -+ RKVDEC_CAPABILITY_VP9 -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { -- { .compatible = "rockchip,rk3399-vdec" }, -+ { -+ .compatible = "rockchip,rk3399-vdec", -+ .data = &rk3399_rkvdec_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1169,6 +1206,7 @@ static const char * const rkvdec_clk_names[] = { - static int rkvdec_probe(struct platform_device *pdev) - { - struct rkvdec_dev *rkvdec; -+ const struct rkvdec_variant *variant; - unsigned int i; - int ret, irq; - -@@ -1194,6 +1232,13 @@ static int rkvdec_probe(struct platform_device *pdev) - if (ret) - return ret; - -+ variant = of_device_get_match_data(rkvdec->dev); -+ if (!variant) -+ return -EINVAL; -+ -+ rkvdec->capabilities = variant->capabilities; -+ -+ - rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(rkvdec->regs)) - return PTR_ERR(rkvdec->regs); -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -29,6 +29,10 @@ - - #define RKVDEC_RESET_DELAY 5 - -+#define RKVDEC_CAPABILITY_H264 BIT(0) -+#define RKVDEC_CAPABILITY_HEVC BIT(1) -+#define RKVDEC_CAPABILITY_VP9 BIT(2) -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -70,6 +74,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - base.vb.vb2_buf); - } - -+struct rkvdec_variant { -+ unsigned int capabilities; -+}; -+ - struct rkvdec_coded_fmt_ops { - int (*adjust_fmt)(struct rkvdec_ctx *ctx, - struct v4l2_format *f); -@@ -91,6 +99,7 @@ struct rkvdec_coded_fmt_desc { - unsigned int num_decoded_fmts; - const u32 *decoded_fmts; - u32 subsystem_flags; -+ unsigned int capability; - }; - - struct rkvdec_dev { -@@ -105,6 +114,7 @@ struct rkvdec_dev { - struct delayed_work watchdog_work; - struct reset_control *rstc; - u8 reset_mask; -+ unsigned int capabilities; - }; - - struct rkvdec_ctx { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 30 Jan 2021 18:21:59 +0100 -Subject: media: rkvdec: add RK3288 variant - -This adds RK3288 variant to rkvdec driver. In this earlier version -of the IP only HEVC decoding is supported. - -Signed-off-by: Alex Bee ---- - drivers/staging/media/rkvdec/rkvdec.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -1190,11 +1190,19 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { - RKVDEC_CAPABILITY_VP9 - }; - -+static const struct rkvdec_variant rk3288_hevc_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { - { - .compatible = "rockchip,rk3399-vdec", - .data = &rk3399_rkvdec_variant, - }, -+ { -+ .compatible = "rockchip,rk3288-hevc", -+ .data = &rk3288_hevc_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sat, 30 Jan 2021 18:27:30 +0100 -Subject: ARM: dts: RK3288: add hevc node - -Signed-off-by: Alex Bee ---- - arch/arm/boot/dts/rockchip/rk3288.dtsi | 21 +++++++++- - 1 file changed, 20 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -1307,6 +1307,25 @@ vpu_mmu: iommu@ff9a0800 { - power-domains = <&power RK3288_PD_VIDEO>; - }; - -+ hevc: hevc@ff9c0000 { -+ compatible = "rockchip,rk3288-hevc"; -+ reg = <0x0 0xff9c0000 0x0 0x400>; -+ interrupts = ; -+ interrupt-names = "irq_dec"; -+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, <&cru SCLK_HEVC_CABAC>, -+ <&cru SCLK_HEVC_CORE>; -+ clock-names = "axi", "ahb", "cabac", "core"; -+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, -+ <&cru SCLK_HEVC_CORE>, -+ <&cru SCLK_HEVC_CABAC>; -+ assigned-clock-rates = <400000000>, <100000000>, -+ <300000000>, <300000000>; -+ iommus = <&hevc_mmu>; -+ power-domains = <&power RK3288_PD_HEVC>; -+ resets = <&cru SRST_HEVC>; -+ reset-names = "video_core"; -+ }; -+ - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; -@@ -1314,7 +1333,7 @@ hevc_mmu: iommu@ff9c0440 { - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -- status = "disabled"; -+ power-domains = <&power RK3288_PD_HEVC>; - }; - - gpu: gpu@ffa30000 { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Dufresne -Date: Tue, 10 May 2022 14:37:29 -0400 -Subject: media: rkvdec: Fix HEVC RPS bit offsets - -The offsets from the uAPI need to be extended to include some bits -that can be calculated from the parameters. This has been compared -to match with the vendor bit sizes (which simply parse again the -data to calcualte it). - -Fixed by this change: -- LTRPSPS_A_Qualcomm_1 -- RPS_C_ericsson_5 -- RPS_D_ericsson_6 -- RPS_E_qualcomm_5 - -Signed-off-by: Nicolas Dufresne ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 26 ++++++++-- - 1 file changed, 23 insertions(+), 3 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -10,6 +10,7 @@ - */ - - #include -+#include - - #include "rkvdec.h" - #include "rkvdec-regs.h" -@@ -2175,6 +2176,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run) - { - const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; - const struct v4l2_ctrl_hevc_slice_params *sl_params; - const struct v4l2_hevc_dpb_entry *dpb; - struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -@@ -2196,9 +2198,21 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - #define NUM_RPS_POC PS_FIELD(202, 4) - - for (j = 0; j < run->num_slices; j++) { -+ uint st_bit_offset = 0; -+ - sl_params = &run->slices_params[j]; - dpb = decode_params->dpb; -- lowdelay = (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_I) ? 0 : 1; -+ -+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { -+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; -+ -+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) -+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; -+ -+ lowdelay = 1; -+ } else { -+ lowdelay = 0; -+ } - - hw_ps = &priv_tbl->rps[j]; - memset(hw_ps, 0, sizeof(*hw_ps)); -@@ -2224,8 +2238,14 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - WRITE_RPS(lowdelay, LOWDELAY); - -- WRITE_RPS(sl_params->long_term_ref_pic_set_size + -- sl_params->short_term_ref_pic_set_size, -+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { -+ if (sl_params->short_term_ref_pic_set_size) -+ st_bit_offset = sl_params->short_term_ref_pic_set_size; -+ else if (sps->num_short_term_ref_pic_sets > 1) -+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); -+ } -+ -+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, - LONG_TERM_RPS_BIT_OFFSET); - WRITE_RPS(sl_params->short_term_ref_pic_set_size, - SHORT_TERM_RPS_BIT_OFFSET); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Dufresne -Date: Tue, 10 May 2022 15:12:03 -0400 -Subject: media: rkvdec: Fix number of HEVC references being set in RPS - -The numbers from the bitstream are values between 1 - 16 (as they are -the number - 1). The difference between 0 and 1 needs to be determined -base on the slice type. I frames have no reference, P frames only have -L0 reference, and B frames have both. - -Signed-off-by: Nicolas Dufresne ---- - drivers/staging/media/rkvdec/rkvdec-hevc.c | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec-hevc.c -+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c -@@ -2199,6 +2199,8 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - for (j = 0; j < run->num_slices; j++) { - uint st_bit_offset = 0; -+ uint num_l0_refs = 0; -+ uint num_l1_refs = 0; - - sl_params = &run->slices_params[j]; - dpb = decode_params->dpb; -@@ -2217,7 +2219,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - hw_ps = &priv_tbl->rps[j]; - memset(hw_ps, 0, sizeof(*hw_ps)); - -- for (i = 0; i <= sl_params->num_ref_idx_l0_active_minus1; i++) { -+ for (i = 0; i < num_l0_refs; i++) { - WRITE_RPS(!!(dpb[sl_params->ref_idx_l0[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L0(i)); - WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -@@ -2227,7 +2229,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - - } - -- for (i = 0; i <= sl_params->num_ref_idx_l1_active_minus1; i++) { -+ for (i = 0; i < num_l1_refs; i++) { - WRITE_RPS(!!(dpb[sl_params->ref_idx_l1[i]].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), - REF_PIC_LONG_TERM_L1(i)); - WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); --- -Armbian - diff --git a/patch/kernel/archive/rockchip64-6.16/media-0000-Unstage-rkvdec.patch b/patch/kernel/archive/rockchip64-6.16/media-0000-Unstage-rkvdec.patch deleted file mode 100644 index 6d1bed6cf468..000000000000 --- a/patch/kernel/archive/rockchip64-6.16/media-0000-Unstage-rkvdec.patch +++ /dev/null @@ -1,268 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Dufresne -Date: Thu, 8 May 2025 17:00:15 -0400 -Subject: media: rkvdec: Restore iommu addresses on errors - -On errors, the rkvdec chip self resets. This can clear the addresses -programmed in the iommu. This case is signaled by the -RKVDEC_SOFTRESET_RDY status bit. - -Since the iommu framework does not have a restore functionality, and -as recommended by the iommu subsystem maintainers, this patch -restores the iommu programming by attaching and detaching an empty -domain, which will clear and restore the default domain. - -Suggested-by: Detlev Casanova -Tested-by: Detlev Casanova -Reviewed-by: Detlev Casanova -Signed-off-by: Nicolas Dufresne -Signed-off-by: Hans Verkuil ---- - drivers/staging/media/rkvdec/rkvdec.c | 43 ++++++++-- - drivers/staging/media/rkvdec/rkvdec.h | 1 + - 2 files changed, 37 insertions(+), 7 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.c -+++ b/drivers/staging/media/rkvdec/rkvdec.c -@@ -11,6 +11,7 @@ - - #include - #include -+#include - #include - #include - #include -@@ -1055,24 +1056,42 @@ static void rkvdec_v4l2_cleanup(struct rkvdec_dev *rkvdec) - v4l2_device_unregister(&rkvdec->v4l2_dev); - } - -+static void rkvdec_iommu_restore(struct rkvdec_dev *rkvdec) -+{ -+ if (rkvdec->empty_domain) { -+ /* -+ * To rewrite mapping into the attached IOMMU core, attach a new empty domain that -+ * will program an empty table, then detach it to restore the default domain and -+ * all cached mappings. -+ * This is safely done in this interrupt handler to make sure no memory get mapped -+ * through the IOMMU while the empty domain is attached. -+ */ -+ iommu_attach_device(rkvdec->empty_domain, rkvdec->dev); -+ iommu_detach_device(rkvdec->empty_domain, rkvdec->dev); -+ } -+} -+ - static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - { - struct rkvdec_dev *rkvdec = priv; -+ struct rkvdec_ctx *ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); - enum vb2_buffer_state state; - u32 status; - - status = readl(rkvdec->regs + RKVDEC_REG_INTERRUPT); -- state = (status & RKVDEC_RDY_STA) ? -- VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; -- - writel(0, rkvdec->regs + RKVDEC_REG_INTERRUPT); -- if (cancel_delayed_work(&rkvdec->watchdog_work)) { -- struct rkvdec_ctx *ctx; - -- ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); -- rkvdec_job_finish(ctx, state); -+ if (status & RKVDEC_RDY_STA) { -+ state = VB2_BUF_STATE_DONE; -+ } else { -+ state = VB2_BUF_STATE_ERROR; -+ if (status & RKVDEC_SOFTRESET_RDY) -+ rkvdec_iommu_restore(rkvdec); - } - -+ if (cancel_delayed_work(&rkvdec->watchdog_work)) -+ rkvdec_job_finish(ctx, state); -+ - return IRQ_HANDLED; - } - -@@ -1140,6 +1159,13 @@ static int rkvdec_probe(struct platform_device *pdev) - return ret; - } - -+ if (iommu_get_domain_for_dev(&pdev->dev)) { -+ rkvdec->empty_domain = iommu_paging_domain_alloc(rkvdec->dev); -+ -+ if (!rkvdec->empty_domain) -+ dev_warn(rkvdec->dev, "cannot alloc new empty domain\n"); -+ } -+ - vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); - - irq = platform_get_irq(pdev, 0); -@@ -1179,6 +1205,9 @@ static void rkvdec_remove(struct platform_device *pdev) - rkvdec_v4l2_cleanup(rkvdec); - pm_runtime_disable(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); -+ -+ if (rkvdec->empty_domain) -+ iommu_domain_free(rkvdec->empty_domain); - } - - #ifdef CONFIG_PM -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/rkvdec/rkvdec.h -+++ b/drivers/staging/media/rkvdec/rkvdec.h -@@ -110,6 +110,7 @@ struct rkvdec_dev { - void __iomem *regs; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; -+ struct iommu_domain *empty_domain; - }; - - struct rkvdec_ctx { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Wed, 18 Jun 2025 13:06:36 -0400 -Subject: media: rkvdec: Remove TODO file - -2 items are present in the TODO file: - - HEVC support - - Evaluate adding helper for rkvdec_request_validate - -Missing HEVC support is not a reason for a driver to be in staging, -support for different features of the hardware can be added in drivers -in the main tree. - -The rkvdec_request_validate function was simplified in -commit 54676d5f5630 ("media: rkvdec: Do not require all controls to be present in every request") -by not setting controls that have not changed. -As it now basically just calls vb2_request_validate(), there is no need -for a helper. - -Signed-off-by: Detlev Casanova ---- - drivers/staging/media/rkvdec/TODO | 11 ---------- - 1 file changed, 11 deletions(-) - -diff --git a/drivers/staging/media/rkvdec/TODO b/drivers/staging/media/rkvdec/TODO -deleted file mode 100644 -index 111111111111..222222222222 ---- a/drivers/staging/media/rkvdec/TODO -+++ /dev/null -@@ -1,11 +0,0 @@ --* Support for HEVC is planned for this driver. -- -- Given the V4L controls for that CODEC will be part of -- the uABI, it will be required to have the driver in staging. -- -- For this reason, we are keeping this driver in staging for now. -- --* Evaluate introducing a helper to consolidate duplicated -- code in rkvdec_request_validate and cedrus_request_validate. -- The helper needs to the driver private data associated with -- the videobuf2 queue, from a media request. --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Wed, 18 Jun 2025 13:17:08 -0400 -Subject: media: rkvdec: Unstage the driver - -The TODO list for unstaging being empty, the driver can now be moved to the -main media folder. - -Also add myself as maintainer. - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/Kconfig | 1 + - drivers/media/platform/rockchip/Makefile | 1 + - drivers/{staging/media => media/platform/rockchip}/rkvdec/Kconfig | 0 - drivers/{staging/media => media/platform/rockchip}/rkvdec/Makefile | 0 - drivers/{staging/media => media/platform/rockchip}/rkvdec/rkvdec-h264.c | 0 - drivers/{staging/media => media/platform/rockchip}/rkvdec/rkvdec-regs.h | 0 - drivers/{staging/media => media/platform/rockchip}/rkvdec/rkvdec-vp9.c | 0 - drivers/{staging/media => media/platform/rockchip}/rkvdec/rkvdec.c | 0 - drivers/{staging/media => media/platform/rockchip}/rkvdec/rkvdec.h | 0 - drivers/staging/media/Kconfig | 2 -- - drivers/staging/media/Makefile | 1 - - 11 files changed, 2 insertions(+), 3 deletions(-) - -diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/Kconfig -+++ b/drivers/media/platform/rockchip/Kconfig -@@ -5,3 +5,4 @@ comment "Rockchip media platform drivers" - source "drivers/media/platform/rockchip/rga/Kconfig" - source "drivers/media/platform/rockchip/rkisp1/Kconfig" - source "drivers/media/platform/rockchip/iep/Kconfig" -+source "drivers/media/platform/rockchip/rkvdec/Kconfig" -diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/Makefile -+++ b/drivers/media/platform/rockchip/Makefile -@@ -2,3 +2,4 @@ - obj-y += rga/ - obj-y += rkisp1/ - obj-y += iep/ -+obj-y += rkvdec/ -diff --git a/drivers/staging/media/rkvdec/Kconfig b/drivers/media/platform/rockchip/rkvdec/Kconfig -similarity index 100% -rename from drivers/staging/media/rkvdec/Kconfig -rename to drivers/media/platform/rockchip/rkvdec/Kconfig -diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile -similarity index 100% -rename from drivers/staging/media/rkvdec/Makefile -rename to drivers/media/platform/rockchip/rkvdec/Makefile -diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -similarity index 100% -rename from drivers/staging/media/rkvdec/rkvdec-h264.c -rename to drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -similarity index 100% -rename from drivers/staging/media/rkvdec/rkvdec-regs.h -rename to drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -diff --git a/drivers/staging/media/rkvdec/rkvdec-vp9.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -similarity index 100% -rename from drivers/staging/media/rkvdec/rkvdec-vp9.c -rename to drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -similarity index 100% -rename from drivers/staging/media/rkvdec/rkvdec.c -rename to drivers/media/platform/rockchip/rkvdec/rkvdec.c -diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -similarity index 100% -rename from drivers/staging/media/rkvdec/rkvdec.h -rename to drivers/media/platform/rockchip/rkvdec/rkvdec.h -diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/Kconfig -+++ b/drivers/staging/media/Kconfig -@@ -32,8 +32,6 @@ source "drivers/staging/media/max96712/Kconfig" - - source "drivers/staging/media/meson/vdec/Kconfig" - --source "drivers/staging/media/rkvdec/Kconfig" -- - source "drivers/staging/media/starfive/Kconfig" - - source "drivers/staging/media/sunxi/Kconfig" -diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/staging/media/Makefile -+++ b/drivers/staging/media/Makefile -@@ -4,7 +4,6 @@ obj-$(CONFIG_INTEL_ATOMISP) += atomisp/ - obj-$(CONFIG_VIDEO_IMX_MEDIA) += imx/ - obj-$(CONFIG_VIDEO_MAX96712) += max96712/ - obj-$(CONFIG_VIDEO_MESON_VDEC) += meson/vdec/ --obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rkvdec/ - obj-$(CONFIG_VIDEO_STARFIVE_CAMSS) += starfive/ - obj-$(CONFIG_VIDEO_SUNXI) += sunxi/ - obj-$(CONFIG_VIDEO_TEGRA) += tegra-video/ --- -Armbian - diff --git a/patch/kernel/archive/rockchip64-6.16/media-0001-Add-rkvdec-Support-v5.patch b/patch/kernel/archive/rockchip64-6.16/media-0001-Add-rkvdec-Support-v5.patch deleted file mode 100644 index 872bf49f5f46..000000000000 --- a/patch/kernel/archive/rockchip64-6.16/media-0001-Add-rkvdec-Support-v5.patch +++ /dev/null @@ -1,13628 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 10 Aug 2025 21:24:31 +0000 -Subject: media: rkvdec: Add HEVC backend - -The Rockchip VDEC supports the HEVC codec with the Main and Main10 -Profile up to Level 5.1 High tier: 4096x2304@60 fps. - -Add the backend for HEVC format to the decoder. - -Signed-off-by: Alex Bee -Signed-off-by: Nicolas Dufresne -Signed-off-by: Sebastian Fricke -Signed-off-by: Jonas Karlman ---- - drivers/media/platform/rockchip/rkvdec/Makefile | 2 +- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c | 1848 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 817 ++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h | 2 + - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 76 + - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 1 + - 6 files changed, 2745 insertions(+), 1 deletion(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/Makefile -+++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -1,3 +1,3 @@ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o - --rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o -+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c -@@ -0,0 +1,1848 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder driver -+ * -+ * Copyright (C) 2023 Collabora, Ltd. -+ * Sebastian Fricke -+ */ -+ -+#include -+ -+#define RKV_CABAC_TABLE_SIZE 27456 -+ -+/* -+ * This file is #include from rkvdec-hevc.c and not compiled. -+ */ -+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { -+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, -+ 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, -+ 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, -+ 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, -+ 0x48, 0x68, 0x60, 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, -+ 0x68, 0x68, 0x50, 0x48, 0x68, 0x48, 0x48, 0x1f, 0x58, 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0x00, 0x00, -+}; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -@@ -0,0 +1,817 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder HEVC backend -+ * -+ * Copyright (C) 2023 Collabora, Ltd. -+ * Sebastian Fricke -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Jeffy Chen -+ */ -+ -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-regs.h" -+#include "rkvdec-hevc-data.c" -+ -+/* Size in u8/u32 units. */ -+#define RKV_SCALING_LIST_SIZE 1360 -+#define RKV_PPS_SIZE (80 / 4) -+#define RKV_PPS_LEN 64 -+#define RKV_RPS_SIZE (32 / 4) -+#define RKV_RPS_LEN 600 -+ -+struct rkvdec_sps_pps_packet { -+ u32 info[RKV_PPS_SIZE]; -+}; -+ -+struct rkvdec_rps_packet { -+ u32 info[RKV_RPS_SIZE]; -+}; -+ -+struct rkvdec_ps_field { -+ u16 offset; -+ u8 len; -+}; -+ -+#define PS_FIELD(_offset, _len) \ -+ ((struct rkvdec_ps_field){ _offset, _len }) -+ -+/* SPS */ -+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4) -+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4) -+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2) -+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13) -+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13) -+#define BIT_DEPTH_LUMA PS_FIELD(36, 4) -+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4) -+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5) -+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2) -+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3) -+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3) -+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3) -+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3) -+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1) -+#define AMP_ENABLED_FLAG PS_FIELD(66, 1) -+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1) -+#define PCM_ENABLED_FLAG PS_FIELD(68, 1) -+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4) -+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4) -+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1) -+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3) -+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3) -+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7) -+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1) -+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6) -+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1) -+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1) -+/* PPS */ -+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6) -+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4) -+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1) -+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1) -+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13) -+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1) -+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1) -+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4) -+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4) -+#define INIT_QP_MINUS26 PS_FIELD(163, 7) -+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1) -+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1) -+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1) -+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3) -+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5) -+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5) -+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1) -+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1) -+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1) -+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1) -+#define TILES_ENABLED_FLAG PS_FIELD(190, 1) -+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1) -+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1) -+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1) -+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1) -+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1) -+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4) -+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4) -+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1) -+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3) -+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1) -+#define NUM_TILE_COLUMNS PS_FIELD(212, 5) -+#define NUM_TILE_ROWS PS_FIELD(217, 5) -+#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8) -+#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8) -+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32) -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_hevc_priv_tbl { -+ u8 cabac_table[RKV_CABAC_TABLE_SIZE]; -+ u8 scaling_list[RKV_SCALING_LIST_SIZE]; -+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; -+ struct rkvdec_rps_packet rps[RKV_RPS_LEN]; -+}; -+ -+struct rkvdec_hevc_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -+ int num_slices; -+}; -+ -+struct rkvdec_hevc_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+}; -+ -+struct scaling_factor { -+ u8 scalingfactor0[1248]; -+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ -+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/ -+ u8 reserved[4]; /*16Bytes align*/ -+}; -+ -+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) -+{ -+ u8 bit = field.offset % 32, word = field.offset / 32; -+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit); -+ u64 val = ((u64)value << bit) & mask; -+ -+ buf[word] &= ~mask; -+ buf[word] |= val; -+ if (bit + field.len > 32) { -+ buf[word + 1] &= ~(mask >> 32); -+ buf[word + 1] |= val >> 32; -+ } -+} -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps_packet *hw_ps; -+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y; -+ u32 log2_min_cu_qp_delta_size, scaling_distance; -+ dma_addr_t scaling_list_address; -+ int i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 80 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) -+ /* write sps */ -+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); -+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); -+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); -+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4, -+ LOG2_MAX_PIC_ORDER_CNT_LSB); -+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2, -+ LOG2_MIN_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size, -+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER); -+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra, -+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED), -+ SCALING_LIST_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED), -+ AMP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET), -+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG); -+ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) { -+ WRITE_PPS(1, PCM_ENABLED_FLAG); -+ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_LUMA); -+ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1, -+ PCM_SAMPLE_BIT_DEPTH_CHROMA); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED), -+ PCM_LOOP_FILTER_DISABLED_FLAG); -+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size, -+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3, -+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE); -+ } -+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT), -+ LONG_TERM_REF_PICS_PRESENT_FLAG); -+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED), -+ SPS_TEMPORAL_MVP_ENABLED_FLAG); -+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), -+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG); -+ -+ /* write pps */ -+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); -+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), -+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), -+ OUTPUT_FLAG_PRESENT_FLAG); -+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), -+ SIGN_DATA_HIDING_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), -+ CABAC_INIT_PRESENT_FLAG); -+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, -+ NUM_REF_IDX_L0_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, -+ NUM_REF_IDX_L1_DEFAULT_ACTIVE); -+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED), -+ CONSTRAINED_INTRA_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED), -+ TRANSFORM_SKIP_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED), -+ CU_QP_DELTA_ENABLED_FLAG); -+ -+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ ctb_log2_size_y = min_cb_log2_size_y + -+ sps->log2_diff_max_min_luma_coding_block_size; -+ ctb_size_y = 1 << ctb_log2_size_y; -+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; -+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE); -+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET); -+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT), -+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED), -+ WEIGHTED_PRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED), -+ WEIGHTED_BIPRED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED), -+ TRANSQUANT_BYPASS_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED), -+ TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED), -+ ENTROPY_CODING_SYNC_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED), -+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED), -+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED), -+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER), -+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG); -+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2); -+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT), -+ LISTS_MODIFICATION_PRESENT_FLAG); -+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); -+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), -+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); -+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); -+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); -+ -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { -+ /* Userspace also provide column width and row height for uniform spacing */ -+ for (i = 0; i <= pps->num_tile_columns_minus1; i++) -+ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i)); -+ for (i = 0; i <= pps->num_tile_rows_minus1; i++) -+ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); -+ } else { -+ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ COLUMN_WIDTH(0)); -+ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, -+ ROW_HEIGHT(0)); -+ } -+ -+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); -+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; -+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); -+} -+ -+/* -+ * Creation of the Reference Picture Set memory blob for the hardware. -+ * The layout looks like this: -+ * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference) -+ * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references -+ * + 4 bits of the 13th reference) -+ * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and -+ * 21 bits for L1 (4 references + first bit of 5) -+ * [3] 32 bits of padding with 0s -+ * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11) -+ * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references) -+ * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32) -+ * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12) -+ * number of references (bit 13 - 16), remaining 16 bits of padding with 0s -+ * [7] 32 bits of padding with 0s -+ * -+ * Thus we have to set up padding in between reference 5 of the L1 list. -+ */ -+static void assemble_hw_rps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params; -+ const struct v4l2_hevc_dpb_entry *dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; -+ struct rkvdec_rps_packet *hw_ps; -+ int i, j; -+ unsigned int lowdelay; -+ -+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) -+ -+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1) -+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4) -+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1) -+#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4) -+ -+#define LOWDELAY PS_FIELD(182, 1) -+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) -+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) -+#define NUM_RPS_POC PS_FIELD(202, 4) -+ -+ for (j = 0; j < run->num_slices; j++) { -+ uint st_bit_offset = 0; -+ uint num_l0_refs = 0; -+ uint num_l1_refs = 0; -+ -+ sl_params = &run->slices_params[j]; -+ dpb = decode_params->dpb; -+ -+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { -+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; -+ -+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) -+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; -+ -+ lowdelay = 1; -+ } else { -+ lowdelay = 0; -+ } -+ -+ hw_ps = &priv_tbl->rps[j]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ for (i = 0; i < num_l0_refs; i++) { -+ const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]]; -+ -+ WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), -+ REF_PIC_LONG_TERM_L0(i)); -+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); -+ -+ if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ } -+ -+ for (i = 0; i < num_l1_refs; i++) { -+ const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]]; -+ int is_long_term = -+ !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE); -+ -+ WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i)); -+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); -+ -+ if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt) -+ lowdelay = 0; -+ } -+ -+ WRITE_RPS(lowdelay, LOWDELAY); -+ -+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { -+ if (sl_params->short_term_ref_pic_set_size) -+ st_bit_offset = sl_params->short_term_ref_pic_set_size; -+ else if (sps->num_short_term_ref_pic_sets > 1) -+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); -+ } -+ -+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, -+ LONG_TERM_RPS_BIT_OFFSET); -+ WRITE_RPS(sl_params->short_term_ref_pic_set_size, -+ SHORT_TERM_RPS_BIT_OFFSET); -+ -+ WRITE_RPS(decode_params->num_poc_st_curr_before + -+ decode_params->num_poc_st_curr_after + -+ decode_params->num_poc_lt_curr, -+ NUM_RPS_POC); -+ } -+} -+ -+/* -+ * Flip one or more matrices along their main diagonal and flatten them -+ * before writing it to the memory. -+ * Convert: -+ * ABCD AEIM -+ * EFGH => BFJN => AEIMBFJNCGKODHLP -+ * IJKL CGKO -+ * MNOP DHLP -+ */ -+static void transpose_and_flatten_matrices(u8 *output, const u8 *input, -+ int matrices, int row_length) -+{ -+ int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value; -+ -+ matrix_size = row_length * row_length; -+ for (i = 0; i < matrices; i++) { -+ row = 0; -+ x_offset = 0; -+ matrix_offset = i * matrix_size; -+ for (j = 0; j < matrix_size; j++) { -+ y_offset = j - (row * row_length); -+ rot_index = y_offset * row_length + x_offset; -+ new_value = *(input + i * matrix_size + j); -+ output[matrix_offset + rot_index] = new_value; -+ if ((j + 1) % row_length == 0) { -+ row += 1; -+ x_offset += 1; -+ } -+ } -+ } -+} -+ -+static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ int offset = 0; -+ -+ transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); -+ offset = 6 * 16 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); -+ offset += 6 * 64 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_16x16, 6, 8); -+ offset += 6 * 64 * sizeof(u8); -+ /* Add a 128 byte padding with 0s between the two 32x32 matrices */ -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_32x32, 1, 8); -+ offset += 64 * sizeof(u8); -+ memset(output + offset, 0, 128); -+ offset += 128 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), -+ 1, 8); -+ offset += 64 * sizeof(u8); -+ memset(output + offset, 0, 128); -+} -+ -+/* -+ * Required layout: -+ * A = scaling_list_dc_coef_16x16 -+ * B = scaling_list_dc_coef_32x32 -+ * 0 = Padding -+ * -+ * A, A, A, A, A, A, B, 0, 0, B, 0, 0 -+ */ -+static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ u8 list_32x32[6] = {0}; -+ -+ memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8)); -+ list_32x32[0] = input->scaling_list_dc_coef_32x32[0]; -+ list_32x32[3] = input->scaling_list_dc_coef_32x32[1]; -+ memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); -+} -+ -+static void translate_scaling_list(struct scaling_factor *output, -+ const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ assemble_scalingfactor0(output->scalingfactor0, input); -+ memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); -+ assemble_scalingdc(output->scalingdc, input); -+ memset(output->reserved, 0, 4 * sizeof(u8)); -+} -+ -+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -+ u8 *dst; -+ -+ if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) -+ return; -+ -+ dst = tbl->scaling_list; -+ translate_scaling_list((struct scaling_factor *)dst, scaling); -+ -+ memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); -+} -+ -+static struct vb2_buffer * -+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *buf = NULL; -+ -+ if (dpb_idx < decode_params->num_active_dpb_entries) -+ buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); -+ -+ /* -+ * If a DPB entry is unused or invalid, the address of current destination -+ * buffer is returned. -+ */ -+ if (!buf) -+ return &run->base.bufs.dst->vb2_buf; -+ -+ return buf; -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t refer_addr; -+ u32 rlc_len; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; -+ u32 yuv_virstride = 0; -+ u32 offset; -+ dma_addr_t dst_addr; -+ u32 reg, i; -+ -+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ -+ if (sps->chroma_format_idc == 0) -+ yuv_virstride = y_virstride; -+ else if (sps->chroma_format_idc == 1) -+ yuv_virstride = y_virstride + y_virstride / 2; -+ else if (sps->chroma_format_idc == 2) -+ yuv_virstride = 2 * y_virstride; -+ -+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | -+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); -+ -+ /* config rlc base address */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -+ -+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ -+ /* config cabac table */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ -+ /* config output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ -+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ -+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ -+ /* config ref pic address */ -+ for (i = 0; i < 15; i++) { -+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); -+ -+ if (i < 4 && decode_params->num_active_dpb_entries) { -+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); -+ reg = (reg >> (i * 4)) & 0xf; -+ } else { -+ reg = 0; -+ } -+ -+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ writel_relaxed(refer_addr | reg, -+ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ -+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? -+ dpb[i].pic_order_cnt_val : 0); -+ writel_relaxed(reg, -+ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); -+ } -+ -+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); -+ -+ /* config hw pps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ -+ /* config hw rps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -+ writel_relaxed(priv_start_addr + offset, -+ rkvdec->regs + RKVDEC_REG_RPS_BASE); -+ -+ reg = RKVDEC_AXI_DDR_RDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); -+ -+ reg = RKVDEC_AXI_DDR_WDATA(0); -+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+} -+ -+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -+ -+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; -+ return 0; -+} -+ -+static enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS) -+ return RKVDEC_IMG_FMT_ANY; -+ -+ if (sps->bit_depth_luma_minus8 == 0) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_8BIT; -+ else -+ return RKVDEC_IMG_FMT_420_8BIT; -+ } else if (sps->bit_depth_luma_minus8 == 2) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_10BIT; -+ else -+ return RKVDEC_IMG_FMT_420_10BIT; -+ } -+ -+ return RKVDEC_IMG_FMT_ANY; -+} -+ -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_priv_tbl *priv_tbl; -+ struct rkvdec_hevc_ctx *hevc_ctx; -+ -+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); -+ if (!hevc_ctx) -+ return -ENOMEM; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ kfree(hevc_ctx); -+ return -ENOMEM; -+ } -+ -+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ hevc_ctx->priv_tbl.cpu = priv_tbl; -+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, -+ sizeof(rkvdec_hevc_cabac_table)); -+ -+ ctx->priv = hevc_ctx; -+ return 0; -+} -+ -+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, -+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); -+ kfree(hevc_ctx); -+} -+ -+static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct v4l2_ctrl *ctrl; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); -+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -+ run->num_slices = ctrl ? ctrl->new_elems : 0; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ run->sps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_PPS); -+ run->pps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); -+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ -+ rkvdec_run_preamble(ctx, &run->base); -+} -+ -+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_run run; -+ u32 reg; -+ -+ rkvdec_hevc_run_preamble(ctx, &run); -+ -+ assemble_hw_scaling_list(ctx, &run); -+ assemble_hw_pps(ctx, &run); -+ assemble_hw_rps(ctx, &run); -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); -+ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); -+ -+ /* Start decoding! */ -+ reg = (run.pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ? -+ 0 : RKVDEC_WR_DDR_ALIGN_EN; -+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | -+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E | reg, -+ rkvdec->regs + RKVDEC_REG_INTERRUPT); -+ -+ return 0; -+} -+ -+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { -+ .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .start = rkvdec_hevc_start, -+ .stop = rkvdec_hevc_stop, -+ .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .get_image_fmt = rkvdec_hevc_get_image_fmt, -+}; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -@@ -28,6 +28,7 @@ - #define RKVDEC_SOFTRST_EN_P BIT(20) - #define RKVDEC_FORCE_SOFTRESET_VALID BIT(21) - #define RKVDEC_SOFTRESET_RDY BIT(22) -+#define RKVDEC_WR_DDR_ALIGN_EN BIT(23) - - #define RKVDEC_REG_SYSCTRL 0x008 - #define RKVDEC_IN_ENDIAN BIT(0) -@@ -43,6 +44,7 @@ - #define RKVDEC_RLC_MODE BIT(11) - #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) - #define RKVDEC_MODE(x) (((x) & 0x03) << 20) -+#define RKVDEC_MODE_HEVC 0 - #define RKVDEC_MODE_H264 1 - #define RKVDEC_MODE_VP9 2 - #define RKVDEC_RPS_MODE BIT(24) -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -158,6 +158,67 @@ static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { - .s_ctrl = rkvdec_s_ctrl, - }; - -+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, -+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, -+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, -+ .cfg.dims = { 600 }, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, -+ .cfg.ops = &rkvdec_ctrl_ops, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, -+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, -+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, -+ }, -+}; -+ -+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { -+ .ctrls = rkvdec_hevc_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), -+}; -+ -+static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV15, -+ .image_fmt = RKVDEC_IMG_FMT_420_10BIT, -+ }, -+}; -+ - static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { - { - .cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, -@@ -252,6 +313,21 @@ static const struct rkvdec_decoded_fmt_desc rkvdec_vp9_decoded_fmts[] = { - }; - - static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 4096, -+ .step_width = 64, -+ .min_height = 64, -+ .max_height = 2304, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_hevc_ctrls, -+ .ops = &rkvdec_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, - .frmsize = { -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -139,6 +139,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; - - #endif /* RKVDEC_H_ */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 10 Aug 2025 21:24:32 +0000 -Subject: media: rkvdec: Add variants support - -Different versions of the Rockchip VDEC IP exists and one way they can -differ is what decoding formats are supported. - -Add a variant implementation in order to support flagging different -capabilities. - -Signed-off-by: Alex Bee -Signed-off-by: Jonas Karlman -Reviewed-by: Nicolas Dufresne ---- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 21 +++++++++- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 10 +++++ - 2 files changed, 30 insertions(+), 1 deletion(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -14,6 +14,7 @@ - #include - #include - #include -+#include - #include - #include - #include -@@ -327,6 +328,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .ops = &rkvdec_hevc_fmt_ops, - .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), - .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_HEVC, - }, - { - .fourcc = V4L2_PIX_FMT_H264_SLICE, -@@ -343,6 +345,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), - .decoded_fmts = rkvdec_h264_decoded_fmts, - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ .capability = RKVDEC_CAPABILITY_H264, - }, - { - .fourcc = V4L2_PIX_FMT_VP9_FRAME, -@@ -358,6 +361,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - .ops = &rkvdec_vp9_fmt_ops, - .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), - .decoded_fmts = rkvdec_vp9_decoded_fmts, -+ .capability = RKVDEC_CAPABILITY_VP9, - } - }; - -@@ -1187,8 +1191,17 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+static const struct rkvdec_variant rk3399_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC | -+ RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_VP9, -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { -- { .compatible = "rockchip,rk3399-vdec" }, -+ { -+ .compatible = "rockchip,rk3399-vdec", -+ .data = &rk3399_rkvdec_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1199,16 +1212,22 @@ static const char * const rkvdec_clk_names[] = { - - static int rkvdec_probe(struct platform_device *pdev) - { -+ const struct rkvdec_variant *variant; - struct rkvdec_dev *rkvdec; - unsigned int i; - int ret, irq; - -+ variant = of_device_get_match_data(&pdev->dev); -+ if (!variant) -+ return -EINVAL; -+ - rkvdec = devm_kzalloc(&pdev->dev, sizeof(*rkvdec), GFP_KERNEL); - if (!rkvdec) - return -ENOMEM; - - platform_set_drvdata(pdev, rkvdec); - rkvdec->dev = &pdev->dev; -+ rkvdec->capabilities = variant->capabilities; - mutex_init(&rkvdec->vdev_lock); - INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -22,6 +22,10 @@ - #include - #include - -+#define RKVDEC_CAPABILITY_HEVC BIT(0) -+#define RKVDEC_CAPABILITY_H264 BIT(1) -+#define RKVDEC_CAPABILITY_VP9 BIT(2) -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -63,6 +67,10 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - base.vb.vb2_buf); - } - -+struct rkvdec_variant { -+ unsigned int capabilities; -+}; -+ - struct rkvdec_coded_fmt_ops { - int (*adjust_fmt)(struct rkvdec_ctx *ctx, - struct v4l2_format *f); -@@ -98,6 +106,7 @@ struct rkvdec_coded_fmt_desc { - unsigned int num_decoded_fmts; - const struct rkvdec_decoded_fmt_desc *decoded_fmts; - u32 subsystem_flags; -+ unsigned int capability; - }; - - struct rkvdec_dev { -@@ -111,6 +120,7 @@ struct rkvdec_dev { - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; - struct iommu_domain *empty_domain; -+ unsigned int capabilities; - }; - - struct rkvdec_ctx { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 10 Aug 2025 21:24:33 +0000 -Subject: media: rkvdec: Implement capability filtering - -Add filtering of coded formats and controls depending on a variant -capabilities. - -Signed-off-by: Alex Bee -Signed-off-by: Jonas Karlman -Reviewed-by: Nicolas Dufresne ---- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 67 +++++++--- - 1 file changed, 49 insertions(+), 18 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -365,13 +365,36 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - } - }; - -+static bool rkvdec_is_capable(struct rkvdec_ctx *ctx, unsigned int capability) -+{ -+ return (ctx->dev->capabilities & capability) == capability; -+} -+ - static const struct rkvdec_coded_fmt_desc * --rkvdec_find_coded_fmt_desc(u32 fourcc) -+rkvdec_enum_coded_fmt_desc(struct rkvdec_ctx *ctx, int index) - { -+ int fmt_idx = -1; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- if (rkvdec_coded_fmts[i].fourcc == fourcc) -+ if (!rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) -+ continue; -+ fmt_idx++; -+ if (index == fmt_idx) -+ return &rkvdec_coded_fmts[i]; -+ } -+ -+ return NULL; -+} -+ -+static const struct rkvdec_coded_fmt_desc * -+rkvdec_find_coded_fmt_desc(struct rkvdec_ctx *ctx, u32 fourcc) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -+ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability) && -+ rkvdec_coded_fmts[i].fourcc == fourcc) - return &rkvdec_coded_fmts[i]; - } - -@@ -382,7 +405,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) - { - struct v4l2_format *f = &ctx->coded_fmt; - -- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0]; -+ ctx->coded_fmt_desc = rkvdec_enum_coded_fmt_desc(ctx, 0); - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); - - f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; -@@ -396,21 +419,22 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) - static int rkvdec_enum_framesizes(struct file *file, void *priv, - struct v4l2_frmsizeenum *fsize) - { -- const struct rkvdec_coded_fmt_desc *fmt; -+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); -+ const struct rkvdec_coded_fmt_desc *desc; - - if (fsize->index != 0) - return -EINVAL; - -- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format); -- if (!fmt) -+ desc = rkvdec_find_coded_fmt_desc(ctx, fsize->pixel_format); -+ if (!desc) - return -EINVAL; - - fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; - fsize->stepwise.min_width = 1; -- fsize->stepwise.max_width = fmt->frmsize.max_width; -+ fsize->stepwise.max_width = desc->frmsize.max_width; - fsize->stepwise.step_width = 1; - fsize->stepwise.min_height = 1; -- fsize->stepwise.max_height = fmt->frmsize.max_height; -+ fsize->stepwise.max_height = desc->frmsize.max_height; - fsize->stepwise.step_height = 1; - - return 0; -@@ -470,10 +494,10 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, - struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); - const struct rkvdec_coded_fmt_desc *desc; - -- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(ctx, pix_mp->pixelformat); - if (!desc) { -- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc; -- desc = &rkvdec_coded_fmts[0]; -+ desc = rkvdec_enum_coded_fmt_desc(ctx, 0); -+ pix_mp->pixelformat = desc->fourcc; - } - - v4l2_apply_frmsize_constraints(&pix_mp->width, -@@ -550,7 +574,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, - if (ret) - return ret; - -- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); -+ desc = rkvdec_find_coded_fmt_desc(ctx, f->fmt.pix_mp.pixelformat); - if (!desc) - return -EINVAL; - ctx->coded_fmt_desc = desc; -@@ -602,10 +626,14 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, - static int rkvdec_enum_output_fmt(struct file *file, void *priv, - struct v4l2_fmtdesc *f) - { -- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts)) -+ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); -+ const struct rkvdec_coded_fmt_desc *desc; -+ -+ desc = rkvdec_enum_coded_fmt_desc(ctx, f->index); -+ if (!desc) - return -EINVAL; - -- f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; -+ f->pixelformat = desc->fourcc; - return 0; - } - -@@ -970,14 +998,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) - int ret; - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) -- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; -+ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) -+ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; - - v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); - - for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -- if (ret) -- goto err_free_handler; -+ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) { -+ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -+ if (ret) -+ goto err_free_handler; -+ } - } - - ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 10 Aug 2025 21:24:34 +0000 -Subject: media: rkvdec: Add RK3288 variant - -Add a RK3288 variant, a version of the Rockchip VDEC IP that only -support HEVC decoding. - -Signed-off-by: Alex Bee -Signed-off-by: Jonas Karlman -Reviewed-by: Nicolas Dufresne ---- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -1222,6 +1222,10 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+static const struct rkvdec_variant rk3288_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC, -+}; -+ - static const struct rkvdec_variant rk3399_rkvdec_variant = { - .capabilities = RKVDEC_CAPABILITY_HEVC | - RKVDEC_CAPABILITY_H264 | -@@ -1229,6 +1233,10 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { - }; - - static const struct of_device_id of_rkvdec_match[] = { -+ { -+ .compatible = "rockchip,rk3288-vdec", -+ .data = &rk3288_rkvdec_variant, -+ }, - { - .compatible = "rockchip,rk3399-vdec", - .data = &rk3399_rkvdec_variant, --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 10 Aug 2025 21:24:35 +0000 -Subject: media: rkvdec: Disable QoS for HEVC and VP9 on RK3328 - -The RK3328 VDEC has a HW quirk that require QoS to be disabled when HEVC -or VP9 is decoded, otherwise the decoded picture may become corrupted. - -Add a RK3328 variant with a quirk flag to disable QoS when before -decoding is started. - -Signed-off-by: Alex Bee -Signed-off-by: Jonas Karlman ---- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 9 +++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h | 2 ++ - drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c | 10 ++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 12 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 4 ++++ - 5 files changed, 37 insertions(+) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -@@ -789,6 +789,15 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - -+ if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) { -+ u32 reg; -+ -+ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ reg |= 0xFFFF; -+ reg &= ~BIT(12); -+ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ } -+ - /* Start decoding! */ - reg = (run.pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ? - 0 : RKVDEC_WR_DDR_ALIGN_EN; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -@@ -219,6 +219,8 @@ - #define RKVDEC_REG_H264_ERR_E 0x134 - #define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff) - -+#define RKVDEC_REG_QOS_CTRL 0x18C -+ - #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410 - #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -@@ -824,6 +824,16 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - - writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -+ -+ if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) { -+ u32 reg; -+ -+ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ reg |= 0xFFFF; -+ reg &= ~BIT(12); -+ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL); -+ } -+ - /* Start decoding! */ - writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | - RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -1226,6 +1226,13 @@ static const struct rkvdec_variant rk3288_rkvdec_variant = { - .capabilities = RKVDEC_CAPABILITY_HEVC, - }; - -+static const struct rkvdec_variant rk3328_rkvdec_variant = { -+ .capabilities = RKVDEC_CAPABILITY_HEVC | -+ RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_VP9, -+ .quirks = RKVDEC_QUIRK_DISABLE_QOS, -+}; -+ - static const struct rkvdec_variant rk3399_rkvdec_variant = { - .capabilities = RKVDEC_CAPABILITY_HEVC | - RKVDEC_CAPABILITY_H264 | -@@ -1237,6 +1244,10 @@ static const struct of_device_id of_rkvdec_match[] = { - .compatible = "rockchip,rk3288-vdec", - .data = &rk3288_rkvdec_variant, - }, -+ { -+ .compatible = "rockchip,rk3328-vdec", -+ .data = &rk3328_rkvdec_variant, -+ }, - { - .compatible = "rockchip,rk3399-vdec", - .data = &rk3399_rkvdec_variant, -@@ -1267,6 +1278,7 @@ static int rkvdec_probe(struct platform_device *pdev) - platform_set_drvdata(pdev, rkvdec); - rkvdec->dev = &pdev->dev; - rkvdec->capabilities = variant->capabilities; -+ rkvdec->quirks = variant->quirks; - mutex_init(&rkvdec->vdev_lock); - INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -26,6 +26,8 @@ - #define RKVDEC_CAPABILITY_H264 BIT(1) - #define RKVDEC_CAPABILITY_VP9 BIT(2) - -+#define RKVDEC_QUIRK_DISABLE_QOS BIT(0) -+ - struct rkvdec_ctx; - - struct rkvdec_ctrl_desc { -@@ -69,6 +71,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - - struct rkvdec_variant { - unsigned int capabilities; -+ unsigned int quirks; - }; - - struct rkvdec_coded_fmt_ops { -@@ -121,6 +124,7 @@ struct rkvdec_dev { - struct delayed_work watchdog_work; - struct iommu_domain *empty_domain; - unsigned int capabilities; -+ unsigned int quirks; - }; - - struct rkvdec_ctx { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jonas Karlman -Date: Sun, 10 Aug 2025 21:24:36 +0000 -Subject: media: dt-bindings: rockchip,vdec: Add RK3288 compatible - -Add a RK3288 compatible for a version of the Rockchip VDEC IP that only -support HEVC decoding. - -Signed-off-by: Jonas Karlman -Acked-by: Conor Dooley ---- - Documentation/devicetree/bindings/media/rockchip,vdec.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -index 111111111111..222222222222 100644 ---- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -+++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml -@@ -16,6 +16,7 @@ description: |- - properties: - compatible: - oneOf: -+ - const: rockchip,rk3288-vdec - - const: rockchip,rk3399-vdec - - items: - - enum: --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Alex Bee -Date: Sun, 10 Aug 2025 21:24:37 +0000 -Subject: ARM: dts: rockchip: Add vdec node for RK3288 - -RK3288 contains a Rockchip VDEC block that only support HEVC -decoding. Add a vdec node for this. - -Signed-off-by: Alex Bee -Signed-off-by: Jonas Karlman ---- - arch/arm/boot/dts/rockchip/rk3288.dtsi | 17 +++++++++- - 1 file changed, 16 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/rockchip/rk3288.dtsi b/arch/arm/boot/dts/rockchip/rk3288.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm/boot/dts/rockchip/rk3288.dtsi -+++ b/arch/arm/boot/dts/rockchip/rk3288.dtsi -@@ -1304,6 +1304,21 @@ vpu_mmu: iommu@ff9a0800 { - power-domains = <&power RK3288_PD_VIDEO>; - }; - -+ hevc: video-codec@ff9c0000 { -+ compatible = "rockchip,rk3288-vdec"; -+ reg = <0x0 0xff9c0000 0x0 0x440>; -+ interrupts = ; -+ clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, -+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; -+ clock-names = "axi", "ahb", "cabac", "core"; -+ assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>, -+ <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>; -+ assigned-clock-rates = <400000000>, <100000000>, -+ <300000000>, <300000000>; -+ iommus = <&hevc_mmu>; -+ power-domains = <&power RK3288_PD_HEVC>; -+ }; -+ - hevc_mmu: iommu@ff9c0440 { - compatible = "rockchip,iommu"; - reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>; -@@ -1311,7 +1326,7 @@ hevc_mmu: iommu@ff9c0440 { - clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>; - clock-names = "aclk", "iface"; - #iommu-cells = <0>; -- status = "disabled"; -+ power-domains = <&power RK3288_PD_HEVC>; - }; - - gpu: gpu@ffa30000 { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Thu, 24 Jul 2025 14:10:18 -0400 -Subject: media: uapi: HEVC: Add v4l2_ctrl_hevc_ext_sps_[ls]t_rps controls - -Some hardware (e.g.: Rockchip's rk3588 hevc decoder) need the -long and short term reference information for HEVC decoding. - -Add controls to provide it as the raw data form the stream. - -Signed-off-by: Detlev Casanova ---- - Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst | 114 ++++++++++ - Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst | 12 + - Documentation/userspace-api/media/videodev2.h.rst.exceptions | 2 + - 3 files changed, 128 insertions(+) - -diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -index 111111111111..222222222222 100644 ---- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst -@@ -2958,6 +2958,120 @@ This structure contains all loop filter related parameters. See sections - - 0x00000004 - - - -+``V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS (struct)`` -+ Specifies the list of Long-Term reference sets parameters from the SPS. -+ These parameters are defined according to :ref:`hevc`. -+ They are described in section 7.4.3.2.1 "General sequence parameter set -+ RBSP semantics" of the specification. -+ This control is a dynamically sized 1-dimensional array, -+ V4L2_CTRL_FLAG_DYNAMIC_ARRAY flag must be set when using it. -+ -+.. c:type:: v4l2_ctrl_hevc_ext_sps_lt_rps -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_hevc_ext_sps_lt_rps -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u16 -+ - ``lt_ref_pic_poc_lsb_sps`` -+ - Long term reference picture order count as described in section 7.4.3.2.1 -+ "General sequence parameter set RBSP semantics" of the specification. -+ * - __u8 -+ - ``flags`` -+ - See :ref:`Extended Long-Term RPS Flags ` -+ -+.. _hevc_ext_sps_lt_rps_flags: -+ -+``Extended SPS Long-Term RPS Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT`` -+ - 0x00000001 -+ - Specifies if the long-term reference picture is used 7.4.3.2.1 "General sequence parameter -+ set RBSP semantics" of the specification. -+ -+``V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS (struct)`` -+ Specifies the list of Short-Term reference sets parameters from the SPS. -+ These parameters are defined according to :ref:`hevc`. -+ They are described in section 7.4.8 "Short-term reference picture set -+ semantics" of the specification. -+ This control is a dynamically sized 1-dimensional array, -+ V4L2_CTRL_FLAG_DYNAMIC_ARRAY flag must be set when using it. -+ -+.. c:type:: v4l2_ctrl_hevc_ext_sps_st_rps -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_hevc_ext_sps_st_rps -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``delta_idx_minus1`` -+ - Specifies the delta compare to the index. See details in section 7.4.8 "Short-term -+ reference picture set semantics" of the specification. -+ * - __u8 -+ - ``delta_rps_sign`` -+ - Sign of the delta as specified in section 7.4.8 "Short-term reference picture set -+ semantics" of the specification. -+ * - __u16 -+ - ``abs_delta_rps_minus1`` -+ - Absolute delta RPS as specified in section 7.4.8 "Short-term reference picture set -+ semantics" of the specification. -+ * - __u8 -+ - ``num_negative_pics`` -+ - Number of short-term RPS entries that have picture order count values less than the -+ picture order count value of the current picture. -+ * - __u8 -+ - ``num_positive_pics`` -+ - Number of short-term RPS entries that have picture order count values greater than the -+ picture order count value of the current picture. -+ * - __u32 -+ - ``used_by_curr_pic`` -+ - Bit i specifies if short-term RPS i is used by the current picture. -+ * - __u32 -+ - ``use_delta_flag`` -+ - Bit i specifies if short-term RPS i is included in the short-term RPS entries. -+ * - __u16 -+ - ``delta_poc_s0_minus1[16]`` -+ - Specifies the negative picture order count delta for the i-th entry in the short-term RPS. -+ See details in section 7.4.8 "Short-term reference picture set semantics" of the -+ specification. -+ * - __u16 -+ - ``delta_poc_s1_minus1[16]`` -+ - Specifies the positive picture order count delta for the i-th entry in the short-term RPS. -+ See details in section 7.4.8 "Short-term reference picture set semantics" of the -+ specification. -+ * - __u8 -+ - ``flags`` -+ - See :ref:`Extended Short-Term RPS Flags ` -+ -+.. _hevc_ext_sps_st_rps_flags: -+ -+``Extended SPS Short-Term RPS Flags`` -+ -+.. cssclass:: longtable -+ -+.. flat-table:: -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - ``V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED`` -+ - 0x00000001 -+ - Specifies if the short-term RPS is predicted from another short term RPS. See details in -+ section 7.4.8 "Short-term reference picture set semantics" of the specification. -+ - .. _v4l2-codec-stateless-av1: - - ``V4L2_CID_STATELESS_AV1_SEQUENCE (struct)`` -diff --git a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -index 111111111111..222222222222 100644 ---- a/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -+++ b/Documentation/userspace-api/media/v4l/vidioc-queryctrl.rst -@@ -523,6 +523,18 @@ See also the examples in :ref:`control`. - - n/a - - A struct :c:type:`v4l2_ctrl_hevc_decode_params`, containing HEVC - decoding parameters for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_hevc_ext_sps_lt_rps`, containing HEVC -+ extended Long-Term RPS for stateless video decoders. -+ * - ``V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS`` -+ - n/a -+ - n/a -+ - n/a -+ - A struct :c:type:`v4l2_ctrl_hevc_ext_sps_st_rps`, containing HEVC -+ extended Short-Term RPS for stateless video decoders. - * - ``V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR`` - - n/a - - n/a -diff --git a/Documentation/userspace-api/media/videodev2.h.rst.exceptions b/Documentation/userspace-api/media/videodev2.h.rst.exceptions -index 111111111111..222222222222 100644 ---- a/Documentation/userspace-api/media/videodev2.h.rst.exceptions -+++ b/Documentation/userspace-api/media/videodev2.h.rst.exceptions -@@ -149,6 +149,8 @@ replace symbol V4L2_CTRL_TYPE_H264_DECODE_PARAMS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HEVC_SPS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HEVC_PPS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS :c:type:`v4l2_ctrl_type` -+replace symbol V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_AREA :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_RECT :c:type:`v4l2_ctrl_type` - replace symbol V4L2_CTRL_TYPE_FWHT_PARAMS :c:type:`v4l2_ctrl_type` --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Thu, 24 Jul 2025 14:10:19 -0400 -Subject: media: v4l2-ctrls: Add hevc_ext_sps_[ls]t_rps controls - -The vdpu381 decoder found on newer Rockchip SoC need the information -from the long term and short term ref pic sets from the SPS. - -So far, it wasn't included in the v4l2 API, so add it with new dynamic -sized controls. - -Each element of the hevc_ext_sps_lt_rps array contains the long term ref -pic set at that index. -Each element of the hevc_ext_sps_st_rps contains the short term ref pic -set at that index, as the raw data. -It is the role of the drivers to calculate the reference sets values. - -Signed-off-by: Detlev Casanova ---- - drivers/media/v4l2-core/v4l2-ctrls-core.c | 18 +++ - drivers/media/v4l2-core/v4l2-ctrls-defs.c | 10 ++ - include/uapi/linux/v4l2-controls.h | 61 ++++++++++ - include/uapi/linux/videodev2.h | 2 + - 4 files changed, 91 insertions(+) - -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-core.c b/drivers/media/v4l2-core/v4l2-ctrls-core.c -index 111111111111..222222222222 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-core.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-core.c -@@ -418,6 +418,12 @@ void v4l2_ctrl_type_op_log(const struct v4l2_ctrl *ctrl) - case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: - pr_cont("HEVC_SLICE_PARAMS"); - break; -+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS: -+ pr_cont("HEVC_EXT_SPS_ST_RPS"); -+ break; -+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS: -+ pr_cont("HEVC_EXT_SPS_LT_RPS"); -+ break; - case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: - pr_cont("HEVC_SCALING_MATRIX"); - break; -@@ -1173,6 +1179,12 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx, - case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: - break; - -+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS: -+ break; -+ -+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS: -+ break; -+ - case V4L2_CTRL_TYPE_HDR10_CLL_INFO: - break; - -@@ -1921,6 +1933,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl, - case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS: - elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params); - break; -+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS: -+ elem_size = sizeof(struct v4l2_ctrl_hevc_ext_sps_st_rps); -+ break; -+ case V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS: -+ elem_size = sizeof(struct v4l2_ctrl_hevc_ext_sps_lt_rps); -+ break; - case V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX: - elem_size = sizeof(struct v4l2_ctrl_hevc_scaling_matrix); - break; -diff --git a/drivers/media/v4l2-core/v4l2-ctrls-defs.c b/drivers/media/v4l2-core/v4l2-ctrls-defs.c -index 111111111111..222222222222 100644 ---- a/drivers/media/v4l2-core/v4l2-ctrls-defs.c -+++ b/drivers/media/v4l2-core/v4l2-ctrls-defs.c -@@ -1233,6 +1233,8 @@ const char *v4l2_ctrl_get_name(u32 id) - case V4L2_CID_STATELESS_HEVC_DECODE_MODE: return "HEVC Decode Mode"; - case V4L2_CID_STATELESS_HEVC_START_CODE: return "HEVC Start Code"; - case V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS: return "HEVC Entry Point Offsets"; -+ case V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS: return "HEVC Short Term Ref Sets"; -+ case V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS: return "HEVC Long Term Ref Sets"; - case V4L2_CID_STATELESS_AV1_SEQUENCE: return "AV1 Sequence Parameters"; - case V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY: return "AV1 Tile Group Entry"; - case V4L2_CID_STATELESS_AV1_FRAME: return "AV1 Frame Parameters"; -@@ -1578,6 +1580,14 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type, - *type = V4L2_CTRL_TYPE_U32; - *flags |= V4L2_CTRL_FLAG_DYNAMIC_ARRAY; - break; -+ case V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS: -+ *type = V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS; -+ *flags |= V4L2_CTRL_FLAG_DYNAMIC_ARRAY; -+ break; -+ case V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS: -+ *type = V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS; -+ *flags |= V4L2_CTRL_FLAG_DYNAMIC_ARRAY; -+ break; - case V4L2_CID_STATELESS_VP9_COMPRESSED_HDR: - *type = V4L2_CTRL_TYPE_VP9_COMPRESSED_HDR; - break; -diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h -index 111111111111..222222222222 100644 ---- a/include/uapi/linux/v4l2-controls.h -+++ b/include/uapi/linux/v4l2-controls.h -@@ -2088,6 +2088,8 @@ struct v4l2_ctrl_mpeg2_quantisation { - #define V4L2_CID_STATELESS_HEVC_DECODE_MODE (V4L2_CID_CODEC_STATELESS_BASE + 405) - #define V4L2_CID_STATELESS_HEVC_START_CODE (V4L2_CID_CODEC_STATELESS_BASE + 406) - #define V4L2_CID_STATELESS_HEVC_ENTRY_POINT_OFFSETS (V4L2_CID_CODEC_STATELESS_BASE + 407) -+#define V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS (V4L2_CID_CODEC_STATELESS_BASE + 408) -+#define V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS (V4L2_CID_CODEC_STATELESS_BASE + 409) - - enum v4l2_stateless_hevc_decode_mode { - V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED, -@@ -2543,6 +2545,65 @@ struct v4l2_ctrl_hevc_scaling_matrix { - __u8 scaling_list_dc_coef_32x32[2]; - }; - -+#define V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED 0x1 -+ -+/* -+ * struct v4l2_ctrl_hevc_ext_sps_st_rps - HEVC short term RPS parameters -+ * -+ * Dynamic size 1-dimension array for short term RPS. The number of elements -+ * is v4l2_ctrl_hevc_sps::num_short_term_ref_pic_sets. It can contain up to 65 elements. -+ * -+ * @delta_idx_minus1: Specifies the delta compare to the index. See details in section 7.4.8 -+ * "Short-term reference picture set semantics" of the specification. -+ * @delta_rps_sign: Sign of the delta as specified in section 7.4.8 "Short-term reference picture -+ * set semantics" of the specification. -+ * @abs_delta_rps_minus1: Absolute delta RPS as specified in section 7.4.8 "Short-term reference -+ * picture set semantics" of the specification. -+ * @num_negative_pics: Number of short-term RPS entries that have picture order count values less -+ * than the picture order count value of the current picture. -+ * @num_positive_pics: Number of short-term RPS entries that have picture order count values -+ * greater than the picture order count value of the current picture. -+ * @used_by_curr_pic: Bit j specifies if short-term RPS j is used by the current picture. -+ * @use_delta_flag: Bit j equals to 1 specifies that the j-th entry in the source candidate -+ * short-term RPS is included in this candidate short-term RPS. -+ * @delta_poc_s0_minus1: Specifies the negative picture order count delta for the i-th entry in -+ * the short-term RPS. See details in section 7.4.8 "Short-term reference -+ * picture set semantics" of the specification. -+ * @delta_poc_s1_minus1: Specifies the positive picture order count delta for the i-th entry in -+ * the short-term RPS. See details in section 7.4.8 "Short-term reference -+ * picture set semantics" of the specification. -+ * @flags: See V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_{} -+ */ -+struct v4l2_ctrl_hevc_ext_sps_st_rps { -+ __u8 delta_idx_minus1; -+ __u8 delta_rps_sign; -+ __u16 abs_delta_rps_minus1; -+ __u8 num_negative_pics; -+ __u8 num_positive_pics; -+ __u32 used_by_curr_pic; -+ __u32 use_delta_flag; -+ __u16 delta_poc_s0_minus1[16]; -+ __u16 delta_poc_s1_minus1[16]; -+ __u8 flags; -+}; -+ -+#define V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT 0x1 -+ -+/* -+ * struct v4l2_ctrl_hevc_ext_sps_lt_rps - HEVC long term RPS parameters -+ * -+ * Dynamic size 1-dimension array for long term RPS. The number of elements -+ * is v4l2_ctrl_hevc_sps::num_long_term_ref_pics_sps. It can contain up to 65 elements. -+ * -+ * @lt_ref_pic_poc_lsb_sps: picture order count modulo MaxPicOrderCntLsb of the i-th candidate -+ * long-term reference picture. -+ * @flags: See V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_{} -+ */ -+struct v4l2_ctrl_hevc_ext_sps_lt_rps { -+ __u16 lt_ref_pic_poc_lsb_sps; -+ __u8 flags; -+}; -+ - #define V4L2_CID_COLORIMETRY_CLASS_BASE (V4L2_CTRL_CLASS_COLORIMETRY | 0x900) - #define V4L2_CID_COLORIMETRY_CLASS (V4L2_CTRL_CLASS_COLORIMETRY | 1) - -diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h -index 111111111111..222222222222 100644 ---- a/include/uapi/linux/videodev2.h -+++ b/include/uapi/linux/videodev2.h -@@ -1974,6 +1974,8 @@ enum v4l2_ctrl_type { - V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS = 0x0272, - V4L2_CTRL_TYPE_HEVC_SCALING_MATRIX = 0x0273, - V4L2_CTRL_TYPE_HEVC_DECODE_PARAMS = 0x0274, -+ V4L2_CTRL_TYPE_HEVC_EXT_SPS_ST_RPS = 0x0275, -+ V4L2_CTRL_TYPE_HEVC_EXT_SPS_LT_RPS = 0x0276, - - V4L2_CTRL_TYPE_AV1_SEQUENCE = 0x280, - V4L2_CTRL_TYPE_AV1_TILE_GROUP_ENTRY = 0x281, --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Fri, 14 Jun 2024 19:56:19 -0400 -Subject: arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588 - -Add the vdpu381 Video Decoders to the rk3588-base devicetree. - -The RK3588 based SoCs all embed 2 vdpu381 decoders. -This also adds the dedicated IOMMU controllers. - -Signed-off-by: Detlev Casanova ---- - arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 ++++++++++ - 1 file changed, 74 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi -@@ -1252,6 +1252,70 @@ vepu121_3_mmu: iommu@fdbac800 { - #iommu-cells = <0>; - }; - -+ vdec0: video-codec@fdc38000 { -+ compatible = "rockchip,rk3588-vdec"; -+ reg = <0x0 0xfdc38100 0x0 0x500>, -+ <0x0 0xfdc38000 0x0 0x100>, -+ <0x0 0xfdc38600 0x0 0x100>; -+ reg-names = "function", "link", "cache"; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>, -+ <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>; -+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, -+ <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; -+ assigned-clock-rates = <800000000>, <600000000>, -+ <600000000>, <1000000000>; -+ iommus = <&vdec0_mmu>; -+ power-domains = <&power RK3588_PD_RKVDEC0>; -+ resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>, -+ <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>; -+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ sram = <&vdec0_sram>; -+ }; -+ -+ vdec0_mmu: iommu@fdc38700 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_RKVDEC0>; -+ #iommu-cells = <0>; -+ }; -+ -+ vdec1: video-codec@fdc40000 { -+ compatible = "rockchip,rk3588-vdec"; -+ reg = <0x0 0xfdc40100 0x0 0x500>, -+ <0x0 0xfdc40000 0x0 0x100>, -+ <0x0 0xfdc40600 0x0 0x100>; -+ reg-names = "function", "link", "cache"; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>, -+ <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>; -+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, -+ <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; -+ assigned-clock-rates = <800000000>, <600000000>, -+ <600000000>, <1000000000>; -+ iommus = <&vdec1_mmu>; -+ power-domains = <&power RK3588_PD_RKVDEC1>; -+ resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>, -+ <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>; -+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ sram = <&vdec1_sram>; -+ }; -+ -+ vdec1_mmu: iommu@fdc40700 { -+ compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3588_PD_RKVDEC1>; -+ #iommu-cells = <0>; -+ }; -+ - av1d: video-codec@fdc70000 { - compatible = "rockchip,rk3588-av1-vpu"; - reg = <0x0 0xfdc70000 0x0 0x800>; -@@ -3093,6 +3157,16 @@ system_sram2: sram@ff001000 { - ranges = <0x0 0x0 0xff001000 0xef000>; - #address-cells = <1>; - #size-cells = <1>; -+ -+ vdec0_sram: codec-sram@0 { -+ reg = <0x0 0x78000>; -+ pool; -+ }; -+ -+ vdec1_sram: codec-sram@78000 { -+ reg = <0x78000 0x77000>; -+ pool; -+ }; - }; - - pinctrl: pinctrl { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Wed, 11 Jun 2025 10:49:48 -0400 -Subject: arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576 - -Add the vdpu383 Video Decoder variant to the RK3576 device tree. - -Also allow using the dedicated SRAM as a pool. - -Signed-off-by: Detlev Casanova ---- - arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++ - 1 file changed, 36 insertions(+) - -diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi -@@ -1139,6 +1139,41 @@ gpu: gpu@27800000 { - status = "disabled"; - }; - -+ vdec: video-codec@27b00000 { -+ compatible = "rockchip,rk3576-vdec"; -+ reg = <0x0 0x27b00100 0x0 0x500>, -+ <0x0 0x27b00000 0x0 0x100>, -+ <0x0 0x27b00600 0x0 0x100>; -+ reg-names = "function", "link", "cache"; -+ interrupts = ; -+ clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, -+ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, -+ <&cru CLK_RKVDEC_HEVC_CA>; -+ clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>, -+ <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>; -+ assigned-clock-rates = <600000000>, <600000000>, -+ <500000000>, <1000000000>; -+ iommus = <&vdec_mmu>; -+ power-domains = <&power RK3576_PD_VDEC>; -+ resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>, -+ <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>, -+ <&cru SRST_RKVDEC_HEVC_CA>; -+ reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac"; -+ sram = <&rkvdec_sram>; -+ }; -+ -+ vdec_mmu: iommu@27b00800 { -+ compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; -+ reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>; -+ interrupts = ; -+ clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>; -+ clock-names = "aclk", "iface"; -+ power-domains = <&power RK3576_PD_VDEC>; -+ rockchip,disable-mmu-reset; -+ #iommu-cells = <0>; -+ }; -+ - vop: vop@27d00000 { - compatible = "rockchip,rk3576-vop"; - reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; -@@ -2409,6 +2444,7 @@ sram: sram@3ff88000 { - /* start address and size should be 4k align */ - rkvdec_sram: rkvdec-sram@0 { - reg = <0x0 0x78000>; -+ pool; - }; - }; - --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Mon, 23 Jun 2025 18:05:29 +0200 -Subject: bitmap: introduce hardware-specific bitfield operations - -Hardware of various vendors, but very notably Rockchip, often uses -32-bit registers where the upper 16-bit half of the register is a -write-enable mask for the lower half. - -This type of hardware setup allows for more granular concurrent register -write access. - -Over the years, many drivers have hand-rolled their own version of this -macro, usually without any checks, often called something like -HIWORD_UPDATE or FIELD_PREP_HIWORD, commonly with slightly different -semantics between them. - -Clearly there is a demand for such a macro, and thus the demand should -be satisfied in a common header file. As this is a convention that spans -across multiple vendors, and similar conventions may also have -cross-vendor adoption, it's best if it lives in a vendor-agnostic header -file that can be expanded over time. - -Add hw_bitfield.h with two macros: FIELD_PREP_WM16, and -FIELD_PREP_WM16_CONST. The latter is a version that can be used in -initializers, like FIELD_PREP_CONST. - -Suggested-by: -Signed-off-by: Nicolas Frattaroli ---- - include/linux/hw_bitfield.h | 62 ++++++++++ - 1 file changed, 62 insertions(+) - -diff --git a/include/linux/hw_bitfield.h b/include/linux/hw_bitfield.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/include/linux/hw_bitfield.h -@@ -0,0 +1,62 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright (C) 2025, Collabora Ltd. -+ */ -+ -+#ifndef _LINUX_HW_BITFIELD_H -+#define _LINUX_HW_BITFIELD_H -+ -+#include -+#include -+#include -+ -+/** -+ * FIELD_PREP_WM16() - prepare a bitfield element with a mask in the upper half -+ * @_mask: shifted mask defining the field's length and position -+ * @_val: value to put in the field -+ * -+ * FIELD_PREP_WM16() masks and shifts up the value, as well as bitwise ORs the -+ * result with the mask shifted up by 16. -+ * -+ * This is useful for a common design of hardware registers where the upper -+ * 16-bit half of a 32-bit register is used as a write-enable mask. In such a -+ * register, a bit in the lower half is only updated if the corresponding bit -+ * in the upper half is high. -+ */ -+#define FIELD_PREP_WM16(_mask, _val) \ -+ ({ \ -+ typeof(_val) __val = _val; \ -+ typeof(_mask) __mask = _mask; \ -+ __BF_FIELD_CHECK(__mask, ((u16)0U), __val, \ -+ "HWORD_UPDATE: "); \ -+ (((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) | \ -+ ((__mask) << 16); \ -+ }) -+ -+/** -+ * FIELD_PREP_WM16_CONST() - prepare a constant bitfield element with a mask in -+ * the upper half -+ * @_mask: shifted mask defining the field's length and position -+ * @_val: value to put in the field -+ * -+ * FIELD_PREP_WM16_CONST() masks and shifts up the value, as well as bitwise ORs -+ * the result with the mask shifted up by 16. -+ * -+ * This is useful for a common design of hardware registers where the upper -+ * 16-bit half of a 32-bit register is used as a write-enable mask. In such a -+ * register, a bit in the lower half is only updated if the corresponding bit -+ * in the upper half is high. -+ * -+ * Unlike FIELD_PREP_WM16(), this is a constant expression and can therefore -+ * be used in initializers. Error checking is less comfortable for this -+ * version. -+ */ -+#define FIELD_PREP_WM16_CONST(_mask, _val) \ -+ ( \ -+ FIELD_PREP_CONST(_mask, _val) | \ -+ (BUILD_BUG_ON_ZERO(const_true((u64)(_mask) > U16_MAX)) + \ -+ ((_mask) << 16)) \ -+ ) -+ -+ -+#endif /* _LINUX_HW_BITFIELD_H */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Thu, 26 Jun 2025 08:53:07 -0400 -Subject: drm/bridge: synopsys: Do not warn about audio params computation - -There is no need to warn about non pre-computed values, just change it to -dbg. - -Signed-off-by: Detlev Casanova ---- - drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -index 111111111111..222222222222 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c -@@ -276,8 +276,7 @@ static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pix - if (n > 0) - return n; - -- dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n", -- pixel_clk); -+ dev_dbg(hdmi->dev, "Rate %lu missing; compute N dynamically\n", pixel_clk); - - return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate); - } --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Tue, 27 May 2025 11:00:22 -0400 -Subject: media: rkvdec: Switch to using structs instead of writel - -In an effort to merge the rkvdec2 driver [1] with this one, switch from -writel() calls to using structs to represent the register mappings. - -This is done in order to have all supported decoders use the same format -in the future and ease reading of the code. - -Using structs also improves stability as the hardware is tested and -validated downstream using a similar method. -It was noticed, on decoders, that: - - Some registers require to be writen in increasing order [2] - - Some registers, even if unrelated, need to be written to their reset - values (it was the case here for axi_ddr_[rw]data). - -Using structs can also help improving performance later when, e.g. -multicore support is added on RK3588. - -Performance seems to be slightly improved, but at least, not made worse. -Running fluster's JVT-AVC_V1 test suite with GStreamer on the Radxa ROCK -PI 4 SE gives the following times: - -Before this patch: - -- --jobs 1: Ran 129/135 tests successfully in 77.167 secs -- --jobs 6: Ran 129/135 tests successfully in 23.046 secs - -With this patch: -- --jobs 1: Ran 129/135 tests successfully in 70.698 secs -- --jobs 6: Ran 129/135 tests successfully in 22.917 secs - -This also shows that the fluster score hasn't changed. - -[1]: https://lore.kernel.org/all/20250325213303.826925-1-detlev.casanova@collabora.com/ -[2]: https://lore.kernel.org/all/20200127143009.15677-5-andrzej.p@collabora.com/ - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 165 ++- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 66 +- - drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h | 571 +++++++--- - drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c | 231 ++-- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 10 +- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 1 + - 6 files changed, 589 insertions(+), 455 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -@@ -115,6 +115,7 @@ struct rkvdec_h264_run { - struct rkvdec_h264_ctx { - struct rkvdec_aux_buf priv_tbl; - struct rkvdec_h264_reflists reflists; -+ struct rkvdec_regs regs; - }; - - #define CABAC_ENTRY(ctxidx, idc0_m, idc0_n, idc1_m, idc1_n, \ -@@ -841,45 +842,41 @@ static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, - } - - /* -- * dpb poc related registers table -+ * Set the ref POC in the correct register. -+ * -+ * The 32 registers are spread across 3 regions, each alternating top and bottom ref POCs: -+ * - 1: ref 0 to 14 contain top 0 to 7 and bottoms 0 to 6 -+ * - 2: ref 15 to 29 contain top 8 to 14 and bottoms 7 to 14 -+ * - 3: ref 30 and 31 which correspond to top 15 and bottom 15 respectively. - */ --static const u32 poc_reg_tbl_top_field[16] = { -- RKVDEC_REG_H264_POC_REFER0(0), -- RKVDEC_REG_H264_POC_REFER0(2), -- RKVDEC_REG_H264_POC_REFER0(4), -- RKVDEC_REG_H264_POC_REFER0(6), -- RKVDEC_REG_H264_POC_REFER0(8), -- RKVDEC_REG_H264_POC_REFER0(10), -- RKVDEC_REG_H264_POC_REFER0(12), -- RKVDEC_REG_H264_POC_REFER0(14), -- RKVDEC_REG_H264_POC_REFER1(1), -- RKVDEC_REG_H264_POC_REFER1(3), -- RKVDEC_REG_H264_POC_REFER1(5), -- RKVDEC_REG_H264_POC_REFER1(7), -- RKVDEC_REG_H264_POC_REFER1(9), -- RKVDEC_REG_H264_POC_REFER1(11), -- RKVDEC_REG_H264_POC_REFER1(13), -- RKVDEC_REG_H264_POC_REFER2(0) --}; -- --static const u32 poc_reg_tbl_bottom_field[16] = { -- RKVDEC_REG_H264_POC_REFER0(1), -- RKVDEC_REG_H264_POC_REFER0(3), -- RKVDEC_REG_H264_POC_REFER0(5), -- RKVDEC_REG_H264_POC_REFER0(7), -- RKVDEC_REG_H264_POC_REFER0(9), -- RKVDEC_REG_H264_POC_REFER0(11), -- RKVDEC_REG_H264_POC_REFER0(13), -- RKVDEC_REG_H264_POC_REFER1(0), -- RKVDEC_REG_H264_POC_REFER1(2), -- RKVDEC_REG_H264_POC_REFER1(4), -- RKVDEC_REG_H264_POC_REFER1(6), -- RKVDEC_REG_H264_POC_REFER1(8), -- RKVDEC_REG_H264_POC_REFER1(10), -- RKVDEC_REG_H264_POC_REFER1(12), -- RKVDEC_REG_H264_POC_REFER1(14), -- RKVDEC_REG_H264_POC_REFER2(1) --}; -+static void set_poc_reg(struct rkvdec_regs *regs, uint32_t poc, int id, bool bottom) -+{ -+ if (!bottom) { -+ switch (id) { -+ case 0 ... 7: -+ regs->h264.ref0_14_poc[id * 2] = poc; -+ break; -+ case 8 ... 14: -+ regs->h264.ref15_29_poc[(id - 8) * 2 + 1] = poc; -+ break; -+ case 15: -+ regs->h264.ref30_poc = poc; -+ break; -+ } -+ } else { -+ switch (id) { -+ case 0 ... 6: -+ regs->h264.ref0_14_poc[id * 2 + 1] = poc; -+ break; -+ case 7 ... 14: -+ regs->h264.ref15_29_poc[(id - 7) * 2] = poc; -+ break; -+ case 15: -+ regs->h264.ref31_poc = poc; -+ break; -+ } -+ } -+} - - static void config_registers(struct rkvdec_ctx *ctx, - struct rkvdec_h264_run *run) -@@ -894,6 +891,7 @@ static void config_registers(struct rkvdec_ctx *ctx, - struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; - struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; - const struct v4l2_format *f; -+ struct rkvdec_regs *regs = &h264_ctx->regs; - dma_addr_t rlc_addr; - dma_addr_t refer_addr; - u32 rlc_len; -@@ -903,10 +901,11 @@ static void config_registers(struct rkvdec_ctx *ctx, - u32 yuv_virstride = 0; - u32 offset; - dma_addr_t dst_addr; -- u32 reg, i; -+ u32 i; - -- reg = RKVDEC_MODE(RKVDEC_MODE_H264); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ memset(regs, 0, sizeof(*regs)); -+ -+ regs->common.reg02.dec_mode = RKVDEC_MODE_H264; - - f = &ctx->decoded_fmt; - dst_fmt = &f->fmt.pix_mp; -@@ -921,39 +920,35 @@ static void config_registers(struct rkvdec_ctx *ctx, - else if (sps->chroma_format_idc == 2) - yuv_virstride = 2 * y_virstride; - -- reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | -- RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | -- RKVDEC_SLICE_NUM_HIGHBIT | -- RKVDEC_SLICE_NUM_LOWBITS(0x7ff); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); -+ regs->common.reg03.uv_hor_virstride = hor_virstride / 16; -+ regs->common.reg03.y_hor_virstride = hor_virstride / 16; -+ regs->common.reg03.slice_num_highbit = 1; -+ regs->common.reg03.slice_num_lowbits = 0x7ff; - - /* config rlc base address */ - rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -- writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -- writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_RLCWRITE_BASE); -+ regs->common.strm_rlc_base = rlc_addr; -+ regs->h264.rlcwrite_base = rlc_addr; - - rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -- reg = RKVDEC_STRM_LEN(rlc_len); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ regs->common.stream_len = rlc_len; - - /* config cabac table */ - offset = offsetof(struct rkvdec_h264_priv_tbl, cabac_table); -- writel_relaxed(priv_start_addr + offset, -- rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ regs->common.cabactbl_base = priv_start_addr + offset; - - /* config output base address */ - dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -- writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ regs->common.decout_base = dst_addr; - -- reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ regs->common.reg08.y_virstride = y_virstride / 16; - -- reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ regs->common.reg09.yuv_virstride = yuv_virstride / 16; - - /* config ref pic address & poc */ - for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { - struct vb2_buffer *vb_buf = run->ref_buf[i]; -+ struct ref_base *base; - - /* - * If a DPB entry is unused or invalid, address of current destination -@@ -963,54 +958,36 @@ static void config_registers(struct rkvdec_ctx *ctx, - vb_buf = &dst_buf->vb2_buf; - refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); - -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) -- refer_addr |= RKVDEC_COLMV_USED_FLAG_REF; -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD) -- refer_addr |= RKVDEC_FIELD_REF; -- -- if (dpb[i].fields & V4L2_H264_TOP_FIELD_REF) -- refer_addr |= RKVDEC_TOPFIELD_USED_REF; -- if (dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF) -- refer_addr |= RKVDEC_BOTFIELD_USED_REF; -- -- writel_relaxed(dpb[i].top_field_order_cnt, -- rkvdec->regs + poc_reg_tbl_top_field[i]); -- writel_relaxed(dpb[i].bottom_field_order_cnt, -- rkvdec->regs + poc_reg_tbl_bottom_field[i]); -- - if (i < V4L2_H264_NUM_DPB_ENTRIES - 1) -- writel_relaxed(refer_addr, -- rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ base = ®s->h264.ref0_14_base[i]; - else -- writel_relaxed(refer_addr, -- rkvdec->regs + RKVDEC_REG_H264_BASE_REFER15); -- } -+ base = ®s->h264.ref15_base; - -- reg = RKVDEC_CUR_POC(dec_params->top_field_order_cnt); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); -+ base->field_ref = !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD); -+ base->colmv_used_flag_ref = !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE); -+ base->topfield_used_ref = !!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF); -+ base->botfield_used_ref = !!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF); -+ base->base_addr = refer_addr >> 4; - -- reg = RKVDEC_CUR_POC(dec_params->bottom_field_order_cnt); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC1); -+ set_poc_reg(regs, dpb[i].top_field_order_cnt, i, false); -+ set_poc_reg(regs, dpb[i].bottom_field_order_cnt, i, true); -+ } -+ -+ regs->h264.cur_poc = dec_params->top_field_order_cnt; -+ regs->h264.cur_poc1 = dec_params->bottom_field_order_cnt; - - /* config hw pps address */ - offset = offsetof(struct rkvdec_h264_priv_tbl, param_set); -- writel_relaxed(priv_start_addr + offset, -- rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ regs->h264.pps_base = priv_start_addr + offset; - - /* config hw rps address */ - offset = offsetof(struct rkvdec_h264_priv_tbl, rps); -- writel_relaxed(priv_start_addr + offset, -- rkvdec->regs + RKVDEC_REG_RPS_BASE); -- -- reg = RKVDEC_AXI_DDR_RDATA(0); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); -- -- reg = RKVDEC_AXI_DDR_WDATA(0); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+ regs->h264.rps_base = priv_start_addr + offset; - - offset = offsetof(struct rkvdec_h264_priv_tbl, err_info); -- writel_relaxed(priv_start_addr + offset, -- rkvdec->regs + RKVDEC_REG_H264_ERRINFO_BASE); -+ regs->h264.errorinfo_base = priv_start_addr + offset; -+ -+ rkvdec_memcpy_toio(rkvdec->regs, regs, sizeof(*regs)); - } - - #define RKVDEC_H264_MAX_DEPTH_IN_BYTES 2 -@@ -1181,8 +1158,6 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx) - - schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); - -- writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -- writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E); - writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -@@ -129,6 +129,7 @@ struct rkvdec_hevc_run { - struct rkvdec_hevc_ctx { - struct rkvdec_aux_buf priv_tbl; - struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+ struct rkvdec_regs regs; - }; - - struct scaling_factor { -@@ -548,6 +549,7 @@ static void config_registers(struct rkvdec_ctx *ctx, - const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; - const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; - struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_regs *regs = &hevc_ctx->regs; - dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; - const struct v4l2_pix_format_mplane *dst_fmt; - struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -@@ -564,8 +566,9 @@ static void config_registers(struct rkvdec_ctx *ctx, - dma_addr_t dst_addr; - u32 reg, i; - -- reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ memset(regs, 0, sizeof(*regs)); -+ -+ regs->common.reg02.dec_mode = RKVDEC_MODE_HEVC; - - f = &ctx->decoded_fmt; - dst_fmt = &f->fmt.pix_mp; -@@ -580,33 +583,27 @@ static void config_registers(struct rkvdec_ctx *ctx, - else if (sps->chroma_format_idc == 2) - yuv_virstride = 2 * y_virstride; - -- reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | -- RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | -- RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); -+ regs->common.reg03.slice_num_lowbits = run->num_slices; -+ regs->common.reg03.uv_hor_virstride = hor_virstride / 16; -+ regs->common.reg03.y_hor_virstride = hor_virstride / 16; - - /* config rlc base address */ - rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -- writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -+ regs->common.strm_rlc_base = rlc_addr; - - rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -- reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ regs->common.stream_len = round_up(rlc_len, 16) + 64; - - /* config cabac table */ - offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -- writel_relaxed(priv_start_addr + offset, -- rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -+ regs->common.cabactbl_base = priv_start_addr + offset; - - /* config output base address */ - dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -- writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -- -- reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -+ regs->common.decout_base = dst_addr; - -- reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ regs->common.reg08.y_virstride = y_virstride / 16; -+ regs->common.reg09.yuv_virstride = yuv_virstride / 16; - - /* config ref pic address */ - for (i = 0; i < 15; i++) { -@@ -620,33 +617,30 @@ static void config_registers(struct rkvdec_ctx *ctx, - } - - refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -- writel_relaxed(refer_addr | reg, -- rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -- -- reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? -- dpb[i].pic_order_cnt_val : 0); -- writel_relaxed(reg, -- rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); -+ //writel_relaxed(refer_addr | reg, -+ // rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); -+ regs->h264.ref0_14_base[i].base_addr = refer_addr >> 4; -+ regs->h264.ref0_14_base[i].field_ref = !!(reg & 1); -+ regs->h264.ref0_14_base[i].topfield_used_ref = !!(reg & 2); -+ regs->h264.ref0_14_base[i].botfield_used_ref = !!(reg & 4); -+ regs->h264.ref0_14_base[i].colmv_used_flag_ref = !!(reg & 8); -+ -+ regs->h264.ref0_14_poc[i] = i < decode_params->num_active_dpb_entries -+ ? dpb[i].pic_order_cnt_val -+ : 0; - } - -- reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); -+ regs->h264.cur_poc = sl_params->slice_pic_order_cnt; - - /* config hw pps address */ - offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -- writel_relaxed(priv_start_addr + offset, -- rkvdec->regs + RKVDEC_REG_PPS_BASE); -+ regs->h264.pps_base = priv_start_addr + offset; - - /* config hw rps address */ - offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -- writel_relaxed(priv_start_addr + offset, -- rkvdec->regs + RKVDEC_REG_RPS_BASE); -- -- reg = RKVDEC_AXI_DDR_RDATA(0); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); -+ regs->h264.rps_base = priv_start_addr + offset; - -- reg = RKVDEC_AXI_DDR_WDATA(0); -- writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); -+ rkvdec_memcpy_toio(rkvdec->regs, regs, sizeof(*regs)); - } - - #define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -@@ -784,8 +778,6 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - - schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); - -- writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -- writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E); - writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h -@@ -3,7 +3,12 @@ - #ifndef RKVDEC_REGS_H_ - #define RKVDEC_REGS_H_ - --/* rkvcodec registers */ -+#include -+ -+/* -+ * REG_INTERRUPT is accessed via writel to enable the decoder after -+ * configuring it and clear interrupt strmd_error_status -+ */ - #define RKVDEC_REG_INTERRUPT 0x004 - #define RKVDEC_INTERRUPT_DEC_E BIT(0) - #define RKVDEC_CONFIG_DEC_CLK_GATE_E BIT(1) -@@ -30,198 +35,384 @@ - #define RKVDEC_SOFTRESET_RDY BIT(22) - #define RKVDEC_WR_DDR_ALIGN_EN BIT(23) - --#define RKVDEC_REG_SYSCTRL 0x008 --#define RKVDEC_IN_ENDIAN BIT(0) --#define RKVDEC_IN_SWAP32_E BIT(1) --#define RKVDEC_IN_SWAP64_E BIT(2) --#define RKVDEC_STR_ENDIAN BIT(3) --#define RKVDEC_STR_SWAP32_E BIT(4) --#define RKVDEC_STR_SWAP64_E BIT(5) --#define RKVDEC_OUT_ENDIAN BIT(6) --#define RKVDEC_OUT_SWAP32_E BIT(7) --#define RKVDEC_OUT_CBCR_SWAP BIT(8) --#define RKVDEC_RLC_MODE_DIRECT_WRITE BIT(10) --#define RKVDEC_RLC_MODE BIT(11) --#define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) --#define RKVDEC_MODE(x) (((x) & 0x03) << 20) --#define RKVDEC_MODE_HEVC 0 --#define RKVDEC_MODE_H264 1 --#define RKVDEC_MODE_VP9 2 --#define RKVDEC_RPS_MODE BIT(24) --#define RKVDEC_STRM_MODE BIT(25) --#define RKVDEC_H264_STRM_LASTPKT BIT(26) --#define RKVDEC_H264_FIRSTSLICE_FLAG BIT(27) --#define RKVDEC_H264_FRAME_ORSLICE BIT(28) --#define RKVDEC_BUSPR_SLOT_DIS BIT(29) -- --#define RKVDEC_REG_PICPAR 0x00C --#define RKVDEC_Y_HOR_VIRSTRIDE(x) ((x) & 0x1ff) --#define RKVDEC_SLICE_NUM_HIGHBIT BIT(11) --#define RKVDEC_UV_HOR_VIRSTRIDE(x) (((x) & 0x1ff) << 12) --#define RKVDEC_SLICE_NUM_LOWBITS(x) (((x) & 0x7ff) << 21) -- --#define RKVDEC_REG_STRM_RLC_BASE 0x010 -- --#define RKVDEC_REG_STRM_LEN 0x014 --#define RKVDEC_STRM_LEN(x) ((x) & 0x7ffffff) -- --#define RKVDEC_REG_CABACTBL_PROB_BASE 0x018 --#define RKVDEC_REG_DECOUT_BASE 0x01C -- --#define RKVDEC_REG_Y_VIRSTRIDE 0x020 --#define RKVDEC_Y_VIRSTRIDE(x) ((x) & 0xfffff) -- --#define RKVDEC_REG_YUV_VIRSTRIDE 0x024 --#define RKVDEC_YUV_VIRSTRIDE(x) ((x) & 0x1fffff) --#define RKVDEC_REG_H264_BASE_REFER(i) (((i) * 0x04) + 0x028) -- --#define RKVDEC_REG_H264_BASE_REFER15 0x0C0 --#define RKVDEC_FIELD_REF BIT(0) --#define RKVDEC_TOPFIELD_USED_REF BIT(1) --#define RKVDEC_BOTFIELD_USED_REF BIT(2) --#define RKVDEC_COLMV_USED_FLAG_REF BIT(3) -- --#define RKVDEC_REG_VP9_LAST_FRAME_BASE 0x02c --#define RKVDEC_REG_VP9_GOLDEN_FRAME_BASE 0x030 --#define RKVDEC_REG_VP9_ALTREF_FRAME_BASE 0x034 -- --#define RKVDEC_REG_VP9_CPRHEADER_OFFSET 0x028 --#define RKVDEC_VP9_CPRHEADER_OFFSET(x) ((x) & 0xffff) -- --#define RKVDEC_REG_VP9_REFERLAST_BASE 0x02C --#define RKVDEC_REG_VP9_REFERGOLDEN_BASE 0x030 --#define RKVDEC_REG_VP9_REFERALFTER_BASE 0x034 -- --#define RKVDEC_REG_VP9COUNT_BASE 0x038 --#define RKVDEC_VP9COUNT_UPDATE_EN BIT(0) -- --#define RKVDEC_REG_VP9_SEGIDLAST_BASE 0x03C --#define RKVDEC_REG_VP9_SEGIDCUR_BASE 0x040 --#define RKVDEC_REG_VP9_FRAME_SIZE(i) ((i) * 0x04 + 0x044) --#define RKVDEC_VP9_FRAMEWIDTH(x) (((x) & 0xffff) << 0) --#define RKVDEC_VP9_FRAMEHEIGHT(x) (((x) & 0xffff) << 16) -- --#define RKVDEC_VP9_SEGID_GRP(i) ((i) * 0x04 + 0x050) --#define RKVDEC_SEGID_ABS_DELTA(x) ((x) & 0x1) --#define RKVDEC_SEGID_FRAME_QP_DELTA_EN(x) (((x) & 0x1) << 1) --#define RKVDEC_SEGID_FRAME_QP_DELTA(x) (((x) & 0x1ff) << 2) --#define RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE_EN(x) (((x) & 0x1) << 11) --#define RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE(x) (((x) & 0x7f) << 12) --#define RKVDEC_SEGID_REFERINFO_EN(x) (((x) & 0x1) << 19) --#define RKVDEC_SEGID_REFERINFO(x) (((x) & 0x03) << 20) --#define RKVDEC_SEGID_FRAME_SKIP_EN(x) (((x) & 0x1) << 22) -- --#define RKVDEC_VP9_CPRHEADER_CONFIG 0x070 --#define RKVDEC_VP9_TX_MODE(x) ((x) & 0x07) --#define RKVDEC_VP9_FRAME_REF_MODE(x) (((x) & 0x03) << 3) -- --#define RKVDEC_VP9_REF_SCALE(i) ((i) * 0x04 + 0x074) --#define RKVDEC_VP9_REF_HOR_SCALE(x) ((x) & 0xffff) --#define RKVDEC_VP9_REF_VER_SCALE(x) (((x) & 0xffff) << 16) -- --#define RKVDEC_VP9_REF_DELTAS_LASTFRAME 0x080 --#define RKVDEC_REF_DELTAS_LASTFRAME(pos, val) (((val) & 0x7f) << ((pos) * 7)) -- --#define RKVDEC_VP9_INFO_LASTFRAME 0x084 --#define RKVDEC_MODE_DELTAS_LASTFRAME(pos, val) (((val) & 0x7f) << ((pos) * 7)) --#define RKVDEC_SEG_EN_LASTFRAME BIT(16) --#define RKVDEC_LAST_SHOW_FRAME BIT(17) --#define RKVDEC_LAST_INTRA_ONLY BIT(18) --#define RKVDEC_LAST_WIDHHEIGHT_EQCUR BIT(19) --#define RKVDEC_COLOR_SPACE_LASTKEYFRAME(x) (((x) & 0x07) << 20) -- --#define RKVDEC_VP9_INTERCMD_BASE 0x088 -- --#define RKVDEC_VP9_INTERCMD_NUM 0x08C --#define RKVDEC_INTERCMD_NUM(x) ((x) & 0xffffff) -- --#define RKVDEC_VP9_LASTTILE_SIZE 0x090 --#define RKVDEC_LASTTILE_SIZE(x) ((x) & 0xffffff) -- --#define RKVDEC_VP9_HOR_VIRSTRIDE(i) ((i) * 0x04 + 0x094) --#define RKVDEC_HOR_Y_VIRSTRIDE(x) ((x) & 0x1ff) --#define RKVDEC_HOR_UV_VIRSTRIDE(x) (((x) & 0x1ff) << 16) -- --#define RKVDEC_REG_H264_POC_REFER0(i) (((i) * 0x04) + 0x064) --#define RKVDEC_REG_H264_POC_REFER1(i) (((i) * 0x04) + 0x0C4) --#define RKVDEC_REG_H264_POC_REFER2(i) (((i) * 0x04) + 0x120) --#define RKVDEC_POC_REFER(x) ((x) & 0xffffffff) -- --#define RKVDEC_REG_CUR_POC0 0x0A0 --#define RKVDEC_REG_CUR_POC1 0x128 --#define RKVDEC_CUR_POC(x) ((x) & 0xffffffff) -- --#define RKVDEC_REG_RLCWRITE_BASE 0x0A4 --#define RKVDEC_REG_PPS_BASE 0x0A8 --#define RKVDEC_REG_RPS_BASE 0x0AC -- --#define RKVDEC_REG_STRMD_ERR_EN 0x0B0 --#define RKVDEC_STRMD_ERR_EN(x) ((x) & 0xffffffff) -- --#define RKVDEC_REG_STRMD_ERR_STA 0x0B4 --#define RKVDEC_STRMD_ERR_STA(x) ((x) & 0xfffffff) --#define RKVDEC_COLMV_ERR_REF_PICIDX(x) (((x) & 0x0f) << 28) -- --#define RKVDEC_REG_STRMD_ERR_CTU 0x0B8 --#define RKVDEC_STRMD_ERR_CTU(x) ((x) & 0xff) --#define RKVDEC_STRMD_ERR_CTU_YOFFSET(x) (((x) & 0xff) << 8) --#define RKVDEC_STRMFIFO_SPACE2FULL(x) (((x) & 0x7f) << 16) --#define RKVDEC_VP9_ERR_EN_CTU0 BIT(24) -- --#define RKVDEC_REG_SAO_CTU_POS 0x0BC --#define RKVDEC_SAOWR_XOFFSET(x) ((x) & 0x1ff) --#define RKVDEC_SAOWR_YOFFSET(x) (((x) & 0x3ff) << 16) -- --#define RKVDEC_VP9_LAST_FRAME_YSTRIDE 0x0C0 --#define RKVDEC_VP9_GOLDEN_FRAME_YSTRIDE 0x0C4 --#define RKVDEC_VP9_ALTREF_FRAME_YSTRIDE 0x0C8 --#define RKVDEC_VP9_REF_YSTRIDE(x) (((x) & 0xfffff) << 0) -- --#define RKVDEC_VP9_LAST_FRAME_YUVSTRIDE 0x0CC --#define RKVDEC_VP9_REF_YUVSTRIDE(x) (((x) & 0x1fffff) << 0) -- --#define RKVDEC_VP9_REF_COLMV_BASE 0x0D0 -- --#define RKVDEC_REG_PERFORMANCE_CYCLE 0x100 --#define RKVDEC_PERFORMANCE_CYCLE(x) ((x) & 0xffffffff) -- --#define RKVDEC_REG_AXI_DDR_RDATA 0x104 --#define RKVDEC_AXI_DDR_RDATA(x) ((x) & 0xffffffff) -- --#define RKVDEC_REG_AXI_DDR_WDATA 0x108 --#define RKVDEC_AXI_DDR_WDATA(x) ((x) & 0xffffffff) -- --#define RKVDEC_REG_FPGADEBUG_RESET 0x10C --#define RKVDEC_BUSIFD_RESETN BIT(0) --#define RKVDEC_CABAC_RESETN BIT(1) --#define RKVDEC_DEC_CTRL_RESETN BIT(2) --#define RKVDEC_TRANSD_RESETN BIT(3) --#define RKVDEC_INTRA_RESETN BIT(4) --#define RKVDEC_INTER_RESETN BIT(5) --#define RKVDEC_RECON_RESETN BIT(6) --#define RKVDEC_FILER_RESETN BIT(7) -- --#define RKVDEC_REG_PERFORMANCE_SEL 0x110 --#define RKVDEC_PERF_SEL_CNT0(x) ((x) & 0x3f) --#define RKVDEC_PERF_SEL_CNT1(x) (((x) & 0x3f) << 8) --#define RKVDEC_PERF_SEL_CNT2(x) (((x) & 0x3f) << 16) -- --#define RKVDEC_REG_PERFORMANCE_CNT(i) ((i) * 0x04 + 0x114) --#define RKVDEC_PERF_CNT(x) ((x) & 0xffffffff) -- --#define RKVDEC_REG_H264_ERRINFO_BASE 0x12C -- --#define RKVDEC_REG_H264_ERRINFO_NUM 0x130 --#define RKVDEC_SLICEDEC_NUM(x) ((x) & 0x3fff) --#define RKVDEC_STRMD_DECT_ERR_FLAG BIT(15) --#define RKVDEC_ERR_PKT_NUM(x) (((x) & 0x3fff) << 16) -- --#define RKVDEC_REG_H264_ERR_E 0x134 --#define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff) -- - #define RKVDEC_REG_QOS_CTRL 0x18C - -+/* -+ * Cache configuration is not covered in the range of the register struct -+ */ - #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410 - #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 - -+/* -+ * Define the mode values -+ */ -+#define RKVDEC_MODE_HEVC 0 -+#define RKVDEC_MODE_H264 1 -+#define RKVDEC_MODE_VP9 2 -+ -+/* rkvcodec registers */ -+struct rkvdec_common_regs { -+ struct rkvdec_id { -+ u32 minor_ver : 8; -+ u32 level : 1; -+ u32 dec_support : 3; -+ u32 profile : 1; -+ u32 reserved0 : 1; -+ u32 codec_flag : 1; -+ u32 reserved1 : 1; -+ u32 prod_num : 16; -+ } reg00; -+ -+ struct rkvdec_int { -+ u32 dec_e : 1; -+ u32 dec_clkgate_e : 1; -+ u32 reserved0 : 1; -+ u32 timeout_mode : 1; -+ u32 dec_irq_dis : 1; -+ u32 dec_timeout_e : 1; -+ u32 buf_empty_en : 1; -+ u32 stmerror_waitdecfifo_empty : 1; -+ u32 dec_irq : 1; -+ u32 dec_irq_raw : 1; -+ u32 reserved2 : 2; -+ u32 dec_rdy_sta : 1; -+ u32 dec_bus_sta : 1; -+ u32 dec_error_sta : 1; -+ u32 dec_timeout_sta : 1; -+ u32 dec_empty_sta : 1; -+ u32 colmv_ref_error_sta : 1; -+ u32 cabu_end_sta : 1; -+ u32 h264orvp9_error_mode : 1; -+ u32 softrst_en_p : 1; -+ u32 force_softreset_valid : 1; -+ u32 softreset_rdy : 1; -+ u32 reserved1 : 9; -+ } reg01; -+ -+ struct rkvdec_sysctrl { -+ u32 in_endian : 1; -+ u32 in_swap32_e : 1; -+ u32 in_swap64_e : 1; -+ u32 str_endian : 1; -+ u32 str_swap32_e : 1; -+ u32 str_swap64_e : 1; -+ u32 out_endian : 1; -+ u32 out_swap32_e : 1; -+ u32 out_cbcr_swap : 1; -+ u32 reserved0 : 1; -+ u32 rlc_mode_direct_write : 1; -+ u32 rlc_mode : 1; -+ u32 strm_start_bit : 7; -+ u32 reserved1 : 1; -+ u32 dec_mode : 2; -+ u32 reserved2 : 2; -+ u32 rps_mode : 1; -+ u32 stream_mode : 1; -+ u32 stream_lastpacket : 1; -+ u32 firstslice_flag : 1; -+ u32 frame_orslice : 1; -+ u32 buspr_slot_disable : 1; -+ u32 reserved3 : 2; -+ } reg02; -+ -+ struct rkvdec_picpar { -+ u32 y_hor_virstride : 9; -+ u32 reserved : 2; -+ u32 slice_num_highbit : 1; -+ u32 uv_hor_virstride : 9; -+ u32 slice_num_lowbits : 11; -+ } reg03; -+ -+ u32 strm_rlc_base; -+ u32 stream_len; -+ u32 cabactbl_base; -+ u32 decout_base; -+ -+ struct rkvdec_y_virstride { -+ u32 y_virstride : 20; -+ u32 reserved0 : 12; -+ } reg08; -+ -+ struct rkvdec_yuv_virstride { -+ u32 yuv_virstride : 21; -+ u32 reserved0 : 11; -+ } reg09; -+} __packed; -+ -+struct ref_base { -+ u32 field_ref : 1; -+ u32 topfield_used_ref : 1; -+ u32 botfield_used_ref : 1; -+ u32 colmv_used_flag_ref : 1; -+ u32 base_addr : 28; -+}; -+ -+struct rkvdec_h264_regs { -+ struct ref_base ref0_14_base[15]; -+ u32 ref0_14_poc[15]; -+ -+ u32 cur_poc; -+ u32 rlcwrite_base; -+ u32 pps_base; -+ u32 rps_base; -+ -+ u32 strmd_error_e; -+ -+ struct { -+ u32 strmd_error_status : 28; -+ u32 colmv_error_ref_picidx : 4; -+ } reg45; -+ -+ struct { -+ u32 strmd_error_ctu_xoffset : 8; -+ u32 strmd_error_ctu_yoffset : 8; -+ u32 streamfifo_space2full : 7; -+ u32 reserved0 : 1; -+ u32 vp9_error_ctu0_en : 1; -+ u32 reserved1 : 7; -+ } reg46; -+ -+ struct { -+ u32 saowr_xoffet : 9; -+ u32 reserved0 : 7; -+ u32 saowr_yoffset : 10; -+ u32 reserved1 : 6; -+ } reg47; -+ -+ struct ref_base ref15_base; -+ -+ u32 ref15_29_poc[15]; -+ -+ u32 performance_cycle; -+ u32 axi_ddr_rdata; -+ u32 axi_ddr_wdata; -+ -+ struct { -+ u32 busifd_resetn : 1; -+ u32 cabac_resetn : 1; -+ u32 dec_ctrl_resetn : 1; -+ u32 transd_resetn : 1; -+ u32 intra_resetn : 1; -+ u32 inter_resetn : 1; -+ u32 recon_resetn : 1; -+ u32 filer_resetn : 1; -+ u32 reserved0 : 24; -+ } reg67; -+ -+ struct { -+ u32 perf_cnt0_sel : 6; -+ u32 reserved0 : 2; -+ u32 perf_cnt1_sel : 6; -+ u32 reserved1 : 2; -+ u32 perf_cnt2_sel : 6; -+ u32 reserved2 : 10; -+ } reg68; -+ -+ u32 perf_cnt0; -+ u32 perf_cnt1; -+ u32 perf_cnt2; -+ u32 ref30_poc; -+ u32 ref31_poc; -+ u32 cur_poc1; -+ u32 errorinfo_base; -+ -+ struct { -+ u32 slicedec_num : 14; -+ u32 reserved0 : 1; -+ u32 strmd_detect_error_flag : 1; -+ u32 error_packet_num : 14; -+ u32 reserved1 : 2; -+ } reg76; -+ -+ struct { -+ u32 error_en_highbits : 30; -+ u32 reserved : 2; -+ } reg77; -+} __packed; -+ -+struct rkvdec_vp9_regs { -+ struct cprheader_offset { -+ u32 cprheader_offset : 16; -+ u32 reserved : 16; -+ } reg10; -+ -+ u32 refer_bases[3]; -+ u32 count_base; -+ u32 segidlast_base; -+ u32 segidcur_base; -+ -+ struct frame_sizes { -+ u32 framewidth : 16; -+ u32 frameheight : 16; -+ } reg17_19[3]; -+ -+ struct segid_grp { -+ u32 segid_abs_delta : 1; -+ u32 segid_frame_qp_delta_en : 1; -+ u32 segid_frame_qp_delta : 9; -+ u32 segid_frame_loopfilter_value_en : 1; -+ u32 segid_frame_loopfilter_value : 7; -+ u32 segid_referinfo_en : 1; -+ u32 segid_referinfo : 2; -+ u32 segid_frame_skip_en : 1; -+ u32 reserved : 9; -+ } reg20_27[8]; -+ -+ struct cprheader_config { -+ u32 tx_mode : 3; -+ u32 frame_reference_mode : 2; -+ u32 reserved : 27; -+ } reg28; -+ -+ struct ref_scale { -+ u32 ref_hor_scale : 16; -+ u32 ref_ver_scale : 16; -+ } reg29_31[3]; -+ -+ struct ref_deltas_lastframe { -+ u32 ref_deltas_lastframe0 : 7; -+ u32 ref_deltas_lastframe1 : 7; -+ u32 ref_deltas_lastframe2 : 7; -+ u32 ref_deltas_lastframe3 : 7; -+ u32 reserved : 4; -+ } reg32; -+ -+ struct info_lastframe { -+ u32 mode_deltas_lastframe0 : 7; -+ u32 mode_deltas_lastframe1 : 7; -+ u32 reserved0 : 2; -+ u32 segmentation_enable_lstframe : 1; -+ u32 last_show_frame : 1; -+ u32 last_intra_only : 1; -+ u32 last_widthheight_eqcur : 1; -+ u32 color_space_lastkeyframe : 3; -+ u32 reserved1 : 9; -+ } reg33; -+ -+ u32 intercmd_base; -+ -+ struct intercmd_num { -+ u32 intercmd_num : 24; -+ u32 reserved : 8; -+ } reg35; -+ -+ struct lasttile_size { -+ u32 lasttile_size : 24; -+ u32 reserved : 8; -+ } reg36; -+ -+ struct hor_virstride { -+ u32 y_hor_virstride : 9; -+ u32 reserved0 : 7; -+ u32 uv_hor_virstride : 9; -+ u32 reserved1 : 7; -+ } reg37_39[3]; -+ -+ u32 cur_poc; -+ -+ struct rlcwrite_base { -+ u32 reserved : 3; -+ u32 rlcwrite_base : 29; -+ } reg41; -+ -+ struct pps_base { -+ u32 reserved : 4; -+ u32 pps_base : 28; -+ } reg42; -+ -+ struct rps_base { -+ u32 reserved : 4; -+ u32 rps_base : 28; -+ } reg43; -+ -+ struct strmd_error_en { -+ u32 strmd_error_e : 28; -+ u32 reserved : 4; -+ } reg44; -+ -+ u32 vp9_error_info0; -+ -+ struct strmd_error_ctu { -+ u32 strmd_error_ctu_xoffset : 8; -+ u32 strmd_error_ctu_yoffset : 8; -+ u32 streamfifo_space2full : 7; -+ u32 reserved0 : 1; -+ u32 error_ctu0_en : 1; -+ u32 reserved1 : 7; -+ } reg46; -+ -+ struct sao_ctu_position { -+ u32 saowr_xoffet : 9; -+ u32 reserved0 : 7; -+ u32 saowr_yoffset : 10; -+ u32 reserved1 : 6; -+ } reg47; -+ -+ struct ystride { -+ u32 virstride : 20; -+ u32 reserved : 12; -+ } reg48_50[3]; -+ -+ struct lastref_yuvstride { -+ u32 lastref_yuv_virstride : 21; -+ u32 reserved : 11; -+ } reg51; -+ -+ u32 refcolmv_base; -+ -+ u32 reserved0[11]; -+ -+ u32 performance_cycle; -+ u32 axi_ddr_rdata; -+ u32 axi_ddr_wdata; -+ -+ struct fpgadebug_reset { -+ u32 busifd_resetn : 1; -+ u32 cabac_resetn : 1; -+ u32 dec_ctrl_resetn : 1; -+ u32 transd_resetn : 1; -+ u32 intra_resetn : 1; -+ u32 inter_resetn : 1; -+ u32 recon_resetn : 1; -+ u32 filer_resetn : 1; -+ u32 reserved : 24; -+ } reg67; -+ -+ struct performance_sel { -+ u32 perf_cnt0_sel : 6; -+ u32 reserved0 : 2; -+ u32 perf_cnt1_sel : 6; -+ u32 reserved1 : 2; -+ u32 perf_cnt2_sel : 6; -+ u32 reserved : 10; -+ } reg68; -+ -+ u32 perf_cnt0; -+ u32 perf_cnt1; -+ u32 perf_cnt2; -+ -+ u32 reserved1[3]; -+ -+ u32 vp9_error_info1; -+ -+ struct error_ctu1 { -+ u32 vp9_error_ctu1_x : 6; -+ u32 reserved0 : 2; -+ u32 vp9_error_ctu1_y : 6; -+ u32 reserved1 : 1; -+ u32 vp9_error_ctu1_en : 1; -+ u32 reserved2 : 16; -+ } reg76; -+ -+ u32 reserved2; -+} __packed; -+ -+struct rkvdec_regs { -+ struct rkvdec_common_regs common; -+ union { -+ struct rkvdec_h264_regs h264; //TODO: rename to h26x -+ struct rkvdec_vp9_regs vp9; -+ }; -+} __packed; -+ - #endif /* RKVDEC_REGS_H_ */ -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c -@@ -163,6 +163,7 @@ struct rkvdec_vp9_ctx { - struct v4l2_vp9_frame_context frame_context[4]; - struct rkvdec_vp9_frame_info cur; - struct rkvdec_vp9_frame_info last; -+ struct rkvdec_regs regs; - }; - - static void write_coeff_plane(const u8 coef[6][6][3], u8 *coeff_plane) -@@ -347,38 +348,6 @@ static void init_probs(struct rkvdec_ctx *ctx, - init_inter_probs(ctx, run); - } - --struct rkvdec_vp9_ref_reg { -- u32 reg_frm_size; -- u32 reg_hor_stride; -- u32 reg_y_stride; -- u32 reg_yuv_stride; -- u32 reg_ref_base; --}; -- --static struct rkvdec_vp9_ref_reg ref_regs[] = { -- { -- .reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(0), -- .reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(0), -- .reg_y_stride = RKVDEC_VP9_LAST_FRAME_YSTRIDE, -- .reg_yuv_stride = RKVDEC_VP9_LAST_FRAME_YUVSTRIDE, -- .reg_ref_base = RKVDEC_REG_VP9_LAST_FRAME_BASE, -- }, -- { -- .reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(1), -- .reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(1), -- .reg_y_stride = RKVDEC_VP9_GOLDEN_FRAME_YSTRIDE, -- .reg_yuv_stride = 0, -- .reg_ref_base = RKVDEC_REG_VP9_GOLDEN_FRAME_BASE, -- }, -- { -- .reg_frm_size = RKVDEC_REG_VP9_FRAME_SIZE(2), -- .reg_hor_stride = RKVDEC_VP9_HOR_VIRSTRIDE(2), -- .reg_y_stride = RKVDEC_VP9_ALTREF_FRAME_YSTRIDE, -- .reg_yuv_stride = 0, -- .reg_ref_base = RKVDEC_REG_VP9_ALTREF_FRAME_BASE, -- } --}; -- - static struct rkvdec_decoded_buffer * - get_ref_buf(struct rkvdec_ctx *ctx, struct vb2_v4l2_buffer *dst, u64 timestamp) - { -@@ -412,18 +381,17 @@ static dma_addr_t get_mv_base_addr(struct rkvdec_decoded_buffer *buf) - static void config_ref_registers(struct rkvdec_ctx *ctx, - const struct rkvdec_vp9_run *run, - struct rkvdec_decoded_buffer *ref_buf, -- struct rkvdec_vp9_ref_reg *ref_reg) -+ int i) - { - unsigned int aligned_pitch, aligned_height, y_len, yuv_len; -- struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_regs *regs = &vp9_ctx->regs; - - aligned_height = round_up(ref_buf->vp9.height, 64); -- writel_relaxed(RKVDEC_VP9_FRAMEWIDTH(ref_buf->vp9.width) | -- RKVDEC_VP9_FRAMEHEIGHT(ref_buf->vp9.height), -- rkvdec->regs + ref_reg->reg_frm_size); -+ regs->vp9.reg17_19[i].frameheight = ref_buf->vp9.height; -+ regs->vp9.reg17_19[i].framewidth = ref_buf->vp9.width; - -- writel_relaxed(vb2_dma_contig_plane_dma_addr(&ref_buf->base.vb.vb2_buf, 0), -- rkvdec->regs + ref_reg->reg_ref_base); -+ regs->vp9.refer_bases[i] = vb2_dma_contig_plane_dma_addr(&ref_buf->base.vb.vb2_buf, 0); - - if (&ref_buf->base.vb == run->base.bufs.dst) - return; -@@ -432,59 +400,50 @@ static void config_ref_registers(struct rkvdec_ctx *ctx, - y_len = aligned_height * aligned_pitch; - yuv_len = (y_len * 3) / 2; - -- writel_relaxed(RKVDEC_HOR_Y_VIRSTRIDE(aligned_pitch / 16) | -- RKVDEC_HOR_UV_VIRSTRIDE(aligned_pitch / 16), -- rkvdec->regs + ref_reg->reg_hor_stride); -- writel_relaxed(RKVDEC_VP9_REF_YSTRIDE(y_len / 16), -- rkvdec->regs + ref_reg->reg_y_stride); -- -- if (!ref_reg->reg_yuv_stride) -- return; -+ regs->vp9.reg37_39[i].y_hor_virstride = aligned_pitch / 16; -+ regs->vp9.reg37_39[i].uv_hor_virstride = aligned_pitch / 16; -+ regs->vp9.reg48_50[i].virstride = y_len / 16; - -- writel_relaxed(RKVDEC_VP9_REF_YUVSTRIDE(yuv_len / 16), -- rkvdec->regs + ref_reg->reg_yuv_stride); -+ if (!i) -+ regs->vp9.reg51.lastref_yuv_virstride = yuv_len / 16; - } - - static void config_seg_registers(struct rkvdec_ctx *ctx, unsigned int segid) - { - struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -+ struct rkvdec_regs *regs = &vp9_ctx->regs; - const struct v4l2_vp9_segmentation *seg; -- struct rkvdec_dev *rkvdec = ctx->dev; - s16 feature_val; - int feature_id; -- u32 val = 0; - - seg = vp9_ctx->last.valid ? &vp9_ctx->last.seg : &vp9_ctx->cur.seg; - feature_id = V4L2_VP9_SEG_LVL_ALT_Q; - if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) { - feature_val = seg->feature_data[segid][feature_id]; -- val |= RKVDEC_SEGID_FRAME_QP_DELTA_EN(1) | -- RKVDEC_SEGID_FRAME_QP_DELTA(feature_val); -+ regs->vp9.reg20_27[segid].segid_frame_qp_delta_en = 1; -+ regs->vp9.reg20_27[segid].segid_frame_qp_delta = feature_val; - } - - feature_id = V4L2_VP9_SEG_LVL_ALT_L; - if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) { - feature_val = seg->feature_data[segid][feature_id]; -- val |= RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE_EN(1) | -- RKVDEC_SEGID_FRAME_LOOPFILTER_VALUE(feature_val); -+ regs->vp9.reg20_27[segid].segid_frame_loopfilter_value_en = 1; -+ regs->vp9.reg20_27[segid].segid_frame_loopfilter_value = feature_val; - } - - feature_id = V4L2_VP9_SEG_LVL_REF_FRAME; - if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) { - feature_val = seg->feature_data[segid][feature_id]; -- val |= RKVDEC_SEGID_REFERINFO_EN(1) | -- RKVDEC_SEGID_REFERINFO(feature_val); -+ regs->vp9.reg20_27[segid].segid_referinfo_en = 1; -+ regs->vp9.reg20_27[segid].segid_referinfo = feature_val; - } - - feature_id = V4L2_VP9_SEG_LVL_SKIP; -- if (v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid)) -- val |= RKVDEC_SEGID_FRAME_SKIP_EN(1); -- -- if (!segid && -- (seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE)) -- val |= RKVDEC_SEGID_ABS_DELTA(1); -+ regs->vp9.reg20_27[segid].segid_frame_skip_en = -+ v4l2_vp9_seg_feat_enabled(seg->feature_enabled, feature_id, segid); - -- writel_relaxed(val, rkvdec->regs + RKVDEC_VP9_SEGID_GRP(segid)); -+ regs->vp9.reg20_27[segid].segid_abs_delta = !segid && -+ (seg->flags & V4L2_VP9_SEGMENTATION_FLAG_ABS_OR_DELTA_UPDATE); - } - - static void update_dec_buf_info(struct rkvdec_decoded_buffer *buf, -@@ -521,7 +480,8 @@ static void config_registers(struct rkvdec_ctx *ctx, - struct rkvdec_decoded_buffer *ref_bufs[3]; - struct rkvdec_decoded_buffer *dst, *last, *mv_ref; - struct rkvdec_vp9_ctx *vp9_ctx = ctx->priv; -- u32 val, last_frame_info = 0; -+ struct rkvdec_regs *regs = &vp9_ctx->regs; -+ u32 val; - const struct v4l2_vp9_segmentation *seg; - struct rkvdec_dev *rkvdec = ctx->dev; - dma_addr_t addr; -@@ -547,8 +507,7 @@ static void config_registers(struct rkvdec_ctx *ctx, - (V4L2_VP9_FRAME_FLAG_KEY_FRAME | - V4L2_VP9_FRAME_FLAG_INTRA_ONLY)); - -- writel_relaxed(RKVDEC_MODE(RKVDEC_MODE_VP9), -- rkvdec->regs + RKVDEC_REG_SYSCTRL); -+ regs->common.reg02.dec_mode = RKVDEC_MODE_VP9; - - bit_depth = dec_params->bit_depth; - aligned_height = round_up(ctx->decoded_fmt.fmt.pix_mp.height, 64); -@@ -560,17 +519,14 @@ static void config_registers(struct rkvdec_ctx *ctx, - uv_len = y_len / 2; - yuv_len = y_len + uv_len; - -- writel_relaxed(RKVDEC_Y_HOR_VIRSTRIDE(aligned_pitch / 16) | -- RKVDEC_UV_HOR_VIRSTRIDE(aligned_pitch / 16), -- rkvdec->regs + RKVDEC_REG_PICPAR); -- writel_relaxed(RKVDEC_Y_VIRSTRIDE(y_len / 16), -- rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); -- writel_relaxed(RKVDEC_YUV_VIRSTRIDE(yuv_len / 16), -- rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); -+ regs->common.reg03.y_hor_virstride = aligned_pitch / 16; -+ regs->common.reg03.uv_hor_virstride = aligned_pitch / 16; -+ regs->common.reg08.y_virstride = y_len / 16; -+ regs->common.reg09.yuv_virstride = yuv_len / 16; - - stream_len = vb2_get_plane_payload(&run->base.bufs.src->vb2_buf, 0); -- writel_relaxed(RKVDEC_STRM_LEN(stream_len), -- rkvdec->regs + RKVDEC_REG_STRM_LEN); -+ -+ regs->common.stream_len = stream_len; - - /* - * Reset count buffer, because decoder only output intra related syntax -@@ -588,14 +544,13 @@ static void config_registers(struct rkvdec_ctx *ctx, - vp9_ctx->cur.segmapid++; - - for (i = 0; i < ARRAY_SIZE(ref_bufs); i++) -- config_ref_registers(ctx, run, ref_bufs[i], &ref_regs[i]); -+ config_ref_registers(ctx, run, ref_bufs[i], i); - - for (i = 0; i < 8; i++) - config_seg_registers(ctx, i); - -- writel_relaxed(RKVDEC_VP9_TX_MODE(vp9_ctx->cur.tx_mode) | -- RKVDEC_VP9_FRAME_REF_MODE(dec_params->reference_mode), -- rkvdec->regs + RKVDEC_VP9_CPRHEADER_CONFIG); -+ regs->vp9.reg28.tx_mode = vp9_ctx->cur.tx_mode; -+ regs->vp9.reg28.frame_reference_mode = dec_params->reference_mode; - - if (!intra_only) { - const struct v4l2_vp9_loop_filter *lf; -@@ -609,43 +564,56 @@ static void config_registers(struct rkvdec_ctx *ctx, - val = 0; - for (i = 0; i < ARRAY_SIZE(lf->ref_deltas); i++) { - delta = lf->ref_deltas[i]; -- val |= RKVDEC_REF_DELTAS_LASTFRAME(i, delta); -+ switch (i) { -+ case 0: -+ regs->vp9.reg32.ref_deltas_lastframe0 = delta; -+ break; -+ case 1: -+ regs->vp9.reg32.ref_deltas_lastframe1 = delta; -+ break; -+ case 2: -+ regs->vp9.reg32.ref_deltas_lastframe2 = delta; -+ break; -+ case 3: -+ regs->vp9.reg32.ref_deltas_lastframe3 = delta; -+ break; -+ } - } - -- writel_relaxed(val, -- rkvdec->regs + RKVDEC_VP9_REF_DELTAS_LASTFRAME); -- - for (i = 0; i < ARRAY_SIZE(lf->mode_deltas); i++) { - delta = lf->mode_deltas[i]; -- last_frame_info |= RKVDEC_MODE_DELTAS_LASTFRAME(i, -- delta); -+ switch (i) { -+ case 0: -+ regs->vp9.reg33.mode_deltas_lastframe0 = delta; -+ break; -+ case 1: -+ regs->vp9.reg33.mode_deltas_lastframe1 = delta; -+ break; -+ } - } - } - -- if (vp9_ctx->last.valid && !intra_only && -- vp9_ctx->last.seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED) -- last_frame_info |= RKVDEC_SEG_EN_LASTFRAME; -+ regs->vp9.reg33.segmentation_enable_lstframe = -+ vp9_ctx->last.valid && !intra_only && -+ vp9_ctx->last.seg.flags & V4L2_VP9_SEGMENTATION_FLAG_ENABLED; - -- if (vp9_ctx->last.valid && -- vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_SHOW_FRAME) -- last_frame_info |= RKVDEC_LAST_SHOW_FRAME; -+ regs->vp9.reg33.last_show_frame = -+ vp9_ctx->last.valid && -+ vp9_ctx->last.flags & V4L2_VP9_FRAME_FLAG_SHOW_FRAME; - -- if (vp9_ctx->last.valid && -- vp9_ctx->last.flags & -- (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY)) -- last_frame_info |= RKVDEC_LAST_INTRA_ONLY; -+ regs->vp9.reg33.last_intra_only = -+ vp9_ctx->last.valid && -+ vp9_ctx->last.flags & -+ (V4L2_VP9_FRAME_FLAG_KEY_FRAME | V4L2_VP9_FRAME_FLAG_INTRA_ONLY); - -- if (vp9_ctx->last.valid && -- last->vp9.width == dst->vp9.width && -- last->vp9.height == dst->vp9.height) -- last_frame_info |= RKVDEC_LAST_WIDHHEIGHT_EQCUR; -+ regs->vp9.reg33.last_widthheight_eqcur = -+ vp9_ctx->last.valid && -+ last->vp9.width == dst->vp9.width && -+ last->vp9.height == dst->vp9.height; - -- writel_relaxed(last_frame_info, -- rkvdec->regs + RKVDEC_VP9_INFO_LASTFRAME); -- -- writel_relaxed(stream_len - dec_params->compressed_header_size - -- dec_params->uncompressed_header_size, -- rkvdec->regs + RKVDEC_VP9_LASTTILE_SIZE); -+ regs->vp9.reg36.lasttile_size = -+ stream_len - dec_params->compressed_header_size - -+ dec_params->uncompressed_header_size; - - for (i = 0; !intra_only && i < ARRAY_SIZE(ref_bufs); i++) { - unsigned int refw = ref_bufs[i]->vp9.width; -@@ -654,29 +622,28 @@ static void config_registers(struct rkvdec_ctx *ctx, - - hscale = (refw << 14) / dst->vp9.width; - vscale = (refh << 14) / dst->vp9.height; -- writel_relaxed(RKVDEC_VP9_REF_HOR_SCALE(hscale) | -- RKVDEC_VP9_REF_VER_SCALE(vscale), -- rkvdec->regs + RKVDEC_VP9_REF_SCALE(i)); -+ -+ regs->vp9.reg29_31[i].ref_hor_scale = hscale; -+ regs->vp9.reg29_31[i].ref_ver_scale = vscale; - } - - addr = vb2_dma_contig_plane_dma_addr(&dst->base.vb.vb2_buf, 0); -- writel_relaxed(addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); -+ regs->common.decout_base = addr; - addr = vb2_dma_contig_plane_dma_addr(&run->base.bufs.src->vb2_buf, 0); -- writel_relaxed(addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); -- writel_relaxed(vp9_ctx->priv_tbl.dma + -- offsetof(struct rkvdec_vp9_priv_tbl, probs), -- rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); -- writel_relaxed(vp9_ctx->count_tbl.dma, -- rkvdec->regs + RKVDEC_REG_VP9COUNT_BASE); -- -- writel_relaxed(vp9_ctx->priv_tbl.dma + -- offsetof(struct rkvdec_vp9_priv_tbl, segmap) + -- (RKVDEC_VP9_MAX_SEGMAP_SIZE * vp9_ctx->cur.segmapid), -- rkvdec->regs + RKVDEC_REG_VP9_SEGIDCUR_BASE); -- writel_relaxed(vp9_ctx->priv_tbl.dma + -- offsetof(struct rkvdec_vp9_priv_tbl, segmap) + -- (RKVDEC_VP9_MAX_SEGMAP_SIZE * (!vp9_ctx->cur.segmapid)), -- rkvdec->regs + RKVDEC_REG_VP9_SEGIDLAST_BASE); -+ regs->common.strm_rlc_base = addr; -+ -+ regs->common.cabactbl_base = vp9_ctx->priv_tbl.dma + -+ offsetof(struct rkvdec_vp9_priv_tbl, probs); -+ -+ regs->vp9.count_base = vp9_ctx->count_tbl.dma; -+ -+ regs->vp9.segidlast_base = vp9_ctx->priv_tbl.dma + -+ offsetof(struct rkvdec_vp9_priv_tbl, segmap) + -+ (RKVDEC_VP9_MAX_SEGMAP_SIZE * (!vp9_ctx->cur.segmapid)); -+ -+ regs->vp9.segidcur_base = vp9_ctx->priv_tbl.dma + -+ offsetof(struct rkvdec_vp9_priv_tbl, segmap) + -+ (RKVDEC_VP9_MAX_SEGMAP_SIZE * vp9_ctx->cur.segmapid); - - if (!intra_only && - !(dec_params->flags & V4L2_VP9_FRAME_FLAG_ERROR_RESILIENT) && -@@ -685,12 +652,14 @@ static void config_registers(struct rkvdec_ctx *ctx, - else - mv_ref = dst; - -- writel_relaxed(get_mv_base_addr(mv_ref), -- rkvdec->regs + RKVDEC_VP9_REF_COLMV_BASE); -+ regs->vp9.refcolmv_base = get_mv_base_addr(mv_ref); - -- writel_relaxed(ctx->decoded_fmt.fmt.pix_mp.width | -- (ctx->decoded_fmt.fmt.pix_mp.height << 16), -- rkvdec->regs + RKVDEC_REG_PERFORMANCE_CYCLE); -+ regs->vp9.performance_cycle = ctx->decoded_fmt.fmt.pix_mp.width | -+ (ctx->decoded_fmt.fmt.pix_mp.height << 16); -+ -+ regs->vp9.reg44.strmd_error_e = 0xe; -+ -+ rkvdec_memcpy_toio(rkvdec->regs, regs, sizeof(*regs)); - } - - static int validate_dec_params(struct rkvdec_ctx *ctx, -@@ -823,8 +792,6 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) - writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); - writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); - -- writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); -- - if (rkvdec->quirks & RKVDEC_QUIRK_DISABLE_QOS) { - u32 reg; - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -903,6 +903,15 @@ void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run) - v4l2_ctrl_request_complete(src_req, &ctx->ctrl_hdl); - } - -+void rkvdec_memcpy_toio(void __iomem *dst, void *src, size_t len) -+{ -+#ifdef CONFIG_ARM64 -+ __iowrite32_copy(dst, src, len / 4); -+#else -+ memcpy_toio(dst, src, len); -+#endif -+} -+ - static void rkvdec_device_run(void *priv) - { - struct rkvdec_ctx *ctx = priv; -@@ -1217,7 +1226,6 @@ static void rkvdec_watchdog_func(struct work_struct *work) - if (ctx) { - dev_err(rkvdec->dev, "Frame processing timed out!\n"); - writel(RKVDEC_IRQ_DIS, rkvdec->regs + RKVDEC_REG_INTERRUPT); -- writel(0, rkvdec->regs + RKVDEC_REG_SYSCTRL); - rkvdec_job_finish(ctx, VB2_BUF_STATE_ERROR); - } - } -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -151,6 +151,7 @@ struct rkvdec_aux_buf { - - void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); -+void rkvdec_memcpy_toio(void __iomem *dst, void *src, size_t len); - - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Tue, 10 Jun 2025 10:34:55 -0400 -Subject: media: rkvdec: Move cabac tables to their own source file - -This is in preparation to add support for new variants that will use the -same tables. - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/Makefile | 7 +- - drivers/media/platform/rockchip/rkvdec/{rkvdec-hevc-data.c => rkvdec-cabac.c} | 506 +++++++++- - drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 501 +-------- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 6 +- - 4 files changed, 514 insertions(+), 506 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/Makefile -+++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -1,3 +1,8 @@ - obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o - --rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o -+rockchip-vdec-y += \ -+ rkvdec.o \ -+ rkvdec-cabac.o \ -+ rkvdec-h264.o \ -+ rkvdec-hevc.o \ -+ rkvdec-vp9.o -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-cabac.c -similarity index 86% -rename from drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c -rename to drivers/media/platform/rockchip/rkvdec/rkvdec-cabac.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-cabac.c -@@ -1,19 +1,517 @@ - // SPDX-License-Identifier: GPL-2.0 - /* -- * Rockchip Video Decoder driver -+ * Rockchip Video Decoder CABAC tables - * - * Copyright (C) 2023 Collabora, Ltd. - * Sebastian Fricke -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon - */ - - #include - --#define RKV_CABAC_TABLE_SIZE 27456 -+#define CABAC_ENTRY(ctxidx, idc0_m, idc0_n, idc1_m, idc1_n, \ -+ idc2_m, idc2_n, intra_m, intra_n) \ -+ [0][(ctxidx)] = {idc0_m, idc0_n}, \ -+ [1][(ctxidx)] = {idc1_m, idc1_n}, \ -+ [2][(ctxidx)] = {idc2_m, idc2_n}, \ -+ [3][(ctxidx)] = {intra_m, intra_n} - - /* -- * This file is #include from rkvdec-hevc.c and not compiled. -+ * Constant CABAC table. -+ * Built from the tables described in section '9.3.1.1 Initialisation process -+ * for context variables' of the H264 spec. - */ --static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { -+const s8 rkvdec_h264_cabac_table[4][464][2] = { -+ /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */ -+ CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15), -+ CABAC_ENTRY(1, 2, 54, 2, 54, 2, 54, 2, 54), -+ CABAC_ENTRY(2, 3, 74, 3, 74, 3, 74, 3, 74), -+ CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15), -+ CABAC_ENTRY(4, 2, 54, 2, 54, 2, 54, 2, 54), -+ CABAC_ENTRY(5, 3, 74, 3, 74, 3, 74, 3, 74), -+ CABAC_ENTRY(6, -28, 127, -28, 127, -28, 127, -28, 127), -+ CABAC_ENTRY(7, -23, 104, -23, 104, -23, 104, -23, 104), -+ CABAC_ENTRY(8, -6, 53, -6, 53, -6, 53, -6, 53), -+ CABAC_ENTRY(9, -1, 54, -1, 54, -1, 54, -1, 54), -+ CABAC_ENTRY(10, 7, 51, 7, 51, 7, 51, 7, 51), -+ -+ /* Table 9-13 – Values of variables m and n for ctxIdx from 11 to 23 */ -+ CABAC_ENTRY(11, 23, 33, 22, 25, 29, 16, 0, 0), -+ CABAC_ENTRY(12, 23, 2, 34, 0, 25, 0, 0, 0), -+ CABAC_ENTRY(13, 21, 0, 16, 0, 14, 0, 0, 0), -+ CABAC_ENTRY(14, 1, 9, -2, 9, -10, 51, 0, 0), -+ CABAC_ENTRY(15, 0, 49, 4, 41, -3, 62, 0, 0), -+ CABAC_ENTRY(16, -37, 118, -29, 118, -27, 99, 0, 0), -+ CABAC_ENTRY(17, 5, 57, 2, 65, 26, 16, 0, 0), -+ CABAC_ENTRY(18, -13, 78, -6, 71, -4, 85, 0, 0), -+ CABAC_ENTRY(19, -11, 65, -13, 79, -24, 102, 0, 0), -+ CABAC_ENTRY(20, 1, 62, 5, 52, 5, 57, 0, 0), -+ CABAC_ENTRY(21, 12, 49, 9, 50, 6, 57, 0, 0), -+ CABAC_ENTRY(22, -4, 73, -3, 70, -17, 73, 0, 0), -+ CABAC_ENTRY(23, 17, 50, 10, 54, 14, 57, 0, 0), -+ -+ /* Table 9-14 – Values of variables m and n for ctxIdx from 24 to 39 */ -+ CABAC_ENTRY(24, 18, 64, 26, 34, 20, 40, 0, 0), -+ CABAC_ENTRY(25, 9, 43, 19, 22, 20, 10, 0, 0), -+ CABAC_ENTRY(26, 29, 0, 40, 0, 29, 0, 0, 0), -+ CABAC_ENTRY(27, 26, 67, 57, 2, 54, 0, 0, 0), -+ CABAC_ENTRY(28, 16, 90, 41, 36, 37, 42, 0, 0), -+ CABAC_ENTRY(29, 9, 104, 26, 69, 12, 97, 0, 0), -+ CABAC_ENTRY(30, -46, 127, -45, 127, -32, 127, 0, 0), -+ CABAC_ENTRY(31, -20, 104, -15, 101, -22, 117, 0, 0), -+ CABAC_ENTRY(32, 1, 67, -4, 76, -2, 74, 0, 0), -+ CABAC_ENTRY(33, -13, 78, -6, 71, -4, 85, 0, 0), -+ CABAC_ENTRY(34, -11, 65, -13, 79, -24, 102, 0, 0), -+ CABAC_ENTRY(35, 1, 62, 5, 52, 5, 57, 0, 0), -+ CABAC_ENTRY(36, -6, 86, 6, 69, -6, 93, 0, 0), -+ CABAC_ENTRY(37, -17, 95, -13, 90, -14, 88, 0, 0), -+ CABAC_ENTRY(38, -6, 61, 0, 52, -6, 44, 0, 0), -+ CABAC_ENTRY(39, 9, 45, 8, 43, 4, 55, 0, 0), -+ -+ /* Table 9-15 – Values of variables m and n for ctxIdx from 40 to 53 */ -+ CABAC_ENTRY(40, -3, 69, -2, 69, -11, 89, 0, 0), -+ CABAC_ENTRY(41, -6, 81, -5, 82, -15, 103, 0, 0), -+ CABAC_ENTRY(42, -11, 96, -10, 96, -21, 116, 0, 0), -+ CABAC_ENTRY(43, 6, 55, 2, 59, 19, 57, 0, 0), -+ CABAC_ENTRY(44, 7, 67, 2, 75, 20, 58, 0, 0), -+ CABAC_ENTRY(45, -5, 86, -3, 87, 4, 84, 0, 0), -+ CABAC_ENTRY(46, 2, 88, -3, 100, 6, 96, 0, 0), -+ CABAC_ENTRY(47, 0, 58, 1, 56, 1, 63, 0, 0), -+ CABAC_ENTRY(48, -3, 76, -3, 74, -5, 85, 0, 0), -+ CABAC_ENTRY(49, -10, 94, -6, 85, -13, 106, 0, 0), -+ CABAC_ENTRY(50, 5, 54, 0, 59, 5, 63, 0, 0), -+ CABAC_ENTRY(51, 4, 69, -3, 81, 6, 75, 0, 0), -+ CABAC_ENTRY(52, -3, 81, -7, 86, -3, 90, 0, 0), -+ CABAC_ENTRY(53, 0, 88, -5, 95, -1, 101, 0, 0), -+ -+ /* Table 9-16 – Values of variables m and n for ctxIdx from 54 to 59 */ -+ CABAC_ENTRY(54, -7, 67, -1, 66, 3, 55, 0, 0), -+ CABAC_ENTRY(55, -5, 74, -1, 77, -4, 79, 0, 0), -+ CABAC_ENTRY(56, -4, 74, 1, 70, -2, 75, 0, 0), -+ CABAC_ENTRY(57, -5, 80, -2, 86, -12, 97, 0, 0), -+ CABAC_ENTRY(58, -7, 72, -5, 72, -7, 50, 0, 0), -+ CABAC_ENTRY(59, 1, 58, 0, 61, 1, 60, 0, 0), -+ -+ /* Table 9-17 – Values of variables m and n for ctxIdx from 60 to 69 */ -+ CABAC_ENTRY(60, 0, 41, 0, 41, 0, 41, 0, 41), -+ CABAC_ENTRY(61, 0, 63, 0, 63, 0, 63, 0, 63), -+ CABAC_ENTRY(62, 0, 63, 0, 63, 0, 63, 0, 63), -+ CABAC_ENTRY(63, 0, 63, 0, 63, 0, 63, 0, 63), -+ CABAC_ENTRY(64, -9, 83, -9, 83, -9, 83, -9, 83), -+ CABAC_ENTRY(65, 4, 86, 4, 86, 4, 86, 4, 86), -+ CABAC_ENTRY(66, 0, 97, 0, 97, 0, 97, 0, 97), -+ CABAC_ENTRY(67, -7, 72, -7, 72, -7, 72, -7, 72), -+ CABAC_ENTRY(68, 13, 41, 13, 41, 13, 41, 13, 41), -+ CABAC_ENTRY(69, 3, 62, 3, 62, 3, 62, 3, 62), -+ -+ /* Table 9-18 – Values of variables m and n for ctxIdx from 70 to 104 */ -+ CABAC_ENTRY(70, 0, 45, 13, 15, 7, 34, 0, 11), -+ CABAC_ENTRY(71, -4, 78, 7, 51, -9, 88, 1, 55), -+ CABAC_ENTRY(72, -3, 96, 2, 80, -20, 127, 0, 69), -+ CABAC_ENTRY(73, -27, 126, -39, 127, -36, 127, -17, 127), -+ CABAC_ENTRY(74, -28, 98, -18, 91, -17, 91, -13, 102), -+ CABAC_ENTRY(75, -25, 101, -17, 96, -14, 95, 0, 82), -+ CABAC_ENTRY(76, -23, 67, -26, 81, -25, 84, -7, 74), -+ CABAC_ENTRY(77, -28, 82, -35, 98, -25, 86, -21, 107), -+ CABAC_ENTRY(78, -20, 94, -24, 102, -12, 89, -27, 127), -+ CABAC_ENTRY(79, -16, 83, -23, 97, -17, 91, -31, 127), -+ CABAC_ENTRY(80, -22, 110, -27, 119, -31, 127, -24, 127), -+ CABAC_ENTRY(81, -21, 91, -24, 99, -14, 76, -18, 95), -+ CABAC_ENTRY(82, -18, 102, -21, 110, -18, 103, -27, 127), -+ CABAC_ENTRY(83, -13, 93, -18, 102, -13, 90, -21, 114), -+ CABAC_ENTRY(84, -29, 127, -36, 127, -37, 127, -30, 127), -+ CABAC_ENTRY(85, -7, 92, 0, 80, 11, 80, -17, 123), -+ CABAC_ENTRY(86, -5, 89, -5, 89, 5, 76, -12, 115), -+ CABAC_ENTRY(87, -7, 96, -7, 94, 2, 84, -16, 122), -+ CABAC_ENTRY(88, -13, 108, -4, 92, 5, 78, -11, 115), -+ CABAC_ENTRY(89, -3, 46, 0, 39, -6, 55, -12, 63), -+ CABAC_ENTRY(90, -1, 65, 0, 65, 4, 61, -2, 68), -+ CABAC_ENTRY(91, -1, 57, -15, 84, -14, 83, -15, 84), -+ CABAC_ENTRY(92, -9, 93, -35, 127, -37, 127, -13, 104), -+ CABAC_ENTRY(93, -3, 74, -2, 73, -5, 79, -3, 70), -+ CABAC_ENTRY(94, -9, 92, -12, 104, -11, 104, -8, 93), -+ CABAC_ENTRY(95, -8, 87, -9, 91, -11, 91, -10, 90), -+ CABAC_ENTRY(96, -23, 126, -31, 127, -30, 127, -30, 127), -+ CABAC_ENTRY(97, 5, 54, 3, 55, 0, 65, -1, 74), -+ CABAC_ENTRY(98, 6, 60, 7, 56, -2, 79, -6, 97), -+ CABAC_ENTRY(99, 6, 59, 7, 55, 0, 72, -7, 91), -+ CABAC_ENTRY(100, 6, 69, 8, 61, -4, 92, -20, 127), -+ CABAC_ENTRY(101, -1, 48, -3, 53, -6, 56, -4, 56), -+ CABAC_ENTRY(102, 0, 68, 0, 68, 3, 68, -5, 82), -+ CABAC_ENTRY(103, -4, 69, -7, 74, -8, 71, -7, 76), -+ CABAC_ENTRY(104, -8, 88, -9, 88, -13, 98, -22, 125), -+ -+ /* Table 9-19 – Values of variables m and n for ctxIdx from 105 to 165 */ -+ CABAC_ENTRY(105, -2, 85, -13, 103, -4, 86, -7, 93), -+ CABAC_ENTRY(106, -6, 78, -13, 91, -12, 88, -11, 87), -+ CABAC_ENTRY(107, -1, 75, -9, 89, -5, 82, -3, 77), -+ CABAC_ENTRY(108, -7, 77, -14, 92, -3, 72, -5, 71), -+ CABAC_ENTRY(109, 2, 54, -8, 76, -4, 67, -4, 63), -+ CABAC_ENTRY(110, 5, 50, -12, 87, -8, 72, -4, 68), -+ CABAC_ENTRY(111, -3, 68, -23, 110, -16, 89, -12, 84), -+ CABAC_ENTRY(112, 1, 50, -24, 105, -9, 69, -7, 62), -+ CABAC_ENTRY(113, 6, 42, -10, 78, -1, 59, -7, 65), -+ CABAC_ENTRY(114, -4, 81, -20, 112, 5, 66, 8, 61), -+ CABAC_ENTRY(115, 1, 63, -17, 99, 4, 57, 5, 56), -+ CABAC_ENTRY(116, -4, 70, -78, 127, -4, 71, -2, 66), -+ CABAC_ENTRY(117, 0, 67, -70, 127, -2, 71, 1, 64), -+ CABAC_ENTRY(118, 2, 57, -50, 127, 2, 58, 0, 61), -+ CABAC_ENTRY(119, -2, 76, -46, 127, -1, 74, -2, 78), -+ CABAC_ENTRY(120, 11, 35, -4, 66, -4, 44, 1, 50), -+ CABAC_ENTRY(121, 4, 64, -5, 78, -1, 69, 7, 52), -+ CABAC_ENTRY(122, 1, 61, -4, 71, 0, 62, 10, 35), -+ CABAC_ENTRY(123, 11, 35, -8, 72, -7, 51, 0, 44), -+ CABAC_ENTRY(124, 18, 25, 2, 59, -4, 47, 11, 38), -+ CABAC_ENTRY(125, 12, 24, -1, 55, -6, 42, 1, 45), -+ CABAC_ENTRY(126, 13, 29, -7, 70, -3, 41, 0, 46), -+ CABAC_ENTRY(127, 13, 36, -6, 75, -6, 53, 5, 44), -+ CABAC_ENTRY(128, -10, 93, -8, 89, 8, 76, 31, 17), -+ CABAC_ENTRY(129, -7, 73, -34, 119, -9, 78, 1, 51), -+ CABAC_ENTRY(130, -2, 73, -3, 75, -11, 83, 7, 50), -+ CABAC_ENTRY(131, 13, 46, 32, 20, 9, 52, 28, 19), -+ CABAC_ENTRY(132, 9, 49, 30, 22, 0, 67, 16, 33), -+ CABAC_ENTRY(133, -7, 100, -44, 127, -5, 90, 14, 62), -+ CABAC_ENTRY(134, 9, 53, 0, 54, 1, 67, -13, 108), -+ CABAC_ENTRY(135, 2, 53, -5, 61, -15, 72, -15, 100), -+ CABAC_ENTRY(136, 5, 53, 0, 58, -5, 75, -13, 101), -+ CABAC_ENTRY(137, -2, 61, -1, 60, -8, 80, -13, 91), -+ CABAC_ENTRY(138, 0, 56, -3, 61, -21, 83, -12, 94), -+ CABAC_ENTRY(139, 0, 56, -8, 67, -21, 64, -10, 88), -+ CABAC_ENTRY(140, -13, 63, -25, 84, -13, 31, -16, 84), -+ CABAC_ENTRY(141, -5, 60, -14, 74, -25, 64, -10, 86), -+ CABAC_ENTRY(142, -1, 62, -5, 65, -29, 94, -7, 83), -+ CABAC_ENTRY(143, 4, 57, 5, 52, 9, 75, -13, 87), -+ CABAC_ENTRY(144, -6, 69, 2, 57, 17, 63, -19, 94), -+ CABAC_ENTRY(145, 4, 57, 0, 61, -8, 74, 1, 70), -+ CABAC_ENTRY(146, 14, 39, -9, 69, -5, 35, 0, 72), -+ CABAC_ENTRY(147, 4, 51, -11, 70, -2, 27, -5, 74), -+ CABAC_ENTRY(148, 13, 68, 18, 55, 13, 91, 18, 59), -+ CABAC_ENTRY(149, 3, 64, -4, 71, 3, 65, -8, 102), -+ CABAC_ENTRY(150, 1, 61, 0, 58, -7, 69, -15, 100), -+ CABAC_ENTRY(151, 9, 63, 7, 61, 8, 77, 0, 95), -+ CABAC_ENTRY(152, 7, 50, 9, 41, -10, 66, -4, 75), -+ CABAC_ENTRY(153, 16, 39, 18, 25, 3, 62, 2, 72), -+ CABAC_ENTRY(154, 5, 44, 9, 32, -3, 68, -11, 75), -+ CABAC_ENTRY(155, 4, 52, 5, 43, -20, 81, -3, 71), -+ CABAC_ENTRY(156, 11, 48, 9, 47, 0, 30, 15, 46), -+ CABAC_ENTRY(157, -5, 60, 0, 44, 1, 7, -13, 69), -+ CABAC_ENTRY(158, -1, 59, 0, 51, -3, 23, 0, 62), -+ CABAC_ENTRY(159, 0, 59, 2, 46, -21, 74, 0, 65), -+ CABAC_ENTRY(160, 22, 33, 19, 38, 16, 66, 21, 37), -+ CABAC_ENTRY(161, 5, 44, -4, 66, -23, 124, -15, 72), -+ CABAC_ENTRY(162, 14, 43, 15, 38, 17, 37, 9, 57), -+ CABAC_ENTRY(163, -1, 78, 12, 42, 44, -18, 16, 54), -+ CABAC_ENTRY(164, 0, 60, 9, 34, 50, -34, 0, 62), -+ CABAC_ENTRY(165, 9, 69, 0, 89, -22, 127, 12, 72), -+ -+ /* Table 9-20 – Values of variables m and n for ctxIdx from 166 to 226 */ -+ CABAC_ENTRY(166, 11, 28, 4, 45, 4, 39, 24, 0), -+ CABAC_ENTRY(167, 2, 40, 10, 28, 0, 42, 15, 9), -+ CABAC_ENTRY(168, 3, 44, 10, 31, 7, 34, 8, 25), -+ CABAC_ENTRY(169, 0, 49, 33, -11, 11, 29, 13, 18), -+ CABAC_ENTRY(170, 0, 46, 52, -43, 8, 31, 15, 9), -+ CABAC_ENTRY(171, 2, 44, 18, 15, 6, 37, 13, 19), -+ CABAC_ENTRY(172, 2, 51, 28, 0, 7, 42, 10, 37), -+ CABAC_ENTRY(173, 0, 47, 35, -22, 3, 40, 12, 18), -+ CABAC_ENTRY(174, 4, 39, 38, -25, 8, 33, 6, 29), -+ CABAC_ENTRY(175, 2, 62, 34, 0, 13, 43, 20, 33), -+ CABAC_ENTRY(176, 6, 46, 39, -18, 13, 36, 15, 30), -+ CABAC_ENTRY(177, 0, 54, 32, -12, 4, 47, 4, 45), -+ CABAC_ENTRY(178, 3, 54, 102, -94, 3, 55, 1, 58), -+ CABAC_ENTRY(179, 2, 58, 0, 0, 2, 58, 0, 62), -+ CABAC_ENTRY(180, 4, 63, 56, -15, 6, 60, 7, 61), -+ CABAC_ENTRY(181, 6, 51, 33, -4, 8, 44, 12, 38), -+ CABAC_ENTRY(182, 6, 57, 29, 10, 11, 44, 11, 45), -+ CABAC_ENTRY(183, 7, 53, 37, -5, 14, 42, 15, 39), -+ CABAC_ENTRY(184, 6, 52, 51, -29, 7, 48, 11, 42), -+ CABAC_ENTRY(185, 6, 55, 39, -9, 4, 56, 13, 44), -+ CABAC_ENTRY(186, 11, 45, 52, -34, 4, 52, 16, 45), -+ CABAC_ENTRY(187, 14, 36, 69, -58, 13, 37, 12, 41), -+ CABAC_ENTRY(188, 8, 53, 67, -63, 9, 49, 10, 49), -+ CABAC_ENTRY(189, -1, 82, 44, -5, 19, 58, 30, 34), -+ CABAC_ENTRY(190, 7, 55, 32, 7, 10, 48, 18, 42), -+ CABAC_ENTRY(191, -3, 78, 55, -29, 12, 45, 10, 55), -+ CABAC_ENTRY(192, 15, 46, 32, 1, 0, 69, 17, 51), -+ CABAC_ENTRY(193, 22, 31, 0, 0, 20, 33, 17, 46), -+ CABAC_ENTRY(194, -1, 84, 27, 36, 8, 63, 0, 89), -+ CABAC_ENTRY(195, 25, 7, 33, -25, 35, -18, 26, -19), -+ CABAC_ENTRY(196, 30, -7, 34, -30, 33, -25, 22, -17), -+ CABAC_ENTRY(197, 28, 3, 36, -28, 28, -3, 26, -17), -+ CABAC_ENTRY(198, 28, 4, 38, -28, 24, 10, 30, -25), -+ CABAC_ENTRY(199, 32, 0, 38, -27, 27, 0, 28, -20), -+ CABAC_ENTRY(200, 34, -1, 34, -18, 34, -14, 33, -23), -+ CABAC_ENTRY(201, 30, 6, 35, -16, 52, -44, 37, -27), -+ CABAC_ENTRY(202, 30, 6, 34, -14, 39, -24, 33, -23), -+ CABAC_ENTRY(203, 32, 9, 32, -8, 19, 17, 40, -28), -+ CABAC_ENTRY(204, 31, 19, 37, -6, 31, 25, 38, -17), -+ CABAC_ENTRY(205, 26, 27, 35, 0, 36, 29, 33, -11), -+ CABAC_ENTRY(206, 26, 30, 30, 10, 24, 33, 40, -15), -+ CABAC_ENTRY(207, 37, 20, 28, 18, 34, 15, 41, -6), -+ CABAC_ENTRY(208, 28, 34, 26, 25, 30, 20, 38, 1), -+ CABAC_ENTRY(209, 17, 70, 29, 41, 22, 73, 41, 17), -+ CABAC_ENTRY(210, 1, 67, 0, 75, 20, 34, 30, -6), -+ CABAC_ENTRY(211, 5, 59, 2, 72, 19, 31, 27, 3), -+ CABAC_ENTRY(212, 9, 67, 8, 77, 27, 44, 26, 22), -+ CABAC_ENTRY(213, 16, 30, 14, 35, 19, 16, 37, -16), -+ CABAC_ENTRY(214, 18, 32, 18, 31, 15, 36, 35, -4), -+ CABAC_ENTRY(215, 18, 35, 17, 35, 15, 36, 38, -8), -+ CABAC_ENTRY(216, 22, 29, 21, 30, 21, 28, 38, -3), -+ CABAC_ENTRY(217, 24, 31, 17, 45, 25, 21, 37, 3), -+ CABAC_ENTRY(218, 23, 38, 20, 42, 30, 20, 38, 5), -+ CABAC_ENTRY(219, 18, 43, 18, 45, 31, 12, 42, 0), -+ CABAC_ENTRY(220, 20, 41, 27, 26, 27, 16, 35, 16), -+ CABAC_ENTRY(221, 11, 63, 16, 54, 24, 42, 39, 22), -+ CABAC_ENTRY(222, 9, 59, 7, 66, 0, 93, 14, 48), -+ CABAC_ENTRY(223, 9, 64, 16, 56, 14, 56, 27, 37), -+ CABAC_ENTRY(224, -1, 94, 11, 73, 15, 57, 21, 60), -+ CABAC_ENTRY(225, -2, 89, 10, 67, 26, 38, 12, 68), -+ CABAC_ENTRY(226, -9, 108, -10, 116, -24, 127, 2, 97), -+ -+ /* Table 9-21 – Values of variables m and n for ctxIdx from 227 to 275 */ -+ CABAC_ENTRY(227, -6, 76, -23, 112, -24, 115, -3, 71), -+ CABAC_ENTRY(228, -2, 44, -15, 71, -22, 82, -6, 42), -+ CABAC_ENTRY(229, 0, 45, -7, 61, -9, 62, -5, 50), -+ CABAC_ENTRY(230, 0, 52, 0, 53, 0, 53, -3, 54), -+ CABAC_ENTRY(231, -3, 64, -5, 66, 0, 59, -2, 62), -+ CABAC_ENTRY(232, -2, 59, -11, 77, -14, 85, 0, 58), -+ CABAC_ENTRY(233, -4, 70, -9, 80, -13, 89, 1, 63), -+ CABAC_ENTRY(234, -4, 75, -9, 84, -13, 94, -2, 72), -+ CABAC_ENTRY(235, -8, 82, -10, 87, -11, 92, -1, 74), -+ CABAC_ENTRY(236, -17, 102, -34, 127, -29, 127, -9, 91), -+ CABAC_ENTRY(237, -9, 77, -21, 101, -21, 100, -5, 67), -+ CABAC_ENTRY(238, 3, 24, -3, 39, -14, 57, -5, 27), -+ CABAC_ENTRY(239, 0, 42, -5, 53, -12, 67, -3, 39), -+ CABAC_ENTRY(240, 0, 48, -7, 61, -11, 71, -2, 44), -+ CABAC_ENTRY(241, 0, 55, -11, 75, -10, 77, 0, 46), -+ CABAC_ENTRY(242, -6, 59, -15, 77, -21, 85, -16, 64), -+ CABAC_ENTRY(243, -7, 71, -17, 91, -16, 88, -8, 68), -+ CABAC_ENTRY(244, -12, 83, -25, 107, -23, 104, -10, 78), -+ CABAC_ENTRY(245, -11, 87, -25, 111, -15, 98, -6, 77), -+ CABAC_ENTRY(246, -30, 119, -28, 122, -37, 127, -10, 86), -+ CABAC_ENTRY(247, 1, 58, -11, 76, -10, 82, -12, 92), -+ CABAC_ENTRY(248, -3, 29, -10, 44, -8, 48, -15, 55), -+ CABAC_ENTRY(249, -1, 36, -10, 52, -8, 61, -10, 60), -+ CABAC_ENTRY(250, 1, 38, -10, 57, -8, 66, -6, 62), -+ CABAC_ENTRY(251, 2, 43, -9, 58, -7, 70, -4, 65), -+ CABAC_ENTRY(252, -6, 55, -16, 72, -14, 75, -12, 73), -+ CABAC_ENTRY(253, 0, 58, -7, 69, -10, 79, -8, 76), -+ CABAC_ENTRY(254, 0, 64, -4, 69, -9, 83, -7, 80), -+ CABAC_ENTRY(255, -3, 74, -5, 74, -12, 92, -9, 88), -+ CABAC_ENTRY(256, -10, 90, -9, 86, -18, 108, -17, 110), -+ CABAC_ENTRY(257, 0, 70, 2, 66, -4, 79, -11, 97), -+ CABAC_ENTRY(258, -4, 29, -9, 34, -22, 69, -20, 84), -+ CABAC_ENTRY(259, 5, 31, 1, 32, -16, 75, -11, 79), -+ CABAC_ENTRY(260, 7, 42, 11, 31, -2, 58, -6, 73), -+ CABAC_ENTRY(261, 1, 59, 5, 52, 1, 58, -4, 74), -+ CABAC_ENTRY(262, -2, 58, -2, 55, -13, 78, -13, 86), -+ CABAC_ENTRY(263, -3, 72, -2, 67, -9, 83, -13, 96), -+ CABAC_ENTRY(264, -3, 81, 0, 73, -4, 81, -11, 97), -+ CABAC_ENTRY(265, -11, 97, -8, 89, -13, 99, -19, 117), -+ CABAC_ENTRY(266, 0, 58, 3, 52, -13, 81, -8, 78), -+ CABAC_ENTRY(267, 8, 5, 7, 4, -6, 38, -5, 33), -+ CABAC_ENTRY(268, 10, 14, 10, 8, -13, 62, -4, 48), -+ CABAC_ENTRY(269, 14, 18, 17, 8, -6, 58, -2, 53), -+ CABAC_ENTRY(270, 13, 27, 16, 19, -2, 59, -3, 62), -+ CABAC_ENTRY(271, 2, 40, 3, 37, -16, 73, -13, 71), -+ CABAC_ENTRY(272, 0, 58, -1, 61, -10, 76, -10, 79), -+ CABAC_ENTRY(273, -3, 70, -5, 73, -13, 86, -12, 86), -+ CABAC_ENTRY(274, -6, 79, -1, 70, -9, 83, -13, 90), -+ CABAC_ENTRY(275, -8, 85, -4, 78, -10, 87, -14, 97), -+ -+ /* Table 9-22 – Values of variables m and n for ctxIdx from 277 to 337 */ -+ CABAC_ENTRY(277, -13, 106, -21, 126, -22, 127, -6, 93), -+ CABAC_ENTRY(278, -16, 106, -23, 124, -25, 127, -6, 84), -+ CABAC_ENTRY(279, -10, 87, -20, 110, -25, 120, -8, 79), -+ CABAC_ENTRY(280, -21, 114, -26, 126, -27, 127, 0, 66), -+ CABAC_ENTRY(281, -18, 110, -25, 124, -19, 114, -1, 71), -+ CABAC_ENTRY(282, -14, 98, -17, 105, -23, 117, 0, 62), -+ CABAC_ENTRY(283, -22, 110, -27, 121, -25, 118, -2, 60), -+ CABAC_ENTRY(284, -21, 106, -27, 117, -26, 117, -2, 59), -+ CABAC_ENTRY(285, -18, 103, -17, 102, -24, 113, -5, 75), -+ CABAC_ENTRY(286, -21, 107, -26, 117, -28, 118, -3, 62), -+ CABAC_ENTRY(287, -23, 108, -27, 116, -31, 120, -4, 58), -+ CABAC_ENTRY(288, -26, 112, -33, 122, -37, 124, -9, 66), -+ CABAC_ENTRY(289, -10, 96, -10, 95, -10, 94, -1, 79), -+ CABAC_ENTRY(290, -12, 95, -14, 100, -15, 102, 0, 71), -+ CABAC_ENTRY(291, -5, 91, -8, 95, -10, 99, 3, 68), -+ CABAC_ENTRY(292, -9, 93, -17, 111, -13, 106, 10, 44), -+ CABAC_ENTRY(293, -22, 94, -28, 114, -50, 127, -7, 62), -+ CABAC_ENTRY(294, -5, 86, -6, 89, -5, 92, 15, 36), -+ CABAC_ENTRY(295, 9, 67, -2, 80, 17, 57, 14, 40), -+ CABAC_ENTRY(296, -4, 80, -4, 82, -5, 86, 16, 27), -+ CABAC_ENTRY(297, -10, 85, -9, 85, -13, 94, 12, 29), -+ CABAC_ENTRY(298, -1, 70, -8, 81, -12, 91, 1, 44), -+ CABAC_ENTRY(299, 7, 60, -1, 72, -2, 77, 20, 36), -+ CABAC_ENTRY(300, 9, 58, 5, 64, 0, 71, 18, 32), -+ CABAC_ENTRY(301, 5, 61, 1, 67, -1, 73, 5, 42), -+ CABAC_ENTRY(302, 12, 50, 9, 56, 4, 64, 1, 48), -+ CABAC_ENTRY(303, 15, 50, 0, 69, -7, 81, 10, 62), -+ CABAC_ENTRY(304, 18, 49, 1, 69, 5, 64, 17, 46), -+ CABAC_ENTRY(305, 17, 54, 7, 69, 15, 57, 9, 64), -+ CABAC_ENTRY(306, 10, 41, -7, 69, 1, 67, -12, 104), -+ CABAC_ENTRY(307, 7, 46, -6, 67, 0, 68, -11, 97), -+ CABAC_ENTRY(308, -1, 51, -16, 77, -10, 67, -16, 96), -+ CABAC_ENTRY(309, 7, 49, -2, 64, 1, 68, -7, 88), -+ CABAC_ENTRY(310, 8, 52, 2, 61, 0, 77, -8, 85), -+ CABAC_ENTRY(311, 9, 41, -6, 67, 2, 64, -7, 85), -+ CABAC_ENTRY(312, 6, 47, -3, 64, 0, 68, -9, 85), -+ CABAC_ENTRY(313, 2, 55, 2, 57, -5, 78, -13, 88), -+ CABAC_ENTRY(314, 13, 41, -3, 65, 7, 55, 4, 66), -+ CABAC_ENTRY(315, 10, 44, -3, 66, 5, 59, -3, 77), -+ CABAC_ENTRY(316, 6, 50, 0, 62, 2, 65, -3, 76), -+ CABAC_ENTRY(317, 5, 53, 9, 51, 14, 54, -6, 76), -+ CABAC_ENTRY(318, 13, 49, -1, 66, 15, 44, 10, 58), -+ CABAC_ENTRY(319, 4, 63, -2, 71, 5, 60, -1, 76), -+ CABAC_ENTRY(320, 6, 64, -2, 75, 2, 70, -1, 83), -+ CABAC_ENTRY(321, -2, 69, -1, 70, -2, 76, -7, 99), -+ CABAC_ENTRY(322, -2, 59, -9, 72, -18, 86, -14, 95), -+ CABAC_ENTRY(323, 6, 70, 14, 60, 12, 70, 2, 95), -+ CABAC_ENTRY(324, 10, 44, 16, 37, 5, 64, 0, 76), -+ CABAC_ENTRY(325, 9, 31, 0, 47, -12, 70, -5, 74), -+ CABAC_ENTRY(326, 12, 43, 18, 35, 11, 55, 0, 70), -+ CABAC_ENTRY(327, 3, 53, 11, 37, 5, 56, -11, 75), -+ CABAC_ENTRY(328, 14, 34, 12, 41, 0, 69, 1, 68), -+ CABAC_ENTRY(329, 10, 38, 10, 41, 2, 65, 0, 65), -+ CABAC_ENTRY(330, -3, 52, 2, 48, -6, 74, -14, 73), -+ CABAC_ENTRY(331, 13, 40, 12, 41, 5, 54, 3, 62), -+ CABAC_ENTRY(332, 17, 32, 13, 41, 7, 54, 4, 62), -+ CABAC_ENTRY(333, 7, 44, 0, 59, -6, 76, -1, 68), -+ CABAC_ENTRY(334, 7, 38, 3, 50, -11, 82, -13, 75), -+ CABAC_ENTRY(335, 13, 50, 19, 40, -2, 77, 11, 55), -+ CABAC_ENTRY(336, 10, 57, 3, 66, -2, 77, 5, 64), -+ CABAC_ENTRY(337, 26, 43, 18, 50, 25, 42, 12, 70), -+ -+ /* Table 9-23 – Values of variables m and n for ctxIdx from 338 to 398 */ -+ CABAC_ENTRY(338, 14, 11, 19, -6, 17, -13, 15, 6), -+ CABAC_ENTRY(339, 11, 14, 18, -6, 16, -9, 6, 19), -+ CABAC_ENTRY(340, 9, 11, 14, 0, 17, -12, 7, 16), -+ CABAC_ENTRY(341, 18, 11, 26, -12, 27, -21, 12, 14), -+ CABAC_ENTRY(342, 21, 9, 31, -16, 37, -30, 18, 13), -+ CABAC_ENTRY(343, 23, -2, 33, -25, 41, -40, 13, 11), -+ CABAC_ENTRY(344, 32, -15, 33, -22, 42, -41, 13, 15), -+ CABAC_ENTRY(345, 32, -15, 37, -28, 48, -47, 15, 16), -+ CABAC_ENTRY(346, 34, -21, 39, -30, 39, -32, 12, 23), -+ CABAC_ENTRY(347, 39, -23, 42, -30, 46, -40, 13, 23), -+ CABAC_ENTRY(348, 42, -33, 47, -42, 52, -51, 15, 20), -+ CABAC_ENTRY(349, 41, -31, 45, -36, 46, -41, 14, 26), -+ CABAC_ENTRY(350, 46, -28, 49, -34, 52, -39, 14, 44), -+ CABAC_ENTRY(351, 38, -12, 41, -17, 43, -19, 17, 40), -+ CABAC_ENTRY(352, 21, 29, 32, 9, 32, 11, 17, 47), -+ CABAC_ENTRY(353, 45, -24, 69, -71, 61, -55, 24, 17), -+ CABAC_ENTRY(354, 53, -45, 63, -63, 56, -46, 21, 21), -+ CABAC_ENTRY(355, 48, -26, 66, -64, 62, -50, 25, 22), -+ CABAC_ENTRY(356, 65, -43, 77, -74, 81, -67, 31, 27), -+ CABAC_ENTRY(357, 43, -19, 54, -39, 45, -20, 22, 29), -+ CABAC_ENTRY(358, 39, -10, 52, -35, 35, -2, 19, 35), -+ CABAC_ENTRY(359, 30, 9, 41, -10, 28, 15, 14, 50), -+ CABAC_ENTRY(360, 18, 26, 36, 0, 34, 1, 10, 57), -+ CABAC_ENTRY(361, 20, 27, 40, -1, 39, 1, 7, 63), -+ CABAC_ENTRY(362, 0, 57, 30, 14, 30, 17, -2, 77), -+ CABAC_ENTRY(363, -14, 82, 28, 26, 20, 38, -4, 82), -+ CABAC_ENTRY(364, -5, 75, 23, 37, 18, 45, -3, 94), -+ CABAC_ENTRY(365, -19, 97, 12, 55, 15, 54, 9, 69), -+ CABAC_ENTRY(366, -35, 125, 11, 65, 0, 79, -12, 109), -+ CABAC_ENTRY(367, 27, 0, 37, -33, 36, -16, 36, -35), -+ CABAC_ENTRY(368, 28, 0, 39, -36, 37, -14, 36, -34), -+ CABAC_ENTRY(369, 31, -4, 40, -37, 37, -17, 32, -26), -+ CABAC_ENTRY(370, 27, 6, 38, -30, 32, 1, 37, -30), -+ CABAC_ENTRY(371, 34, 8, 46, -33, 34, 15, 44, -32), -+ CABAC_ENTRY(372, 30, 10, 42, -30, 29, 15, 34, -18), -+ CABAC_ENTRY(373, 24, 22, 40, -24, 24, 25, 34, -15), -+ CABAC_ENTRY(374, 33, 19, 49, -29, 34, 22, 40, -15), -+ CABAC_ENTRY(375, 22, 32, 38, -12, 31, 16, 33, -7), -+ CABAC_ENTRY(376, 26, 31, 40, -10, 35, 18, 35, -5), -+ CABAC_ENTRY(377, 21, 41, 38, -3, 31, 28, 33, 0), -+ CABAC_ENTRY(378, 26, 44, 46, -5, 33, 41, 38, 2), -+ CABAC_ENTRY(379, 23, 47, 31, 20, 36, 28, 33, 13), -+ CABAC_ENTRY(380, 16, 65, 29, 30, 27, 47, 23, 35), -+ CABAC_ENTRY(381, 14, 71, 25, 44, 21, 62, 13, 58), -+ CABAC_ENTRY(382, 8, 60, 12, 48, 18, 31, 29, -3), -+ CABAC_ENTRY(383, 6, 63, 11, 49, 19, 26, 26, 0), -+ CABAC_ENTRY(384, 17, 65, 26, 45, 36, 24, 22, 30), -+ CABAC_ENTRY(385, 21, 24, 22, 22, 24, 23, 31, -7), -+ CABAC_ENTRY(386, 23, 20, 23, 22, 27, 16, 35, -15), -+ CABAC_ENTRY(387, 26, 23, 27, 21, 24, 30, 34, -3), -+ CABAC_ENTRY(388, 27, 32, 33, 20, 31, 29, 34, 3), -+ CABAC_ENTRY(389, 28, 23, 26, 28, 22, 41, 36, -1), -+ CABAC_ENTRY(390, 28, 24, 30, 24, 22, 42, 34, 5), -+ CABAC_ENTRY(391, 23, 40, 27, 34, 16, 60, 32, 11), -+ CABAC_ENTRY(392, 24, 32, 18, 42, 15, 52, 35, 5), -+ CABAC_ENTRY(393, 28, 29, 25, 39, 14, 60, 34, 12), -+ CABAC_ENTRY(394, 23, 42, 18, 50, 3, 78, 39, 11), -+ CABAC_ENTRY(395, 19, 57, 12, 70, -16, 123, 30, 29), -+ CABAC_ENTRY(396, 22, 53, 21, 54, 21, 53, 34, 26), -+ CABAC_ENTRY(397, 22, 61, 14, 71, 22, 56, 29, 39), -+ CABAC_ENTRY(398, 11, 86, 11, 83, 25, 61, 19, 66), -+ -+ /* Values of variables m and n for ctxIdx from 399 to 463 (not documented) */ -+ CABAC_ENTRY(399, 12, 40, 25, 32, 21, 33, 31, 21), -+ CABAC_ENTRY(400, 11, 51, 21, 49, 19, 50, 31, 31), -+ CABAC_ENTRY(401, 14, 59, 21, 54, 17, 61, 25, 50), -+ CABAC_ENTRY(402, -4, 79, -5, 85, -3, 78, -17, 120), -+ CABAC_ENTRY(403, -7, 71, -6, 81, -8, 74, -20, 112), -+ CABAC_ENTRY(404, -5, 69, -10, 77, -9, 72, -18, 114), -+ CABAC_ENTRY(405, -9, 70, -7, 81, -10, 72, -11, 85), -+ CABAC_ENTRY(406, -8, 66, -17, 80, -18, 75, -15, 92), -+ CABAC_ENTRY(407, -10, 68, -18, 73, -12, 71, -14, 89), -+ CABAC_ENTRY(408, -19, 73, -4, 74, -11, 63, -26, 71), -+ CABAC_ENTRY(409, -12, 69, -10, 83, -5, 70, -15, 81), -+ CABAC_ENTRY(410, -16, 70, -9, 71, -17, 75, -14, 80), -+ CABAC_ENTRY(411, -15, 67, -9, 67, -14, 72, 0, 68), -+ CABAC_ENTRY(412, -20, 62, -1, 61, -16, 67, -14, 70), -+ CABAC_ENTRY(413, -19, 70, -8, 66, -8, 53, -24, 56), -+ CABAC_ENTRY(414, -16, 66, -14, 66, -14, 59, -23, 68), -+ CABAC_ENTRY(415, -22, 65, 0, 59, -9, 52, -24, 50), -+ CABAC_ENTRY(416, -20, 63, 2, 59, -11, 68, -11, 74), -+ CABAC_ENTRY(417, 9, -2, 17, -10, 9, -2, 23, -13), -+ CABAC_ENTRY(418, 26, -9, 32, -13, 30, -10, 26, -13), -+ CABAC_ENTRY(419, 33, -9, 42, -9, 31, -4, 40, -15), -+ CABAC_ENTRY(420, 39, -7, 49, -5, 33, -1, 49, -14), -+ CABAC_ENTRY(421, 41, -2, 53, 0, 33, 7, 44, 3), -+ CABAC_ENTRY(422, 45, 3, 64, 3, 31, 12, 45, 6), -+ CABAC_ENTRY(423, 49, 9, 68, 10, 37, 23, 44, 34), -+ CABAC_ENTRY(424, 45, 27, 66, 27, 31, 38, 33, 54), -+ CABAC_ENTRY(425, 36, 59, 47, 57, 20, 64, 19, 82), -+ CABAC_ENTRY(426, -6, 66, -5, 71, -9, 71, -3, 75), -+ CABAC_ENTRY(427, -7, 35, 0, 24, -7, 37, -1, 23), -+ CABAC_ENTRY(428, -7, 42, -1, 36, -8, 44, 1, 34), -+ CABAC_ENTRY(429, -8, 45, -2, 42, -11, 49, 1, 43), -+ CABAC_ENTRY(430, -5, 48, -2, 52, -10, 56, 0, 54), -+ CABAC_ENTRY(431, -12, 56, -9, 57, -12, 59, -2, 55), -+ CABAC_ENTRY(432, -6, 60, -6, 63, -8, 63, 0, 61), -+ CABAC_ENTRY(433, -5, 62, -4, 65, -9, 67, 1, 64), -+ CABAC_ENTRY(434, -8, 66, -4, 67, -6, 68, 0, 68), -+ CABAC_ENTRY(435, -8, 76, -7, 82, -10, 79, -9, 92), -+ CABAC_ENTRY(436, -5, 85, -3, 81, -3, 78, -14, 106), -+ CABAC_ENTRY(437, -6, 81, -3, 76, -8, 74, -13, 97), -+ CABAC_ENTRY(438, -10, 77, -7, 72, -9, 72, -15, 90), -+ CABAC_ENTRY(439, -7, 81, -6, 78, -10, 72, -12, 90), -+ CABAC_ENTRY(440, -17, 80, -12, 72, -18, 75, -18, 88), -+ CABAC_ENTRY(441, -18, 73, -14, 68, -12, 71, -10, 73), -+ CABAC_ENTRY(442, -4, 74, -3, 70, -11, 63, -9, 79), -+ CABAC_ENTRY(443, -10, 83, -6, 76, -5, 70, -14, 86), -+ CABAC_ENTRY(444, -9, 71, -5, 66, -17, 75, -10, 73), -+ CABAC_ENTRY(445, -9, 67, -5, 62, -14, 72, -10, 70), -+ CABAC_ENTRY(446, -1, 61, 0, 57, -16, 67, -10, 69), -+ CABAC_ENTRY(447, -8, 66, -4, 61, -8, 53, -5, 66), -+ CABAC_ENTRY(448, -14, 66, -9, 60, -14, 59, -9, 64), -+ CABAC_ENTRY(449, 0, 59, 1, 54, -9, 52, -5, 58), -+ CABAC_ENTRY(450, 2, 59, 2, 58, -11, 68, 2, 59), -+ CABAC_ENTRY(451, 21, -13, 17, -10, 9, -2, 21, -10), -+ CABAC_ENTRY(452, 33, -14, 32, -13, 30, -10, 24, -11), -+ CABAC_ENTRY(453, 39, -7, 42, -9, 31, -4, 28, -8), -+ CABAC_ENTRY(454, 46, -2, 49, -5, 33, -1, 28, -1), -+ CABAC_ENTRY(455, 51, 2, 53, 0, 33, 7, 29, 3), -+ CABAC_ENTRY(456, 60, 6, 64, 3, 31, 12, 29, 9), -+ CABAC_ENTRY(457, 61, 17, 68, 10, 37, 23, 35, 20), -+ CABAC_ENTRY(458, 55, 34, 66, 27, 31, 38, 29, 36), -+ CABAC_ENTRY(459, 42, 62, 47, 57, 20, 64, 14, 67), -+}; -+ -+#define RKV_HEVC_CABAC_TABLE_SIZE 27456 -+ -+const u8 rkvdec_hevc_cabac_table[RKV_HEVC_CABAC_TABLE_SIZE] = { - 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, - 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, - 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -@@ -15,6 +15,8 @@ - #include "rkvdec.h" - #include "rkvdec-regs.h" - -+extern const s8 rkvdec_h264_cabac_table[4][464][2]; -+ - /* Size with u32 units. */ - #define RKV_CABAC_INIT_BUFFER_SIZE (3680 + 128) - #define RKV_RPS_SIZE ((128 + 128) / 4) -@@ -118,505 +120,6 @@ struct rkvdec_h264_ctx { - struct rkvdec_regs regs; - }; - --#define CABAC_ENTRY(ctxidx, idc0_m, idc0_n, idc1_m, idc1_n, \ -- idc2_m, idc2_n, intra_m, intra_n) \ -- [0][(ctxidx)] = {idc0_m, idc0_n}, \ -- [1][(ctxidx)] = {idc1_m, idc1_n}, \ -- [2][(ctxidx)] = {idc2_m, idc2_n}, \ -- [3][(ctxidx)] = {intra_m, intra_n} -- --/* -- * Constant CABAC table. -- * Built from the tables described in section '9.3.1.1 Initialisation process -- * for context variables' of the H264 spec. -- */ --static const s8 rkvdec_h264_cabac_table[4][464][2] = { -- /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */ -- CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15), -- CABAC_ENTRY(1, 2, 54, 2, 54, 2, 54, 2, 54), -- CABAC_ENTRY(2, 3, 74, 3, 74, 3, 74, 3, 74), -- CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15), -- CABAC_ENTRY(4, 2, 54, 2, 54, 2, 54, 2, 54), -- CABAC_ENTRY(5, 3, 74, 3, 74, 3, 74, 3, 74), -- CABAC_ENTRY(6, -28, 127, -28, 127, -28, 127, -28, 127), -- CABAC_ENTRY(7, -23, 104, -23, 104, -23, 104, -23, 104), -- CABAC_ENTRY(8, -6, 53, -6, 53, -6, 53, -6, 53), -- CABAC_ENTRY(9, -1, 54, -1, 54, -1, 54, -1, 54), -- CABAC_ENTRY(10, 7, 51, 7, 51, 7, 51, 7, 51), -- -- /* Table 9-13 – Values of variables m and n for ctxIdx from 11 to 23 */ -- CABAC_ENTRY(11, 23, 33, 22, 25, 29, 16, 0, 0), -- CABAC_ENTRY(12, 23, 2, 34, 0, 25, 0, 0, 0), -- CABAC_ENTRY(13, 21, 0, 16, 0, 14, 0, 0, 0), -- CABAC_ENTRY(14, 1, 9, -2, 9, -10, 51, 0, 0), -- CABAC_ENTRY(15, 0, 49, 4, 41, -3, 62, 0, 0), -- CABAC_ENTRY(16, -37, 118, -29, 118, -27, 99, 0, 0), -- CABAC_ENTRY(17, 5, 57, 2, 65, 26, 16, 0, 0), -- CABAC_ENTRY(18, -13, 78, -6, 71, -4, 85, 0, 0), -- CABAC_ENTRY(19, -11, 65, -13, 79, -24, 102, 0, 0), -- CABAC_ENTRY(20, 1, 62, 5, 52, 5, 57, 0, 0), -- CABAC_ENTRY(21, 12, 49, 9, 50, 6, 57, 0, 0), -- CABAC_ENTRY(22, -4, 73, -3, 70, -17, 73, 0, 0), -- CABAC_ENTRY(23, 17, 50, 10, 54, 14, 57, 0, 0), -- -- /* Table 9-14 – Values of variables m and n for ctxIdx from 24 to 39 */ -- CABAC_ENTRY(24, 18, 64, 26, 34, 20, 40, 0, 0), -- CABAC_ENTRY(25, 9, 43, 19, 22, 20, 10, 0, 0), -- CABAC_ENTRY(26, 29, 0, 40, 0, 29, 0, 0, 0), -- CABAC_ENTRY(27, 26, 67, 57, 2, 54, 0, 0, 0), -- CABAC_ENTRY(28, 16, 90, 41, 36, 37, 42, 0, 0), -- CABAC_ENTRY(29, 9, 104, 26, 69, 12, 97, 0, 0), -- CABAC_ENTRY(30, -46, 127, -45, 127, -32, 127, 0, 0), -- CABAC_ENTRY(31, -20, 104, -15, 101, -22, 117, 0, 0), -- CABAC_ENTRY(32, 1, 67, -4, 76, -2, 74, 0, 0), -- CABAC_ENTRY(33, -13, 78, -6, 71, -4, 85, 0, 0), -- CABAC_ENTRY(34, -11, 65, -13, 79, -24, 102, 0, 0), -- CABAC_ENTRY(35, 1, 62, 5, 52, 5, 57, 0, 0), -- CABAC_ENTRY(36, -6, 86, 6, 69, -6, 93, 0, 0), -- CABAC_ENTRY(37, -17, 95, -13, 90, -14, 88, 0, 0), -- CABAC_ENTRY(38, -6, 61, 0, 52, -6, 44, 0, 0), -- CABAC_ENTRY(39, 9, 45, 8, 43, 4, 55, 0, 0), -- -- /* Table 9-15 – Values of variables m and n for ctxIdx from 40 to 53 */ -- CABAC_ENTRY(40, -3, 69, -2, 69, -11, 89, 0, 0), -- CABAC_ENTRY(41, -6, 81, -5, 82, -15, 103, 0, 0), -- CABAC_ENTRY(42, -11, 96, -10, 96, -21, 116, 0, 0), -- CABAC_ENTRY(43, 6, 55, 2, 59, 19, 57, 0, 0), -- CABAC_ENTRY(44, 7, 67, 2, 75, 20, 58, 0, 0), -- CABAC_ENTRY(45, -5, 86, -3, 87, 4, 84, 0, 0), -- CABAC_ENTRY(46, 2, 88, -3, 100, 6, 96, 0, 0), -- CABAC_ENTRY(47, 0, 58, 1, 56, 1, 63, 0, 0), -- CABAC_ENTRY(48, -3, 76, -3, 74, -5, 85, 0, 0), -- CABAC_ENTRY(49, -10, 94, -6, 85, -13, 106, 0, 0), -- CABAC_ENTRY(50, 5, 54, 0, 59, 5, 63, 0, 0), -- CABAC_ENTRY(51, 4, 69, -3, 81, 6, 75, 0, 0), -- CABAC_ENTRY(52, -3, 81, -7, 86, -3, 90, 0, 0), -- CABAC_ENTRY(53, 0, 88, -5, 95, -1, 101, 0, 0), -- -- /* Table 9-16 – Values of variables m and n for ctxIdx from 54 to 59 */ -- CABAC_ENTRY(54, -7, 67, -1, 66, 3, 55, 0, 0), -- CABAC_ENTRY(55, -5, 74, -1, 77, -4, 79, 0, 0), -- CABAC_ENTRY(56, -4, 74, 1, 70, -2, 75, 0, 0), -- CABAC_ENTRY(57, -5, 80, -2, 86, -12, 97, 0, 0), -- CABAC_ENTRY(58, -7, 72, -5, 72, -7, 50, 0, 0), -- CABAC_ENTRY(59, 1, 58, 0, 61, 1, 60, 0, 0), -- -- /* Table 9-17 – Values of variables m and n for ctxIdx from 60 to 69 */ -- CABAC_ENTRY(60, 0, 41, 0, 41, 0, 41, 0, 41), -- CABAC_ENTRY(61, 0, 63, 0, 63, 0, 63, 0, 63), -- CABAC_ENTRY(62, 0, 63, 0, 63, 0, 63, 0, 63), -- CABAC_ENTRY(63, 0, 63, 0, 63, 0, 63, 0, 63), -- CABAC_ENTRY(64, -9, 83, -9, 83, -9, 83, -9, 83), -- CABAC_ENTRY(65, 4, 86, 4, 86, 4, 86, 4, 86), -- CABAC_ENTRY(66, 0, 97, 0, 97, 0, 97, 0, 97), -- CABAC_ENTRY(67, -7, 72, -7, 72, -7, 72, -7, 72), -- CABAC_ENTRY(68, 13, 41, 13, 41, 13, 41, 13, 41), -- CABAC_ENTRY(69, 3, 62, 3, 62, 3, 62, 3, 62), -- -- /* Table 9-18 – Values of variables m and n for ctxIdx from 70 to 104 */ -- CABAC_ENTRY(70, 0, 45, 13, 15, 7, 34, 0, 11), -- CABAC_ENTRY(71, -4, 78, 7, 51, -9, 88, 1, 55), -- CABAC_ENTRY(72, -3, 96, 2, 80, -20, 127, 0, 69), -- CABAC_ENTRY(73, -27, 126, -39, 127, -36, 127, -17, 127), -- CABAC_ENTRY(74, -28, 98, -18, 91, -17, 91, -13, 102), -- CABAC_ENTRY(75, -25, 101, -17, 96, -14, 95, 0, 82), -- CABAC_ENTRY(76, -23, 67, -26, 81, -25, 84, -7, 74), -- CABAC_ENTRY(77, -28, 82, -35, 98, -25, 86, -21, 107), -- CABAC_ENTRY(78, -20, 94, -24, 102, -12, 89, -27, 127), -- CABAC_ENTRY(79, -16, 83, -23, 97, -17, 91, -31, 127), -- CABAC_ENTRY(80, -22, 110, -27, 119, -31, 127, -24, 127), -- CABAC_ENTRY(81, -21, 91, -24, 99, -14, 76, -18, 95), -- CABAC_ENTRY(82, -18, 102, -21, 110, -18, 103, -27, 127), -- CABAC_ENTRY(83, -13, 93, -18, 102, -13, 90, -21, 114), -- CABAC_ENTRY(84, -29, 127, -36, 127, -37, 127, -30, 127), -- CABAC_ENTRY(85, -7, 92, 0, 80, 11, 80, -17, 123), -- CABAC_ENTRY(86, -5, 89, -5, 89, 5, 76, -12, 115), -- CABAC_ENTRY(87, -7, 96, -7, 94, 2, 84, -16, 122), -- CABAC_ENTRY(88, -13, 108, -4, 92, 5, 78, -11, 115), -- CABAC_ENTRY(89, -3, 46, 0, 39, -6, 55, -12, 63), -- CABAC_ENTRY(90, -1, 65, 0, 65, 4, 61, -2, 68), -- CABAC_ENTRY(91, -1, 57, -15, 84, -14, 83, -15, 84), -- CABAC_ENTRY(92, -9, 93, -35, 127, -37, 127, -13, 104), -- CABAC_ENTRY(93, -3, 74, -2, 73, -5, 79, -3, 70), -- CABAC_ENTRY(94, -9, 92, -12, 104, -11, 104, -8, 93), -- CABAC_ENTRY(95, -8, 87, -9, 91, -11, 91, -10, 90), -- CABAC_ENTRY(96, -23, 126, -31, 127, -30, 127, -30, 127), -- CABAC_ENTRY(97, 5, 54, 3, 55, 0, 65, -1, 74), -- CABAC_ENTRY(98, 6, 60, 7, 56, -2, 79, -6, 97), -- CABAC_ENTRY(99, 6, 59, 7, 55, 0, 72, -7, 91), -- CABAC_ENTRY(100, 6, 69, 8, 61, -4, 92, -20, 127), -- CABAC_ENTRY(101, -1, 48, -3, 53, -6, 56, -4, 56), -- CABAC_ENTRY(102, 0, 68, 0, 68, 3, 68, -5, 82), -- CABAC_ENTRY(103, -4, 69, -7, 74, -8, 71, -7, 76), -- CABAC_ENTRY(104, -8, 88, -9, 88, -13, 98, -22, 125), -- -- /* Table 9-19 – Values of variables m and n for ctxIdx from 105 to 165 */ -- CABAC_ENTRY(105, -2, 85, -13, 103, -4, 86, -7, 93), -- CABAC_ENTRY(106, -6, 78, -13, 91, -12, 88, -11, 87), -- CABAC_ENTRY(107, -1, 75, -9, 89, -5, 82, -3, 77), -- CABAC_ENTRY(108, -7, 77, -14, 92, -3, 72, -5, 71), -- CABAC_ENTRY(109, 2, 54, -8, 76, -4, 67, -4, 63), -- CABAC_ENTRY(110, 5, 50, -12, 87, -8, 72, -4, 68), -- CABAC_ENTRY(111, -3, 68, -23, 110, -16, 89, -12, 84), -- CABAC_ENTRY(112, 1, 50, -24, 105, -9, 69, -7, 62), -- CABAC_ENTRY(113, 6, 42, -10, 78, -1, 59, -7, 65), -- CABAC_ENTRY(114, -4, 81, -20, 112, 5, 66, 8, 61), -- CABAC_ENTRY(115, 1, 63, -17, 99, 4, 57, 5, 56), -- CABAC_ENTRY(116, -4, 70, -78, 127, -4, 71, -2, 66), -- CABAC_ENTRY(117, 0, 67, -70, 127, -2, 71, 1, 64), -- CABAC_ENTRY(118, 2, 57, -50, 127, 2, 58, 0, 61), -- CABAC_ENTRY(119, -2, 76, -46, 127, -1, 74, -2, 78), -- CABAC_ENTRY(120, 11, 35, -4, 66, -4, 44, 1, 50), -- CABAC_ENTRY(121, 4, 64, -5, 78, -1, 69, 7, 52), -- CABAC_ENTRY(122, 1, 61, -4, 71, 0, 62, 10, 35), -- CABAC_ENTRY(123, 11, 35, -8, 72, -7, 51, 0, 44), -- CABAC_ENTRY(124, 18, 25, 2, 59, -4, 47, 11, 38), -- CABAC_ENTRY(125, 12, 24, -1, 55, -6, 42, 1, 45), -- CABAC_ENTRY(126, 13, 29, -7, 70, -3, 41, 0, 46), -- CABAC_ENTRY(127, 13, 36, -6, 75, -6, 53, 5, 44), -- CABAC_ENTRY(128, -10, 93, -8, 89, 8, 76, 31, 17), -- CABAC_ENTRY(129, -7, 73, -34, 119, -9, 78, 1, 51), -- CABAC_ENTRY(130, -2, 73, -3, 75, -11, 83, 7, 50), -- CABAC_ENTRY(131, 13, 46, 32, 20, 9, 52, 28, 19), -- CABAC_ENTRY(132, 9, 49, 30, 22, 0, 67, 16, 33), -- CABAC_ENTRY(133, -7, 100, -44, 127, -5, 90, 14, 62), -- CABAC_ENTRY(134, 9, 53, 0, 54, 1, 67, -13, 108), -- CABAC_ENTRY(135, 2, 53, -5, 61, -15, 72, -15, 100), -- CABAC_ENTRY(136, 5, 53, 0, 58, -5, 75, -13, 101), -- CABAC_ENTRY(137, -2, 61, -1, 60, -8, 80, -13, 91), -- CABAC_ENTRY(138, 0, 56, -3, 61, -21, 83, -12, 94), -- CABAC_ENTRY(139, 0, 56, -8, 67, -21, 64, -10, 88), -- CABAC_ENTRY(140, -13, 63, -25, 84, -13, 31, -16, 84), -- CABAC_ENTRY(141, -5, 60, -14, 74, -25, 64, -10, 86), -- CABAC_ENTRY(142, -1, 62, -5, 65, -29, 94, -7, 83), -- CABAC_ENTRY(143, 4, 57, 5, 52, 9, 75, -13, 87), -- CABAC_ENTRY(144, -6, 69, 2, 57, 17, 63, -19, 94), -- CABAC_ENTRY(145, 4, 57, 0, 61, -8, 74, 1, 70), -- CABAC_ENTRY(146, 14, 39, -9, 69, -5, 35, 0, 72), -- CABAC_ENTRY(147, 4, 51, -11, 70, -2, 27, -5, 74), -- CABAC_ENTRY(148, 13, 68, 18, 55, 13, 91, 18, 59), -- CABAC_ENTRY(149, 3, 64, -4, 71, 3, 65, -8, 102), -- CABAC_ENTRY(150, 1, 61, 0, 58, -7, 69, -15, 100), -- CABAC_ENTRY(151, 9, 63, 7, 61, 8, 77, 0, 95), -- CABAC_ENTRY(152, 7, 50, 9, 41, -10, 66, -4, 75), -- CABAC_ENTRY(153, 16, 39, 18, 25, 3, 62, 2, 72), -- CABAC_ENTRY(154, 5, 44, 9, 32, -3, 68, -11, 75), -- CABAC_ENTRY(155, 4, 52, 5, 43, -20, 81, -3, 71), -- CABAC_ENTRY(156, 11, 48, 9, 47, 0, 30, 15, 46), -- CABAC_ENTRY(157, -5, 60, 0, 44, 1, 7, -13, 69), -- CABAC_ENTRY(158, -1, 59, 0, 51, -3, 23, 0, 62), -- CABAC_ENTRY(159, 0, 59, 2, 46, -21, 74, 0, 65), -- CABAC_ENTRY(160, 22, 33, 19, 38, 16, 66, 21, 37), -- CABAC_ENTRY(161, 5, 44, -4, 66, -23, 124, -15, 72), -- CABAC_ENTRY(162, 14, 43, 15, 38, 17, 37, 9, 57), -- CABAC_ENTRY(163, -1, 78, 12, 42, 44, -18, 16, 54), -- CABAC_ENTRY(164, 0, 60, 9, 34, 50, -34, 0, 62), -- CABAC_ENTRY(165, 9, 69, 0, 89, -22, 127, 12, 72), -- -- /* Table 9-20 – Values of variables m and n for ctxIdx from 166 to 226 */ -- CABAC_ENTRY(166, 11, 28, 4, 45, 4, 39, 24, 0), -- CABAC_ENTRY(167, 2, 40, 10, 28, 0, 42, 15, 9), -- CABAC_ENTRY(168, 3, 44, 10, 31, 7, 34, 8, 25), -- CABAC_ENTRY(169, 0, 49, 33, -11, 11, 29, 13, 18), -- CABAC_ENTRY(170, 0, 46, 52, -43, 8, 31, 15, 9), -- CABAC_ENTRY(171, 2, 44, 18, 15, 6, 37, 13, 19), -- CABAC_ENTRY(172, 2, 51, 28, 0, 7, 42, 10, 37), -- CABAC_ENTRY(173, 0, 47, 35, -22, 3, 40, 12, 18), -- CABAC_ENTRY(174, 4, 39, 38, -25, 8, 33, 6, 29), -- CABAC_ENTRY(175, 2, 62, 34, 0, 13, 43, 20, 33), -- CABAC_ENTRY(176, 6, 46, 39, -18, 13, 36, 15, 30), -- CABAC_ENTRY(177, 0, 54, 32, -12, 4, 47, 4, 45), -- CABAC_ENTRY(178, 3, 54, 102, -94, 3, 55, 1, 58), -- CABAC_ENTRY(179, 2, 58, 0, 0, 2, 58, 0, 62), -- CABAC_ENTRY(180, 4, 63, 56, -15, 6, 60, 7, 61), -- CABAC_ENTRY(181, 6, 51, 33, -4, 8, 44, 12, 38), -- CABAC_ENTRY(182, 6, 57, 29, 10, 11, 44, 11, 45), -- CABAC_ENTRY(183, 7, 53, 37, -5, 14, 42, 15, 39), -- CABAC_ENTRY(184, 6, 52, 51, -29, 7, 48, 11, 42), -- CABAC_ENTRY(185, 6, 55, 39, -9, 4, 56, 13, 44), -- CABAC_ENTRY(186, 11, 45, 52, -34, 4, 52, 16, 45), -- CABAC_ENTRY(187, 14, 36, 69, -58, 13, 37, 12, 41), -- CABAC_ENTRY(188, 8, 53, 67, -63, 9, 49, 10, 49), -- CABAC_ENTRY(189, -1, 82, 44, -5, 19, 58, 30, 34), -- CABAC_ENTRY(190, 7, 55, 32, 7, 10, 48, 18, 42), -- CABAC_ENTRY(191, -3, 78, 55, -29, 12, 45, 10, 55), -- CABAC_ENTRY(192, 15, 46, 32, 1, 0, 69, 17, 51), -- CABAC_ENTRY(193, 22, 31, 0, 0, 20, 33, 17, 46), -- CABAC_ENTRY(194, -1, 84, 27, 36, 8, 63, 0, 89), -- CABAC_ENTRY(195, 25, 7, 33, -25, 35, -18, 26, -19), -- CABAC_ENTRY(196, 30, -7, 34, -30, 33, -25, 22, -17), -- CABAC_ENTRY(197, 28, 3, 36, -28, 28, -3, 26, -17), -- CABAC_ENTRY(198, 28, 4, 38, -28, 24, 10, 30, -25), -- CABAC_ENTRY(199, 32, 0, 38, -27, 27, 0, 28, -20), -- CABAC_ENTRY(200, 34, -1, 34, -18, 34, -14, 33, -23), -- CABAC_ENTRY(201, 30, 6, 35, -16, 52, -44, 37, -27), -- CABAC_ENTRY(202, 30, 6, 34, -14, 39, -24, 33, -23), -- CABAC_ENTRY(203, 32, 9, 32, -8, 19, 17, 40, -28), -- CABAC_ENTRY(204, 31, 19, 37, -6, 31, 25, 38, -17), -- CABAC_ENTRY(205, 26, 27, 35, 0, 36, 29, 33, -11), -- CABAC_ENTRY(206, 26, 30, 30, 10, 24, 33, 40, -15), -- CABAC_ENTRY(207, 37, 20, 28, 18, 34, 15, 41, -6), -- CABAC_ENTRY(208, 28, 34, 26, 25, 30, 20, 38, 1), -- CABAC_ENTRY(209, 17, 70, 29, 41, 22, 73, 41, 17), -- CABAC_ENTRY(210, 1, 67, 0, 75, 20, 34, 30, -6), -- CABAC_ENTRY(211, 5, 59, 2, 72, 19, 31, 27, 3), -- CABAC_ENTRY(212, 9, 67, 8, 77, 27, 44, 26, 22), -- CABAC_ENTRY(213, 16, 30, 14, 35, 19, 16, 37, -16), -- CABAC_ENTRY(214, 18, 32, 18, 31, 15, 36, 35, -4), -- CABAC_ENTRY(215, 18, 35, 17, 35, 15, 36, 38, -8), -- CABAC_ENTRY(216, 22, 29, 21, 30, 21, 28, 38, -3), -- CABAC_ENTRY(217, 24, 31, 17, 45, 25, 21, 37, 3), -- CABAC_ENTRY(218, 23, 38, 20, 42, 30, 20, 38, 5), -- CABAC_ENTRY(219, 18, 43, 18, 45, 31, 12, 42, 0), -- CABAC_ENTRY(220, 20, 41, 27, 26, 27, 16, 35, 16), -- CABAC_ENTRY(221, 11, 63, 16, 54, 24, 42, 39, 22), -- CABAC_ENTRY(222, 9, 59, 7, 66, 0, 93, 14, 48), -- CABAC_ENTRY(223, 9, 64, 16, 56, 14, 56, 27, 37), -- CABAC_ENTRY(224, -1, 94, 11, 73, 15, 57, 21, 60), -- CABAC_ENTRY(225, -2, 89, 10, 67, 26, 38, 12, 68), -- CABAC_ENTRY(226, -9, 108, -10, 116, -24, 127, 2, 97), -- -- /* Table 9-21 – Values of variables m and n for ctxIdx from 227 to 275 */ -- CABAC_ENTRY(227, -6, 76, -23, 112, -24, 115, -3, 71), -- CABAC_ENTRY(228, -2, 44, -15, 71, -22, 82, -6, 42), -- CABAC_ENTRY(229, 0, 45, -7, 61, -9, 62, -5, 50), -- CABAC_ENTRY(230, 0, 52, 0, 53, 0, 53, -3, 54), -- CABAC_ENTRY(231, -3, 64, -5, 66, 0, 59, -2, 62), -- CABAC_ENTRY(232, -2, 59, -11, 77, -14, 85, 0, 58), -- CABAC_ENTRY(233, -4, 70, -9, 80, -13, 89, 1, 63), -- CABAC_ENTRY(234, -4, 75, -9, 84, -13, 94, -2, 72), -- CABAC_ENTRY(235, -8, 82, -10, 87, -11, 92, -1, 74), -- CABAC_ENTRY(236, -17, 102, -34, 127, -29, 127, -9, 91), -- CABAC_ENTRY(237, -9, 77, -21, 101, -21, 100, -5, 67), -- CABAC_ENTRY(238, 3, 24, -3, 39, -14, 57, -5, 27), -- CABAC_ENTRY(239, 0, 42, -5, 53, -12, 67, -3, 39), -- CABAC_ENTRY(240, 0, 48, -7, 61, -11, 71, -2, 44), -- CABAC_ENTRY(241, 0, 55, -11, 75, -10, 77, 0, 46), -- CABAC_ENTRY(242, -6, 59, -15, 77, -21, 85, -16, 64), -- CABAC_ENTRY(243, -7, 71, -17, 91, -16, 88, -8, 68), -- CABAC_ENTRY(244, -12, 83, -25, 107, -23, 104, -10, 78), -- CABAC_ENTRY(245, -11, 87, -25, 111, -15, 98, -6, 77), -- CABAC_ENTRY(246, -30, 119, -28, 122, -37, 127, -10, 86), -- CABAC_ENTRY(247, 1, 58, -11, 76, -10, 82, -12, 92), -- CABAC_ENTRY(248, -3, 29, -10, 44, -8, 48, -15, 55), -- CABAC_ENTRY(249, -1, 36, -10, 52, -8, 61, -10, 60), -- CABAC_ENTRY(250, 1, 38, -10, 57, -8, 66, -6, 62), -- CABAC_ENTRY(251, 2, 43, -9, 58, -7, 70, -4, 65), -- CABAC_ENTRY(252, -6, 55, -16, 72, -14, 75, -12, 73), -- CABAC_ENTRY(253, 0, 58, -7, 69, -10, 79, -8, 76), -- CABAC_ENTRY(254, 0, 64, -4, 69, -9, 83, -7, 80), -- CABAC_ENTRY(255, -3, 74, -5, 74, -12, 92, -9, 88), -- CABAC_ENTRY(256, -10, 90, -9, 86, -18, 108, -17, 110), -- CABAC_ENTRY(257, 0, 70, 2, 66, -4, 79, -11, 97), -- CABAC_ENTRY(258, -4, 29, -9, 34, -22, 69, -20, 84), -- CABAC_ENTRY(259, 5, 31, 1, 32, -16, 75, -11, 79), -- CABAC_ENTRY(260, 7, 42, 11, 31, -2, 58, -6, 73), -- CABAC_ENTRY(261, 1, 59, 5, 52, 1, 58, -4, 74), -- CABAC_ENTRY(262, -2, 58, -2, 55, -13, 78, -13, 86), -- CABAC_ENTRY(263, -3, 72, -2, 67, -9, 83, -13, 96), -- CABAC_ENTRY(264, -3, 81, 0, 73, -4, 81, -11, 97), -- CABAC_ENTRY(265, -11, 97, -8, 89, -13, 99, -19, 117), -- CABAC_ENTRY(266, 0, 58, 3, 52, -13, 81, -8, 78), -- CABAC_ENTRY(267, 8, 5, 7, 4, -6, 38, -5, 33), -- CABAC_ENTRY(268, 10, 14, 10, 8, -13, 62, -4, 48), -- CABAC_ENTRY(269, 14, 18, 17, 8, -6, 58, -2, 53), -- CABAC_ENTRY(270, 13, 27, 16, 19, -2, 59, -3, 62), -- CABAC_ENTRY(271, 2, 40, 3, 37, -16, 73, -13, 71), -- CABAC_ENTRY(272, 0, 58, -1, 61, -10, 76, -10, 79), -- CABAC_ENTRY(273, -3, 70, -5, 73, -13, 86, -12, 86), -- CABAC_ENTRY(274, -6, 79, -1, 70, -9, 83, -13, 90), -- CABAC_ENTRY(275, -8, 85, -4, 78, -10, 87, -14, 97), -- -- /* Table 9-22 – Values of variables m and n for ctxIdx from 277 to 337 */ -- CABAC_ENTRY(277, -13, 106, -21, 126, -22, 127, -6, 93), -- CABAC_ENTRY(278, -16, 106, -23, 124, -25, 127, -6, 84), -- CABAC_ENTRY(279, -10, 87, -20, 110, -25, 120, -8, 79), -- CABAC_ENTRY(280, -21, 114, -26, 126, -27, 127, 0, 66), -- CABAC_ENTRY(281, -18, 110, -25, 124, -19, 114, -1, 71), -- CABAC_ENTRY(282, -14, 98, -17, 105, -23, 117, 0, 62), -- CABAC_ENTRY(283, -22, 110, -27, 121, -25, 118, -2, 60), -- CABAC_ENTRY(284, -21, 106, -27, 117, -26, 117, -2, 59), -- CABAC_ENTRY(285, -18, 103, -17, 102, -24, 113, -5, 75), -- CABAC_ENTRY(286, -21, 107, -26, 117, -28, 118, -3, 62), -- CABAC_ENTRY(287, -23, 108, -27, 116, -31, 120, -4, 58), -- CABAC_ENTRY(288, -26, 112, -33, 122, -37, 124, -9, 66), -- CABAC_ENTRY(289, -10, 96, -10, 95, -10, 94, -1, 79), -- CABAC_ENTRY(290, -12, 95, -14, 100, -15, 102, 0, 71), -- CABAC_ENTRY(291, -5, 91, -8, 95, -10, 99, 3, 68), -- CABAC_ENTRY(292, -9, 93, -17, 111, -13, 106, 10, 44), -- CABAC_ENTRY(293, -22, 94, -28, 114, -50, 127, -7, 62), -- CABAC_ENTRY(294, -5, 86, -6, 89, -5, 92, 15, 36), -- CABAC_ENTRY(295, 9, 67, -2, 80, 17, 57, 14, 40), -- CABAC_ENTRY(296, -4, 80, -4, 82, -5, 86, 16, 27), -- CABAC_ENTRY(297, -10, 85, -9, 85, -13, 94, 12, 29), -- CABAC_ENTRY(298, -1, 70, -8, 81, -12, 91, 1, 44), -- CABAC_ENTRY(299, 7, 60, -1, 72, -2, 77, 20, 36), -- CABAC_ENTRY(300, 9, 58, 5, 64, 0, 71, 18, 32), -- CABAC_ENTRY(301, 5, 61, 1, 67, -1, 73, 5, 42), -- CABAC_ENTRY(302, 12, 50, 9, 56, 4, 64, 1, 48), -- CABAC_ENTRY(303, 15, 50, 0, 69, -7, 81, 10, 62), -- CABAC_ENTRY(304, 18, 49, 1, 69, 5, 64, 17, 46), -- CABAC_ENTRY(305, 17, 54, 7, 69, 15, 57, 9, 64), -- CABAC_ENTRY(306, 10, 41, -7, 69, 1, 67, -12, 104), -- CABAC_ENTRY(307, 7, 46, -6, 67, 0, 68, -11, 97), -- CABAC_ENTRY(308, -1, 51, -16, 77, -10, 67, -16, 96), -- CABAC_ENTRY(309, 7, 49, -2, 64, 1, 68, -7, 88), -- CABAC_ENTRY(310, 8, 52, 2, 61, 0, 77, -8, 85), -- CABAC_ENTRY(311, 9, 41, -6, 67, 2, 64, -7, 85), -- CABAC_ENTRY(312, 6, 47, -3, 64, 0, 68, -9, 85), -- CABAC_ENTRY(313, 2, 55, 2, 57, -5, 78, -13, 88), -- CABAC_ENTRY(314, 13, 41, -3, 65, 7, 55, 4, 66), -- CABAC_ENTRY(315, 10, 44, -3, 66, 5, 59, -3, 77), -- CABAC_ENTRY(316, 6, 50, 0, 62, 2, 65, -3, 76), -- CABAC_ENTRY(317, 5, 53, 9, 51, 14, 54, -6, 76), -- CABAC_ENTRY(318, 13, 49, -1, 66, 15, 44, 10, 58), -- CABAC_ENTRY(319, 4, 63, -2, 71, 5, 60, -1, 76), -- CABAC_ENTRY(320, 6, 64, -2, 75, 2, 70, -1, 83), -- CABAC_ENTRY(321, -2, 69, -1, 70, -2, 76, -7, 99), -- CABAC_ENTRY(322, -2, 59, -9, 72, -18, 86, -14, 95), -- CABAC_ENTRY(323, 6, 70, 14, 60, 12, 70, 2, 95), -- CABAC_ENTRY(324, 10, 44, 16, 37, 5, 64, 0, 76), -- CABAC_ENTRY(325, 9, 31, 0, 47, -12, 70, -5, 74), -- CABAC_ENTRY(326, 12, 43, 18, 35, 11, 55, 0, 70), -- CABAC_ENTRY(327, 3, 53, 11, 37, 5, 56, -11, 75), -- CABAC_ENTRY(328, 14, 34, 12, 41, 0, 69, 1, 68), -- CABAC_ENTRY(329, 10, 38, 10, 41, 2, 65, 0, 65), -- CABAC_ENTRY(330, -3, 52, 2, 48, -6, 74, -14, 73), -- CABAC_ENTRY(331, 13, 40, 12, 41, 5, 54, 3, 62), -- CABAC_ENTRY(332, 17, 32, 13, 41, 7, 54, 4, 62), -- CABAC_ENTRY(333, 7, 44, 0, 59, -6, 76, -1, 68), -- CABAC_ENTRY(334, 7, 38, 3, 50, -11, 82, -13, 75), -- CABAC_ENTRY(335, 13, 50, 19, 40, -2, 77, 11, 55), -- CABAC_ENTRY(336, 10, 57, 3, 66, -2, 77, 5, 64), -- CABAC_ENTRY(337, 26, 43, 18, 50, 25, 42, 12, 70), -- -- /* Table 9-23 – Values of variables m and n for ctxIdx from 338 to 398 */ -- CABAC_ENTRY(338, 14, 11, 19, -6, 17, -13, 15, 6), -- CABAC_ENTRY(339, 11, 14, 18, -6, 16, -9, 6, 19), -- CABAC_ENTRY(340, 9, 11, 14, 0, 17, -12, 7, 16), -- CABAC_ENTRY(341, 18, 11, 26, -12, 27, -21, 12, 14), -- CABAC_ENTRY(342, 21, 9, 31, -16, 37, -30, 18, 13), -- CABAC_ENTRY(343, 23, -2, 33, -25, 41, -40, 13, 11), -- CABAC_ENTRY(344, 32, -15, 33, -22, 42, -41, 13, 15), -- CABAC_ENTRY(345, 32, -15, 37, -28, 48, -47, 15, 16), -- CABAC_ENTRY(346, 34, -21, 39, -30, 39, -32, 12, 23), -- CABAC_ENTRY(347, 39, -23, 42, -30, 46, -40, 13, 23), -- CABAC_ENTRY(348, 42, -33, 47, -42, 52, -51, 15, 20), -- CABAC_ENTRY(349, 41, -31, 45, -36, 46, -41, 14, 26), -- CABAC_ENTRY(350, 46, -28, 49, -34, 52, -39, 14, 44), -- CABAC_ENTRY(351, 38, -12, 41, -17, 43, -19, 17, 40), -- CABAC_ENTRY(352, 21, 29, 32, 9, 32, 11, 17, 47), -- CABAC_ENTRY(353, 45, -24, 69, -71, 61, -55, 24, 17), -- CABAC_ENTRY(354, 53, -45, 63, -63, 56, -46, 21, 21), -- CABAC_ENTRY(355, 48, -26, 66, -64, 62, -50, 25, 22), -- CABAC_ENTRY(356, 65, -43, 77, -74, 81, -67, 31, 27), -- CABAC_ENTRY(357, 43, -19, 54, -39, 45, -20, 22, 29), -- CABAC_ENTRY(358, 39, -10, 52, -35, 35, -2, 19, 35), -- CABAC_ENTRY(359, 30, 9, 41, -10, 28, 15, 14, 50), -- CABAC_ENTRY(360, 18, 26, 36, 0, 34, 1, 10, 57), -- CABAC_ENTRY(361, 20, 27, 40, -1, 39, 1, 7, 63), -- CABAC_ENTRY(362, 0, 57, 30, 14, 30, 17, -2, 77), -- CABAC_ENTRY(363, -14, 82, 28, 26, 20, 38, -4, 82), -- CABAC_ENTRY(364, -5, 75, 23, 37, 18, 45, -3, 94), -- CABAC_ENTRY(365, -19, 97, 12, 55, 15, 54, 9, 69), -- CABAC_ENTRY(366, -35, 125, 11, 65, 0, 79, -12, 109), -- CABAC_ENTRY(367, 27, 0, 37, -33, 36, -16, 36, -35), -- CABAC_ENTRY(368, 28, 0, 39, -36, 37, -14, 36, -34), -- CABAC_ENTRY(369, 31, -4, 40, -37, 37, -17, 32, -26), -- CABAC_ENTRY(370, 27, 6, 38, -30, 32, 1, 37, -30), -- CABAC_ENTRY(371, 34, 8, 46, -33, 34, 15, 44, -32), -- CABAC_ENTRY(372, 30, 10, 42, -30, 29, 15, 34, -18), -- CABAC_ENTRY(373, 24, 22, 40, -24, 24, 25, 34, -15), -- CABAC_ENTRY(374, 33, 19, 49, -29, 34, 22, 40, -15), -- CABAC_ENTRY(375, 22, 32, 38, -12, 31, 16, 33, -7), -- CABAC_ENTRY(376, 26, 31, 40, -10, 35, 18, 35, -5), -- CABAC_ENTRY(377, 21, 41, 38, -3, 31, 28, 33, 0), -- CABAC_ENTRY(378, 26, 44, 46, -5, 33, 41, 38, 2), -- CABAC_ENTRY(379, 23, 47, 31, 20, 36, 28, 33, 13), -- CABAC_ENTRY(380, 16, 65, 29, 30, 27, 47, 23, 35), -- CABAC_ENTRY(381, 14, 71, 25, 44, 21, 62, 13, 58), -- CABAC_ENTRY(382, 8, 60, 12, 48, 18, 31, 29, -3), -- CABAC_ENTRY(383, 6, 63, 11, 49, 19, 26, 26, 0), -- CABAC_ENTRY(384, 17, 65, 26, 45, 36, 24, 22, 30), -- CABAC_ENTRY(385, 21, 24, 22, 22, 24, 23, 31, -7), -- CABAC_ENTRY(386, 23, 20, 23, 22, 27, 16, 35, -15), -- CABAC_ENTRY(387, 26, 23, 27, 21, 24, 30, 34, -3), -- CABAC_ENTRY(388, 27, 32, 33, 20, 31, 29, 34, 3), -- CABAC_ENTRY(389, 28, 23, 26, 28, 22, 41, 36, -1), -- CABAC_ENTRY(390, 28, 24, 30, 24, 22, 42, 34, 5), -- CABAC_ENTRY(391, 23, 40, 27, 34, 16, 60, 32, 11), -- CABAC_ENTRY(392, 24, 32, 18, 42, 15, 52, 35, 5), -- CABAC_ENTRY(393, 28, 29, 25, 39, 14, 60, 34, 12), -- CABAC_ENTRY(394, 23, 42, 18, 50, 3, 78, 39, 11), -- CABAC_ENTRY(395, 19, 57, 12, 70, -16, 123, 30, 29), -- CABAC_ENTRY(396, 22, 53, 21, 54, 21, 53, 34, 26), -- CABAC_ENTRY(397, 22, 61, 14, 71, 22, 56, 29, 39), -- CABAC_ENTRY(398, 11, 86, 11, 83, 25, 61, 19, 66), -- -- /* Values of variables m and n for ctxIdx from 399 to 463 (not documented) */ -- CABAC_ENTRY(399, 12, 40, 25, 32, 21, 33, 31, 21), -- CABAC_ENTRY(400, 11, 51, 21, 49, 19, 50, 31, 31), -- CABAC_ENTRY(401, 14, 59, 21, 54, 17, 61, 25, 50), -- CABAC_ENTRY(402, -4, 79, -5, 85, -3, 78, -17, 120), -- CABAC_ENTRY(403, -7, 71, -6, 81, -8, 74, -20, 112), -- CABAC_ENTRY(404, -5, 69, -10, 77, -9, 72, -18, 114), -- CABAC_ENTRY(405, -9, 70, -7, 81, -10, 72, -11, 85), -- CABAC_ENTRY(406, -8, 66, -17, 80, -18, 75, -15, 92), -- CABAC_ENTRY(407, -10, 68, -18, 73, -12, 71, -14, 89), -- CABAC_ENTRY(408, -19, 73, -4, 74, -11, 63, -26, 71), -- CABAC_ENTRY(409, -12, 69, -10, 83, -5, 70, -15, 81), -- CABAC_ENTRY(410, -16, 70, -9, 71, -17, 75, -14, 80), -- CABAC_ENTRY(411, -15, 67, -9, 67, -14, 72, 0, 68), -- CABAC_ENTRY(412, -20, 62, -1, 61, -16, 67, -14, 70), -- CABAC_ENTRY(413, -19, 70, -8, 66, -8, 53, -24, 56), -- CABAC_ENTRY(414, -16, 66, -14, 66, -14, 59, -23, 68), -- CABAC_ENTRY(415, -22, 65, 0, 59, -9, 52, -24, 50), -- CABAC_ENTRY(416, -20, 63, 2, 59, -11, 68, -11, 74), -- CABAC_ENTRY(417, 9, -2, 17, -10, 9, -2, 23, -13), -- CABAC_ENTRY(418, 26, -9, 32, -13, 30, -10, 26, -13), -- CABAC_ENTRY(419, 33, -9, 42, -9, 31, -4, 40, -15), -- CABAC_ENTRY(420, 39, -7, 49, -5, 33, -1, 49, -14), -- CABAC_ENTRY(421, 41, -2, 53, 0, 33, 7, 44, 3), -- CABAC_ENTRY(422, 45, 3, 64, 3, 31, 12, 45, 6), -- CABAC_ENTRY(423, 49, 9, 68, 10, 37, 23, 44, 34), -- CABAC_ENTRY(424, 45, 27, 66, 27, 31, 38, 33, 54), -- CABAC_ENTRY(425, 36, 59, 47, 57, 20, 64, 19, 82), -- CABAC_ENTRY(426, -6, 66, -5, 71, -9, 71, -3, 75), -- CABAC_ENTRY(427, -7, 35, 0, 24, -7, 37, -1, 23), -- CABAC_ENTRY(428, -7, 42, -1, 36, -8, 44, 1, 34), -- CABAC_ENTRY(429, -8, 45, -2, 42, -11, 49, 1, 43), -- CABAC_ENTRY(430, -5, 48, -2, 52, -10, 56, 0, 54), -- CABAC_ENTRY(431, -12, 56, -9, 57, -12, 59, -2, 55), -- CABAC_ENTRY(432, -6, 60, -6, 63, -8, 63, 0, 61), -- CABAC_ENTRY(433, -5, 62, -4, 65, -9, 67, 1, 64), -- CABAC_ENTRY(434, -8, 66, -4, 67, -6, 68, 0, 68), -- CABAC_ENTRY(435, -8, 76, -7, 82, -10, 79, -9, 92), -- CABAC_ENTRY(436, -5, 85, -3, 81, -3, 78, -14, 106), -- CABAC_ENTRY(437, -6, 81, -3, 76, -8, 74, -13, 97), -- CABAC_ENTRY(438, -10, 77, -7, 72, -9, 72, -15, 90), -- CABAC_ENTRY(439, -7, 81, -6, 78, -10, 72, -12, 90), -- CABAC_ENTRY(440, -17, 80, -12, 72, -18, 75, -18, 88), -- CABAC_ENTRY(441, -18, 73, -14, 68, -12, 71, -10, 73), -- CABAC_ENTRY(442, -4, 74, -3, 70, -11, 63, -9, 79), -- CABAC_ENTRY(443, -10, 83, -6, 76, -5, 70, -14, 86), -- CABAC_ENTRY(444, -9, 71, -5, 66, -17, 75, -10, 73), -- CABAC_ENTRY(445, -9, 67, -5, 62, -14, 72, -10, 70), -- CABAC_ENTRY(446, -1, 61, 0, 57, -16, 67, -10, 69), -- CABAC_ENTRY(447, -8, 66, -4, 61, -8, 53, -5, 66), -- CABAC_ENTRY(448, -14, 66, -9, 60, -14, 59, -9, 64), -- CABAC_ENTRY(449, 0, 59, 1, 54, -9, 52, -5, 58), -- CABAC_ENTRY(450, 2, 59, 2, 58, -11, 68, 2, 59), -- CABAC_ENTRY(451, 21, -13, 17, -10, 9, -2, 21, -10), -- CABAC_ENTRY(452, 33, -14, 32, -13, 30, -10, 24, -11), -- CABAC_ENTRY(453, 39, -7, 42, -9, 31, -4, 28, -8), -- CABAC_ENTRY(454, 46, -2, 49, -5, 33, -1, 28, -1), -- CABAC_ENTRY(455, 51, 2, 53, 0, 33, 7, 29, 3), -- CABAC_ENTRY(456, 60, 6, 64, 3, 31, 12, 29, 9), -- CABAC_ENTRY(457, 61, 17, 68, 10, 37, 23, 35, 20), -- CABAC_ENTRY(458, 55, 34, 66, 27, 31, 38, 29, 36), -- CABAC_ENTRY(459, 42, 62, 47, 57, 20, 64, 14, 67), --}; -- - static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) - { - u8 bit = field.offset % 32, word = field.offset / 32; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -@@ -16,7 +16,6 @@ - - #include "rkvdec.h" - #include "rkvdec-regs.h" --#include "rkvdec-hevc-data.c" - - /* Size in u8/u32 units. */ - #define RKV_SCALING_LIST_SIZE 1360 -@@ -25,6 +24,9 @@ - #define RKV_RPS_SIZE (32 / 4) - #define RKV_RPS_LEN 600 - -+#define RKV_HEVC_CABAC_TABLE_SIZE 27456 -+extern const u8 rkvdec_hevc_cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; -+ - struct rkvdec_sps_pps_packet { - u32 info[RKV_PPS_SIZE]; - }; -@@ -110,7 +112,7 @@ struct rkvdec_ps_field { - - /* Data structure describing auxiliary buffer format. */ - struct rkvdec_hevc_priv_tbl { -- u8 cabac_table[RKV_CABAC_TABLE_SIZE]; -+ u8 cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; - u8 scaling_list[RKV_SCALING_LIST_SIZE]; - struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; - struct rkvdec_rps_packet rps[RKV_RPS_LEN]; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Wed, 11 Jun 2025 12:28:56 -0400 -Subject: media: rkvdec: Use structs to represent the HW RPS - -This is in preparation to add support for other variants of the decoder. - -Moving to struct representation is mainly to prepare for multicore -support that is present in e.g. rk3588. - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 97 ++++++++-- - 1 file changed, 86 insertions(+), 11 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -@@ -19,7 +19,6 @@ extern const s8 rkvdec_h264_cabac_table[4][464][2]; - - /* Size with u32 units. */ - #define RKV_CABAC_INIT_BUFFER_SIZE (3680 + 128) --#define RKV_RPS_SIZE ((128 + 128) / 4) - #define RKV_ERROR_INFO_SIZE (256 * 144 * 4) - - #define RKVDEC_NUM_REFLIST 3 -@@ -34,6 +33,40 @@ struct rkvdec_sps_pps_packet { - u32 info[8]; - }; - -+struct rkvdec_rps_entry { -+ u32 dpb_info0: 5; -+ u32 bottom_flag0: 1; -+ u32 view_index_off0: 1; -+ u32 dpb_info1: 5; -+ u32 bottom_flag1: 1; -+ u32 view_index_off1: 1; -+ u32 dpb_info2: 5; -+ u32 bottom_flag2: 1; -+ u32 view_index_off2: 1; -+ u32 dpb_info3: 5; -+ u32 bottom_flag3: 1; -+ u32 view_index_off3: 1; -+ u32 dpb_info4: 5; -+ u32 bottom_flag4: 1; -+ u32 view_index_off4: 1; -+ u32 dpb_info5: 5; -+ u32 bottom_flag5: 1; -+ u32 view_index_off5: 1; -+ u32 dpb_info6: 5; -+ u32 bottom_flag6: 1; -+ u32 view_index_off6: 1; -+ u32 dpb_info7: 5; -+ u32 bottom_flag7: 1; -+ u32 view_index_off7: 1; -+} __packed; -+ -+struct rkvdec_rps { -+ u16 frame_num[16]; -+ u32 reserved0; -+ struct rkvdec_rps_entry entries[12]; -+ u32 reserved1[66]; -+} __packed; -+ - struct rkvdec_ps_field { - u16 offset; - u8 len; -@@ -94,7 +127,7 @@ struct rkvdec_ps_field { - struct rkvdec_h264_priv_tbl { - s8 cabac_table[4][464][2]; - struct rkvdec_h264_scaling_list scaling_list; -- u32 rps[RKV_RPS_SIZE]; -+ struct rkvdec_rps rps; - struct rkvdec_sps_pps_packet param_set[256]; - u8 err_info[RKV_ERROR_INFO_SIZE]; - }; -@@ -260,20 +293,64 @@ static void lookup_ref_buf_idx(struct rkvdec_ctx *ctx, - } - } - -+static void set_dpb_info(struct rkvdec_rps_entry *entries, -+ u8 reflist, -+ u8 refnum, -+ u8 info, -+ bool bottom) -+{ -+ struct rkvdec_rps_entry *entry = &entries[(reflist * 4) + refnum / 8]; -+ u8 idx = refnum % 8; -+ -+ switch (idx) { -+ case 0: -+ entry->dpb_info0 = info; -+ entry->bottom_flag0 = bottom; -+ break; -+ case 1: -+ entry->dpb_info1 = info; -+ entry->bottom_flag1 = bottom; -+ break; -+ case 2: -+ entry->dpb_info2 = info; -+ entry->bottom_flag2 = bottom; -+ break; -+ case 3: -+ entry->dpb_info3 = info; -+ entry->bottom_flag3 = bottom; -+ break; -+ case 4: -+ entry->dpb_info4 = info; -+ entry->bottom_flag4 = bottom; -+ break; -+ case 5: -+ entry->dpb_info5 = info; -+ entry->bottom_flag5 = bottom; -+ break; -+ case 6: -+ entry->dpb_info6 = info; -+ entry->bottom_flag6 = bottom; -+ break; -+ case 7: -+ entry->dpb_info7 = info; -+ entry->bottom_flag7 = bottom; -+ break; -+ } -+} -+ - static void assemble_hw_rps(struct rkvdec_ctx *ctx, -- struct v4l2_h264_reflist_builder *builder, -- struct rkvdec_h264_run *run) -+ struct v4l2_h264_reflist_builder *builder, -+ struct rkvdec_h264_run *run) - { - const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; - const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; - struct rkvdec_h264_ctx *h264_ctx = ctx->priv; - struct rkvdec_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; - -- u32 *hw_rps = priv_tbl->rps; -+ struct rkvdec_rps *hw_rps = &priv_tbl->rps; - u32 i, j; -- u16 *p = (u16 *)hw_rps; - -- memset(hw_rps, 0, sizeof(priv_tbl->rps)); -+ memset(hw_rps, 0, sizeof(*hw_rps)); - - /* - * Assign an invalid pic_num if DPB entry at that position is inactive. -@@ -285,7 +362,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) - continue; - -- p[i] = builder->refs[i].frame_num; -+ hw_rps->frame_num[i] = builder->refs[i].frame_num; - } - - for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { -@@ -312,9 +389,7 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - dpb_valid = run->ref_buf[ref->index] != NULL; - bottom = ref->fields == V4L2_H264_BOTTOM_FIELD_REF; - -- set_ps_field(hw_rps, DPB_INFO(i, j), -- ref->index | dpb_valid << 4); -- set_ps_field(hw_rps, BOTTOM_FLAG(i, j), bottom); -+ set_dpb_info(hw_rps->entries, j, i, ref->index | (dpb_valid << 4), bottom); - } - } - } --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Tue, 10 Jun 2025 13:16:24 -0400 -Subject: media: rkvdec: Move h264 functions to common file - -This is a preparation commit to add support for new variants of the -decoder. - -The functions will later be shared with vdpu381 (rk3588) and vdpu383 -(rk3576). - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/Makefile | 1 + - drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c | 253 ++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h | 79 +++ - drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 308 +--------- - 4 files changed, 337 insertions(+), 304 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/Makefile -+++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -4,5 +4,6 @@ rockchip-vdec-y += \ - rkvdec.o \ - rkvdec-cabac.o \ - rkvdec-h264.o \ -+ rkvdec-h264-common.o \ - rkvdec-hevc.o \ - rkvdec-vp9.o -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c -@@ -0,0 +1,253 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip video decoder h264 common functions -+ * -+ * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#include -+#include -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-h264-common.h" -+ -+#define RKVDEC_NUM_REFLIST 3 -+ -+static void set_dpb_info(struct rkvdec_rps_entry *entries, -+ u8 reflist, -+ u8 refnum, -+ u8 info, -+ bool bottom) -+{ -+ struct rkvdec_rps_entry *entry = &entries[(reflist * 4) + refnum / 8]; -+ u8 idx = refnum % 8; -+ -+ switch (idx) { -+ case 0: -+ entry->dpb_info0 = info; -+ entry->bottom_flag0 = bottom; -+ break; -+ case 1: -+ entry->dpb_info1 = info; -+ entry->bottom_flag1 = bottom; -+ break; -+ case 2: -+ entry->dpb_info2 = info; -+ entry->bottom_flag2 = bottom; -+ break; -+ case 3: -+ entry->dpb_info3 = info; -+ entry->bottom_flag3 = bottom; -+ break; -+ case 4: -+ entry->dpb_info4 = info; -+ entry->bottom_flag4 = bottom; -+ break; -+ case 5: -+ entry->dpb_info5 = info; -+ entry->bottom_flag5 = bottom; -+ break; -+ case 6: -+ entry->dpb_info6 = info; -+ entry->bottom_flag6 = bottom; -+ break; -+ case 7: -+ entry->dpb_info7 = info; -+ entry->bottom_flag7 = bottom; -+ break; -+ } -+} -+ -+void lookup_ref_buf_idx(struct rkvdec_ctx *ctx, -+ struct rkvdec_h264_run *run) -+{ -+ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -+ u32 i; -+ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_h264_dpb_entry *dpb = run->decode_params->dpb; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *buf = NULL; -+ -+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) { -+ buf = vb2_find_buffer(cap_q, dpb[i].reference_ts); -+ if (!buf) -+ pr_debug("No buffer for reference_ts %llu", -+ dpb[i].reference_ts); -+ } -+ -+ run->ref_buf[i] = buf; -+ } -+} -+ -+void assemble_hw_rps(struct v4l2_h264_reflist_builder *builder, -+ struct rkvdec_h264_run *run, -+ struct rkvdec_h264_reflists *reflists, -+ struct rkvdec_rps *hw_rps) -+{ -+ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -+ const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; -+ -+ u32 i, j; -+ -+ memset(hw_rps, 0, sizeof(*hw_rps)); -+ -+ /* -+ * Assign an invalid pic_num if DPB entry at that position is inactive. -+ * If we assign 0 in that position hardware will treat that as a real -+ * reference picture with pic_num 0, triggering output picture -+ * corruption. -+ */ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -+ continue; -+ -+ hw_rps->frame_num[i] = builder->refs[i].frame_num; -+ } -+ -+ for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { -+ for (i = 0; i < builder->num_valid; i++) { -+ struct v4l2_h264_reference *ref; -+ bool dpb_valid; -+ bool bottom; -+ -+ switch (j) { -+ case 0: -+ ref = &reflists->p[i]; -+ break; -+ case 1: -+ ref = &reflists->b0[i]; -+ break; -+ case 2: -+ ref = &reflists->b1[i]; -+ break; -+ } -+ -+ if (WARN_ON(ref->index >= ARRAY_SIZE(dec_params->dpb))) -+ continue; -+ -+ dpb_valid = !!(run->ref_buf[ref->index]); -+ bottom = ref->fields == V4L2_H264_BOTTOM_FIELD_REF; -+ -+ set_dpb_info(hw_rps->entries, j, i, ref->index | (dpb_valid << 4), bottom); -+ } -+ } -+} -+ -+void assemble_hw_scaling_list(struct rkvdec_h264_run *run, -+ struct rkvdec_h264_scaling_list *scaling_list) -+{ -+ const struct v4l2_ctrl_h264_scaling_matrix *scaling = run->scaling_matrix; -+ const struct v4l2_ctrl_h264_pps *pps = run->pps; -+ -+ if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT)) -+ return; -+ -+ BUILD_BUG_ON(sizeof(scaling_list->scaling_list_4x4) != -+ sizeof(scaling->scaling_list_4x4)); -+ BUILD_BUG_ON(sizeof(scaling_list->scaling_list_8x8) != -+ sizeof(scaling->scaling_list_8x8)); -+ -+ memcpy(scaling_list->scaling_list_4x4, -+ scaling->scaling_list_4x4, -+ sizeof(scaling->scaling_list_4x4)); -+ -+ memcpy(scaling_list->scaling_list_8x8, -+ scaling->scaling_list_8x8, -+ sizeof(scaling->scaling_list_8x8)); -+} -+ -+#define RKVDEC_H264_MAX_DEPTH_IN_BYTES 2 -+ -+int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -+ RKVDEC_H264_MAX_DEPTH_IN_BYTES; -+ return 0; -+} -+ -+enum rkvdec_image_fmt rkvdec_h264_get_image_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; -+ -+ if (ctrl->id != V4L2_CID_STATELESS_H264_SPS) -+ return RKVDEC_IMG_FMT_ANY; -+ -+ if (sps->bit_depth_luma_minus8 == 0) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_8BIT; -+ else -+ return RKVDEC_IMG_FMT_420_8BIT; -+ } else if (sps->bit_depth_luma_minus8 == 2) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_10BIT; -+ else -+ return RKVDEC_IMG_FMT_420_10BIT; -+ } -+ -+ return RKVDEC_IMG_FMT_ANY; -+} -+ -+int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_h264_sps *sps) -+{ -+ unsigned int width, height; -+ -+ if (sps->chroma_format_idc > 2) -+ /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ width = (sps->pic_width_in_mbs_minus1 + 1) * 16; -+ height = (sps->pic_height_in_map_units_minus1 + 1) * 16; -+ -+ /* -+ * When frame_mbs_only_flag is not set, this is field height, -+ * which is half the final height (see (7-18) in the -+ * specification) -+ */ -+ if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) -+ height *= 2; -+ -+ if (width > ctx->coded_fmt.fmt.pix_mp.width || -+ height > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+void rkvdec_h264_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_h264_run *run) -+{ -+ struct v4l2_ctrl *ctrl; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_SPS); -+ run->sps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_PPS); -+ run->pps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_SCALING_MATRIX); -+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ -+ rkvdec_run_preamble(ctx, &run->base); -+} -+ -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h -@@ -0,0 +1,79 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Rockchip video decoder h264 common functions -+ * -+ * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#include -+#include -+ -+#include "rkvdec.h" -+ -+struct rkvdec_h264_scaling_list { -+ u8 scaling_list_4x4[6][16]; -+ u8 scaling_list_8x8[6][64]; -+ u8 padding[128]; -+}; -+ -+struct rkvdec_h264_reflists { -+ struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; -+ struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN]; -+ struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN]; -+}; -+ -+struct rkvdec_h264_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_h264_decode_params *decode_params; -+ const struct v4l2_ctrl_h264_sps *sps; -+ const struct v4l2_ctrl_h264_pps *pps; -+ const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; -+ struct vb2_buffer *ref_buf[V4L2_H264_NUM_DPB_ENTRIES]; -+}; -+ -+struct rkvdec_rps_entry { -+ u32 dpb_info0: 5; -+ u32 bottom_flag0: 1; -+ u32 view_index_off0: 1; -+ u32 dpb_info1: 5; -+ u32 bottom_flag1: 1; -+ u32 view_index_off1: 1; -+ u32 dpb_info2: 5; -+ u32 bottom_flag2: 1; -+ u32 view_index_off2: 1; -+ u32 dpb_info3: 5; -+ u32 bottom_flag3: 1; -+ u32 view_index_off3: 1; -+ u32 dpb_info4: 5; -+ u32 bottom_flag4: 1; -+ u32 view_index_off4: 1; -+ u32 dpb_info5: 5; -+ u32 bottom_flag5: 1; -+ u32 view_index_off5: 1; -+ u32 dpb_info6: 5; -+ u32 bottom_flag6: 1; -+ u32 view_index_off6: 1; -+ u32 dpb_info7: 5; -+ u32 bottom_flag7: 1; -+ u32 view_index_off7: 1; -+} __packed; -+ -+struct rkvdec_rps { -+ u16 frame_num[16]; -+ u32 reserved0; -+ struct rkvdec_rps_entry entries[12]; -+ u32 reserved1[66]; -+} __packed; -+ -+void lookup_ref_buf_idx(struct rkvdec_ctx *ctx, struct rkvdec_h264_run *run); -+void assemble_hw_rps(struct v4l2_h264_reflist_builder *builder, -+ struct rkvdec_h264_run *run, -+ struct rkvdec_h264_reflists *reflists, -+ struct rkvdec_rps *hw_rps); -+void assemble_hw_scaling_list(struct rkvdec_h264_run *run, -+ struct rkvdec_h264_scaling_list *scaling_list); -+int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f); -+enum rkvdec_image_fmt rkvdec_h264_get_image_fmt(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); -+int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, const struct v4l2_ctrl_h264_sps *sps); -+void rkvdec_h264_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_h264_run *run); -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -@@ -14,6 +14,7 @@ - - #include "rkvdec.h" - #include "rkvdec-regs.h" -+#include "rkvdec-h264-common.h" - - extern const s8 rkvdec_h264_cabac_table[4][464][2]; - -@@ -21,52 +22,10 @@ extern const s8 rkvdec_h264_cabac_table[4][464][2]; - #define RKV_CABAC_INIT_BUFFER_SIZE (3680 + 128) - #define RKV_ERROR_INFO_SIZE (256 * 144 * 4) - --#define RKVDEC_NUM_REFLIST 3 -- --struct rkvdec_h264_scaling_list { -- u8 scaling_list_4x4[6][16]; -- u8 scaling_list_8x8[6][64]; -- u8 padding[128]; --}; -- - struct rkvdec_sps_pps_packet { - u32 info[8]; - }; - --struct rkvdec_rps_entry { -- u32 dpb_info0: 5; -- u32 bottom_flag0: 1; -- u32 view_index_off0: 1; -- u32 dpb_info1: 5; -- u32 bottom_flag1: 1; -- u32 view_index_off1: 1; -- u32 dpb_info2: 5; -- u32 bottom_flag2: 1; -- u32 view_index_off2: 1; -- u32 dpb_info3: 5; -- u32 bottom_flag3: 1; -- u32 view_index_off3: 1; -- u32 dpb_info4: 5; -- u32 bottom_flag4: 1; -- u32 view_index_off4: 1; -- u32 dpb_info5: 5; -- u32 bottom_flag5: 1; -- u32 view_index_off5: 1; -- u32 dpb_info6: 5; -- u32 bottom_flag6: 1; -- u32 view_index_off6: 1; -- u32 dpb_info7: 5; -- u32 bottom_flag7: 1; -- u32 view_index_off7: 1; --} __packed; -- --struct rkvdec_rps { -- u16 frame_num[16]; -- u32 reserved0; -- struct rkvdec_rps_entry entries[12]; -- u32 reserved1[66]; --} __packed; -- - struct rkvdec_ps_field { - u16 offset; - u8 len; -@@ -118,11 +77,6 @@ struct rkvdec_ps_field { - #define SCALING_LIST_ADDRESS PS_FIELD(184, 32) - #define IS_LONG_TERM(i) PS_FIELD(216 + (i), 1) - --#define DPB_OFFS(i, j) (288 + ((j) * 32 * 7) + ((i) * 7)) --#define DPB_INFO(i, j) PS_FIELD(DPB_OFFS(i, j), 5) --#define BOTTOM_FLAG(i, j) PS_FIELD(DPB_OFFS(i, j) + 5, 1) --#define VIEW_INDEX_OFF(i, j) PS_FIELD(DPB_OFFS(i, j) + 6, 1) -- - /* Data structure describing auxiliary buffer format. */ - struct rkvdec_h264_priv_tbl { - s8 cabac_table[4][464][2]; -@@ -132,21 +86,6 @@ struct rkvdec_h264_priv_tbl { - u8 err_info[RKV_ERROR_INFO_SIZE]; - }; - --struct rkvdec_h264_reflists { -- struct v4l2_h264_reference p[V4L2_H264_REF_LIST_LEN]; -- struct v4l2_h264_reference b0[V4L2_H264_REF_LIST_LEN]; -- struct v4l2_h264_reference b1[V4L2_H264_REF_LIST_LEN]; --}; -- --struct rkvdec_h264_run { -- struct rkvdec_run base; -- const struct v4l2_ctrl_h264_decode_params *decode_params; -- const struct v4l2_ctrl_h264_sps *sps; -- const struct v4l2_ctrl_h264_pps *pps; -- const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; -- struct vb2_buffer *ref_buf[V4L2_H264_NUM_DPB_ENTRIES]; --}; -- - struct rkvdec_h264_ctx { - struct rkvdec_aux_buf priv_tbl; - struct rkvdec_h264_reflists reflists; -@@ -270,155 +209,6 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx, - } - } - --static void lookup_ref_buf_idx(struct rkvdec_ctx *ctx, -- struct rkvdec_h264_run *run) --{ -- const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -- u32 i; -- -- for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -- struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -- const struct v4l2_h264_dpb_entry *dpb = run->decode_params->dpb; -- struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -- struct vb2_buffer *buf = NULL; -- -- if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) { -- buf = vb2_find_buffer(cap_q, dpb[i].reference_ts); -- if (!buf) -- pr_debug("No buffer for reference_ts %llu", -- dpb[i].reference_ts); -- } -- -- run->ref_buf[i] = buf; -- } --} -- --static void set_dpb_info(struct rkvdec_rps_entry *entries, -- u8 reflist, -- u8 refnum, -- u8 info, -- bool bottom) --{ -- struct rkvdec_rps_entry *entry = &entries[(reflist * 4) + refnum / 8]; -- u8 idx = refnum % 8; -- -- switch (idx) { -- case 0: -- entry->dpb_info0 = info; -- entry->bottom_flag0 = bottom; -- break; -- case 1: -- entry->dpb_info1 = info; -- entry->bottom_flag1 = bottom; -- break; -- case 2: -- entry->dpb_info2 = info; -- entry->bottom_flag2 = bottom; -- break; -- case 3: -- entry->dpb_info3 = info; -- entry->bottom_flag3 = bottom; -- break; -- case 4: -- entry->dpb_info4 = info; -- entry->bottom_flag4 = bottom; -- break; -- case 5: -- entry->dpb_info5 = info; -- entry->bottom_flag5 = bottom; -- break; -- case 6: -- entry->dpb_info6 = info; -- entry->bottom_flag6 = bottom; -- break; -- case 7: -- entry->dpb_info7 = info; -- entry->bottom_flag7 = bottom; -- break; -- } --} -- --static void assemble_hw_rps(struct rkvdec_ctx *ctx, -- struct v4l2_h264_reflist_builder *builder, -- struct rkvdec_h264_run *run) --{ -- const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -- const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; -- struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -- struct rkvdec_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; -- -- struct rkvdec_rps *hw_rps = &priv_tbl->rps; -- u32 i, j; -- -- memset(hw_rps, 0, sizeof(*hw_rps)); -- -- /* -- * Assign an invalid pic_num if DPB entry at that position is inactive. -- * If we assign 0 in that position hardware will treat that as a real -- * reference picture with pic_num 0, triggering output picture -- * corruption. -- */ -- for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -- if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) -- continue; -- -- hw_rps->frame_num[i] = builder->refs[i].frame_num; -- } -- -- for (j = 0; j < RKVDEC_NUM_REFLIST; j++) { -- for (i = 0; i < builder->num_valid; i++) { -- struct v4l2_h264_reference *ref; -- bool dpb_valid; -- bool bottom; -- -- switch (j) { -- case 0: -- ref = &h264_ctx->reflists.p[i]; -- break; -- case 1: -- ref = &h264_ctx->reflists.b0[i]; -- break; -- case 2: -- ref = &h264_ctx->reflists.b1[i]; -- break; -- } -- -- if (WARN_ON(ref->index >= ARRAY_SIZE(dec_params->dpb))) -- continue; -- -- dpb_valid = run->ref_buf[ref->index] != NULL; -- bottom = ref->fields == V4L2_H264_BOTTOM_FIELD_REF; -- -- set_dpb_info(hw_rps->entries, j, i, ref->index | (dpb_valid << 4), bottom); -- } -- } --} -- --static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, -- struct rkvdec_h264_run *run) --{ -- const struct v4l2_ctrl_h264_scaling_matrix *scaling = run->scaling_matrix; -- const struct v4l2_ctrl_h264_pps *pps = run->pps; -- struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -- struct rkvdec_h264_priv_tbl *tbl = h264_ctx->priv_tbl.cpu; -- -- if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT)) -- return; -- -- BUILD_BUG_ON(sizeof(tbl->scaling_list.scaling_list_4x4) != -- sizeof(scaling->scaling_list_4x4)); -- BUILD_BUG_ON(sizeof(tbl->scaling_list.scaling_list_8x8) != -- sizeof(scaling->scaling_list_8x8)); -- -- memcpy(tbl->scaling_list.scaling_list_4x4, -- scaling->scaling_list_4x4, -- sizeof(scaling->scaling_list_4x4)); -- -- memcpy(tbl->scaling_list.scaling_list_8x8, -- scaling->scaling_list_8x8, -- sizeof(scaling->scaling_list_8x8)); --} -- - /* - * Set the ref POC in the correct register. - * -@@ -568,76 +358,6 @@ static void config_registers(struct rkvdec_ctx *ctx, - rkvdec_memcpy_toio(rkvdec->regs, regs, sizeof(*regs)); - } - --#define RKVDEC_H264_MAX_DEPTH_IN_BYTES 2 -- --static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx, -- struct v4l2_format *f) --{ -- struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -- -- fmt->num_planes = 1; -- if (!fmt->plane_fmt[0].sizeimage) -- fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -- RKVDEC_H264_MAX_DEPTH_IN_BYTES; -- return 0; --} -- --static enum rkvdec_image_fmt rkvdec_h264_get_image_fmt(struct rkvdec_ctx *ctx, -- struct v4l2_ctrl *ctrl) --{ -- const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; -- -- if (ctrl->id != V4L2_CID_STATELESS_H264_SPS) -- return RKVDEC_IMG_FMT_ANY; -- -- if (sps->bit_depth_luma_minus8 == 0) { -- if (sps->chroma_format_idc == 2) -- return RKVDEC_IMG_FMT_422_8BIT; -- else -- return RKVDEC_IMG_FMT_420_8BIT; -- } else if (sps->bit_depth_luma_minus8 == 2) { -- if (sps->chroma_format_idc == 2) -- return RKVDEC_IMG_FMT_422_10BIT; -- else -- return RKVDEC_IMG_FMT_420_10BIT; -- } -- -- return RKVDEC_IMG_FMT_ANY; --} -- --static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, -- const struct v4l2_ctrl_h264_sps *sps) --{ -- unsigned int width, height; -- -- if (sps->chroma_format_idc > 2) -- /* Only 4:0:0, 4:2:0 and 4:2:2 are supported */ -- return -EINVAL; -- if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -- /* Luma and chroma bit depth mismatch */ -- return -EINVAL; -- if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -- /* Only 8-bit and 10-bit is supported */ -- return -EINVAL; -- -- width = (sps->pic_width_in_mbs_minus1 + 1) * 16; -- height = (sps->pic_height_in_map_units_minus1 + 1) * 16; -- -- /* -- * When frame_mbs_only_flag is not set, this is field height, -- * which is half the final height (see (7-18) in the -- * specification) -- */ -- if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) -- height *= 2; -- -- if (width > ctx->coded_fmt.fmt.pix_mp.width || -- height > ctx->coded_fmt.fmt.pix_mp.height) -- return -EINVAL; -- -- return 0; --} -- - static int rkvdec_h264_start(struct rkvdec_ctx *ctx) - { - struct rkvdec_dev *rkvdec = ctx->dev; -@@ -689,33 +409,13 @@ static void rkvdec_h264_stop(struct rkvdec_ctx *ctx) - kfree(h264_ctx); - } - --static void rkvdec_h264_run_preamble(struct rkvdec_ctx *ctx, -- struct rkvdec_h264_run *run) --{ -- struct v4l2_ctrl *ctrl; -- -- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -- V4L2_CID_STATELESS_H264_DECODE_PARAMS); -- run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -- V4L2_CID_STATELESS_H264_SPS); -- run->sps = ctrl ? ctrl->p_cur.p : NULL; -- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -- V4L2_CID_STATELESS_H264_PPS); -- run->pps = ctrl ? ctrl->p_cur.p : NULL; -- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -- V4L2_CID_STATELESS_H264_SCALING_MATRIX); -- run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -- -- rkvdec_run_preamble(ctx, &run->base); --} -- - static int rkvdec_h264_run(struct rkvdec_ctx *ctx) - { - struct v4l2_h264_reflist_builder reflist_builder; - struct rkvdec_dev *rkvdec = ctx->dev; - struct rkvdec_h264_ctx *h264_ctx = ctx->priv; - struct rkvdec_h264_run run; -+ struct rkvdec_h264_priv_tbl *tbl = h264_ctx->priv_tbl.cpu; - - rkvdec_h264_run_preamble(ctx, &run); - -@@ -726,10 +426,10 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx) - v4l2_h264_build_b_ref_lists(&reflist_builder, h264_ctx->reflists.b0, - h264_ctx->reflists.b1); - -- assemble_hw_scaling_list(ctx, &run); -+ assemble_hw_scaling_list(&run, &tbl->scaling_list); - assemble_hw_pps(ctx, &run); - lookup_ref_buf_idx(ctx, &run); -- assemble_hw_rps(ctx, &reflist_builder, &run); -+ assemble_hw_rps(&reflist_builder, &run, &h264_ctx->reflists, &tbl->rps); - config_registers(ctx, &run); - - rkvdec_run_postamble(ctx, &run.base); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Fri, 15 Aug 2025 17:24:37 -0400 -Subject: media: rkvdec: Move hevc functions to common file - -This is a preparation commit to add support for new variants of the -decoder. - -The functions will later be shared with vdpu381 (rk3588) and vdpu383 -(rk3576). - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c | 230 +++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h | 46 ++ - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 240 +--------- - 3 files changed, 282 insertions(+), 234 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -@@ -0,0 +1,230 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip video decoder hevc common functions -+ * -+ * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova -+ * -+ * Copyright (C) 2023 Collabora, Ltd. -+ * Sebastian Fricke -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Jeffy Chen -+ */ -+ -+#include "rkvdec.h" -+#include "rkvdec-hevc-common.h" -+ -+/* -+ * Flip one or more matrices along their main diagonal and flatten them -+ * before writing it to the memory. -+ * Convert: -+ * ABCD AEIM -+ * EFGH => BFJN => AEIMBFJNCGKODHLP -+ * IJKL CGKO -+ * MNOP DHLP -+ */ -+static void transpose_and_flatten_matrices(u8 *output, const u8 *input, -+ int matrices, int row_length) -+{ -+ int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value; -+ -+ matrix_size = row_length * row_length; -+ for (i = 0; i < matrices; i++) { -+ row = 0; -+ x_offset = 0; -+ matrix_offset = i * matrix_size; -+ for (j = 0; j < matrix_size; j++) { -+ y_offset = j - (row * row_length); -+ rot_index = y_offset * row_length + x_offset; -+ new_value = *(input + i * matrix_size + j); -+ output[matrix_offset + rot_index] = new_value; -+ if ((j + 1) % row_length == 0) { -+ row += 1; -+ x_offset += 1; -+ } -+ } -+ } -+} -+ -+static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ int offset = 0; -+ -+ transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); -+ offset = 6 * 16 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); -+ offset += 6 * 64 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_16x16, 6, 8); -+ offset += 6 * 64 * sizeof(u8); -+ /* Add a 128 byte padding with 0s between the two 32x32 matrices */ -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_32x32, 1, 8); -+ offset += 64 * sizeof(u8); -+ memset(output + offset, 0, 128); -+ offset += 128 * sizeof(u8); -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), -+ 1, 8); -+ offset += 64 * sizeof(u8); -+ memset(output + offset, 0, 128); -+} -+ -+/* -+ * Required layout: -+ * A = scaling_list_dc_coef_16x16 -+ * B = scaling_list_dc_coef_32x32 -+ * 0 = Padding -+ * -+ * A, A, A, A, A, A, B, 0, 0, B, 0, 0 -+ */ -+static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ u8 list_32x32[6] = {0}; -+ -+ memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8)); -+ list_32x32[0] = input->scaling_list_dc_coef_32x32[0]; -+ list_32x32[3] = input->scaling_list_dc_coef_32x32[1]; -+ memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); -+} -+ -+static void translate_scaling_list(struct scaling_factor *output, -+ const struct v4l2_ctrl_hevc_scaling_matrix *input) -+{ -+ assemble_scalingfactor0(output->scalingfactor0, input); -+ memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); -+ assemble_scalingdc(output->scalingdc, input); -+ memset(output->reserved, 0, 4 * sizeof(u8)); -+} -+ -+void assemble_hw_scaling_list(struct rkvdec_hevc_run *run, -+ struct scaling_factor *scaling_factor, -+ struct v4l2_ctrl_hevc_scaling_matrix *cache) -+{ -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; -+ -+ if (!memcmp(cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) -+ return; -+ -+ translate_scaling_list(scaling_factor, scaling); -+ -+ memcpy(cache, scaling, -+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); -+} -+ -+struct vb2_buffer * -+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx) -+{ -+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -+ struct vb2_buffer *buf = NULL; -+ -+ if (dpb_idx < decode_params->num_active_dpb_entries) -+ buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); -+ -+ /* -+ * If a DPB entry is unused or invalid, the address of current destination -+ * buffer is returned. -+ */ -+ if (!buf) -+ return &run->base.bufs.dst->vb2_buf; -+ -+ return buf; -+} -+ -+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -+ -+int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f) -+{ -+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -+ -+ fmt->num_planes = 1; -+ if (!fmt->plane_fmt[0].sizeimage) -+ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -+ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; -+ return 0; -+} -+ -+enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS) -+ return RKVDEC_IMG_FMT_ANY; -+ -+ if (sps->bit_depth_luma_minus8 == 0) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_8BIT; -+ else -+ return RKVDEC_IMG_FMT_420_8BIT; -+ } else if (sps->bit_depth_luma_minus8 == 2) { -+ if (sps->chroma_format_idc == 2) -+ return RKVDEC_IMG_FMT_422_10BIT; -+ else -+ return RKVDEC_IMG_FMT_420_10BIT; -+ } -+ -+ return RKVDEC_IMG_FMT_ANY; -+} -+ -+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+ const struct v4l2_ctrl_hevc_sps *sps) -+{ -+ if (sps->chroma_format_idc > 1) -+ /* Only 4:0:0 and 4:2:0 are supported */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -+ /* Luma and chroma bit depth mismatch */ -+ return -EINVAL; -+ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -+ /* Only 8-bit and 10-bit is supported */ -+ return -EINVAL; -+ -+ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -+ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct v4l2_ctrl *ctrl; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); -+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); -+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -+ run->num_slices = ctrl ? ctrl->new_elems : 0; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ run->sps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_PPS); -+ run->pps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); -+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ -+ rkvdec_run_preamble(ctx, &run->base); -+} -+ -+int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -+ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ -+ return 0; -+} -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h -@@ -0,0 +1,46 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Rockchip video decoder hevc common functions -+ * -+ * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova -+ * -+ * Copyright (C) 2023 Collabora, Ltd. -+ * Sebastian Fricke -+ * -+ * Copyright (C) 2019 Collabora, Ltd. -+ * Boris Brezillon -+ * -+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. -+ * Jeffy Chen -+ */ -+ -+struct rkvdec_hevc_run { -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -+ int num_slices; -+}; -+ -+struct scaling_factor { -+ u8 scalingfactor0[1248]; -+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ -+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/ -+ u8 reserved[4]; /*16Bytes align*/ -+}; -+ -+enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl); -+void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_hevc_run *run, -+ struct scaling_factor *scaling_factor, -+ struct v4l2_ctrl_hevc_scaling_matrix *cache); -+struct vb2_buffer *get_ref_buf(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx); -+int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f); -+//int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, const struct v4l2_ctrl_hevc_sps *sps); -+int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); -+void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run); -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -@@ -16,6 +16,7 @@ - - #include "rkvdec.h" - #include "rkvdec-regs.h" -+#include "rkvdec-hevc-common.h" - - /* Size in u8/u32 units. */ - #define RKV_SCALING_LIST_SIZE 1360 -@@ -113,34 +114,17 @@ struct rkvdec_ps_field { - /* Data structure describing auxiliary buffer format. */ - struct rkvdec_hevc_priv_tbl { - u8 cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; -- u8 scaling_list[RKV_SCALING_LIST_SIZE]; -+ struct scaling_factor scaling_list; - struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; - struct rkvdec_rps_packet rps[RKV_RPS_LEN]; - }; - --struct rkvdec_hevc_run { -- struct rkvdec_run base; -- const struct v4l2_ctrl_hevc_slice_params *slices_params; -- const struct v4l2_ctrl_hevc_decode_params *decode_params; -- const struct v4l2_ctrl_hevc_sps *sps; -- const struct v4l2_ctrl_hevc_pps *pps; -- const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -- int num_slices; --}; -- - struct rkvdec_hevc_ctx { - struct rkvdec_aux_buf priv_tbl; - struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; - struct rkvdec_regs regs; - }; - --struct scaling_factor { -- u8 scalingfactor0[1248]; -- u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ -- u8 scalingdc[12]; /*N1005 Vienna Meeting*/ -- u8 reserved[4]; /*16Bytes align*/ --}; -- - static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) - { - u8 bit = field.offset % 32, word = field.offset / 32; -@@ -417,131 +401,6 @@ static void assemble_hw_rps(struct rkvdec_ctx *ctx, - } - } - --/* -- * Flip one or more matrices along their main diagonal and flatten them -- * before writing it to the memory. -- * Convert: -- * ABCD AEIM -- * EFGH => BFJN => AEIMBFJNCGKODHLP -- * IJKL CGKO -- * MNOP DHLP -- */ --static void transpose_and_flatten_matrices(u8 *output, const u8 *input, -- int matrices, int row_length) --{ -- int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value; -- -- matrix_size = row_length * row_length; -- for (i = 0; i < matrices; i++) { -- row = 0; -- x_offset = 0; -- matrix_offset = i * matrix_size; -- for (j = 0; j < matrix_size; j++) { -- y_offset = j - (row * row_length); -- rot_index = y_offset * row_length + x_offset; -- new_value = *(input + i * matrix_size + j); -- output[matrix_offset + rot_index] = new_value; -- if ((j + 1) % row_length == 0) { -- row += 1; -- x_offset += 1; -- } -- } -- } --} -- --static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) --{ -- int offset = 0; -- -- transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); -- offset = 6 * 16 * sizeof(u8); -- transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); -- offset += 6 * 64 * sizeof(u8); -- transpose_and_flatten_matrices(output + offset, -- (const u8 *)input->scaling_list_16x16, 6, 8); -- offset += 6 * 64 * sizeof(u8); -- /* Add a 128 byte padding with 0s between the two 32x32 matrices */ -- transpose_and_flatten_matrices(output + offset, -- (const u8 *)input->scaling_list_32x32, 1, 8); -- offset += 64 * sizeof(u8); -- memset(output + offset, 0, 128); -- offset += 128 * sizeof(u8); -- transpose_and_flatten_matrices(output + offset, -- (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), -- 1, 8); -- offset += 64 * sizeof(u8); -- memset(output + offset, 0, 128); --} -- --/* -- * Required layout: -- * A = scaling_list_dc_coef_16x16 -- * B = scaling_list_dc_coef_32x32 -- * 0 = Padding -- * -- * A, A, A, A, A, A, B, 0, 0, B, 0, 0 -- */ --static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) --{ -- u8 list_32x32[6] = {0}; -- -- memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8)); -- list_32x32[0] = input->scaling_list_dc_coef_32x32[0]; -- list_32x32[3] = input->scaling_list_dc_coef_32x32[1]; -- memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); --} -- --static void translate_scaling_list(struct scaling_factor *output, -- const struct v4l2_ctrl_hevc_scaling_matrix *input) --{ -- assemble_scalingfactor0(output->scalingfactor0, input); -- memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); -- assemble_scalingdc(output->scalingdc, input); -- memset(output->reserved, 0, 4 * sizeof(u8)); --} -- --static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, -- struct rkvdec_hevc_run *run) --{ -- const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; -- struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -- struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -- u8 *dst; -- -- if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling, -- sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) -- return; -- -- dst = tbl->scaling_list; -- translate_scaling_list((struct scaling_factor *)dst, scaling); -- -- memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling, -- sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); --} -- --static struct vb2_buffer * --get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -- unsigned int dpb_idx) --{ -- struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; -- const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -- const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; -- struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; -- struct vb2_buffer *buf = NULL; -- -- if (dpb_idx < decode_params->num_active_dpb_entries) -- buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); -- -- /* -- * If a DPB entry is unused or invalid, the address of current destination -- * buffer is returned. -- */ -- if (!buf) -- return &run->base.bufs.dst->vb2_buf; -- -- return buf; --} -- - static void config_registers(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run) - { -@@ -645,63 +504,6 @@ static void config_registers(struct rkvdec_ctx *ctx, - rkvdec_memcpy_toio(rkvdec->regs, regs, sizeof(*regs)); - } - --#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -- --static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, -- struct v4l2_format *f) --{ -- struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; -- -- fmt->num_planes = 1; -- if (!fmt->plane_fmt[0].sizeimage) -- fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * -- RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; -- return 0; --} -- --static enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -- struct v4l2_ctrl *ctrl) --{ -- const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -- -- if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS) -- return RKVDEC_IMG_FMT_ANY; -- -- if (sps->bit_depth_luma_minus8 == 0) { -- if (sps->chroma_format_idc == 2) -- return RKVDEC_IMG_FMT_422_8BIT; -- else -- return RKVDEC_IMG_FMT_420_8BIT; -- } else if (sps->bit_depth_luma_minus8 == 2) { -- if (sps->chroma_format_idc == 2) -- return RKVDEC_IMG_FMT_422_10BIT; -- else -- return RKVDEC_IMG_FMT_420_10BIT; -- } -- -- return RKVDEC_IMG_FMT_ANY; --} -- --static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -- const struct v4l2_ctrl_hevc_sps *sps) --{ -- if (sps->chroma_format_idc > 1) -- /* Only 4:0:0 and 4:2:0 are supported */ -- return -EINVAL; -- if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -- /* Luma and chroma bit depth mismatch */ -- return -EINVAL; -- if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -- /* Only 8-bit and 10-bit is supported */ -- return -EINVAL; -- -- if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -- sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) -- return -EINVAL; -- -- return 0; --} -- - static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) - { - struct rkvdec_dev *rkvdec = ctx->dev; -@@ -738,40 +540,18 @@ static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) - kfree(hevc_ctx); - } - --static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -- struct rkvdec_hevc_run *run) --{ -- struct v4l2_ctrl *ctrl; -- -- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -- V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); -- run->decode_params = ctrl ? ctrl->p_cur.p : NULL; -- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -- V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); -- run->slices_params = ctrl ? ctrl->p_cur.p : NULL; -- run->num_slices = ctrl ? ctrl->new_elems : 0; -- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -- V4L2_CID_STATELESS_HEVC_SPS); -- run->sps = ctrl ? ctrl->p_cur.p : NULL; -- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -- V4L2_CID_STATELESS_HEVC_PPS); -- run->pps = ctrl ? ctrl->p_cur.p : NULL; -- ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -- V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); -- run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -- -- rkvdec_run_preamble(ctx, &run->base); --} -- - static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - { - struct rkvdec_dev *rkvdec = ctx->dev; - struct rkvdec_hevc_run run; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; - u32 reg; - - rkvdec_hevc_run_preamble(ctx, &run); - -- assemble_hw_scaling_list(ctx, &run); -+ rkvdec_hevc_assemble_hw_scaling_list(&run, &tbl->scaling_list, -+ &hevc_ctx->scaling_matrix_cache); - assemble_hw_pps(ctx, &run); - assemble_hw_rps(ctx, &run); - config_registers(ctx, &run); -@@ -802,14 +582,6 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - return 0; - } - --static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) --{ -- if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) -- return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -- -- return 0; --} -- - const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { - .adjust_fmt = rkvdec_hevc_adjust_fmt, - .start = rkvdec_hevc_start, --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Tue, 10 Jun 2025 14:05:08 -0400 -Subject: media: rkvdec: Add per variant configuration - -This is to prepare for adding different variants of the decoder and -support specific formats and ops. - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 31 +++++++--- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 7 +++ - 2 files changed, 28 insertions(+), 10 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -390,12 +390,13 @@ rkvdec_enum_coded_fmt_desc(struct rkvdec_ctx *ctx, int index) - static const struct rkvdec_coded_fmt_desc * - rkvdec_find_coded_fmt_desc(struct rkvdec_ctx *ctx, u32 fourcc) - { -+ const struct rkvdec_config *cfg = ctx->dev->config; - unsigned int i; - -- for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability) && -- rkvdec_coded_fmts[i].fourcc == fourcc) -- return &rkvdec_coded_fmts[i]; -+ for (i = 0; i < cfg->coded_fmts_num; i++) { -+ if (rkvdec_is_capable(ctx, cfg->coded_fmts[i].capability) && -+ cfg->coded_fmts[i].fourcc == fourcc) -+ return &cfg->coded_fmts[i]; - } - - return NULL; -@@ -1003,18 +1004,19 @@ static int rkvdec_add_ctrls(struct rkvdec_ctx *ctx, - - static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) - { -+ const struct rkvdec_config *cfg = ctx->dev->config; - unsigned int i, nctrls = 0; - int ret; - -- for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) -- if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) -- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; -+ for (i = 0; i < cfg->coded_fmts_num; i++) -+ if (rkvdec_is_capable(ctx, cfg->coded_fmts[i].capability)) -+ nctrls += cfg->coded_fmts[i].ctrls->num_ctrls; - - v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); - -- for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { -- if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) { -- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); -+ for (i = 0; i < cfg->coded_fmts_num; i++) { -+ if (rkvdec_is_capable(ctx, cfg->coded_fmts[i].capability)) { -+ ret = rkvdec_add_ctrls(ctx, cfg->coded_fmts[i].ctrls); - if (ret) - goto err_free_handler; - } -@@ -1230,11 +1232,18 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+static const struct rkvdec_config config_rkvdec = { -+ .coded_fmts = (struct rkvdec_coded_fmt_desc *)rkvdec_coded_fmts, -+ .coded_fmts_num = ARRAY_SIZE(rkvdec_coded_fmts), -+}; -+ - static const struct rkvdec_variant rk3288_rkvdec_variant = { -+ .config = &config_rkvdec, - .capabilities = RKVDEC_CAPABILITY_HEVC, - }; - - static const struct rkvdec_variant rk3328_rkvdec_variant = { -+ .config = &config_rkvdec, - .capabilities = RKVDEC_CAPABILITY_HEVC | - RKVDEC_CAPABILITY_H264 | - RKVDEC_CAPABILITY_VP9, -@@ -1242,6 +1251,7 @@ static const struct rkvdec_variant rk3328_rkvdec_variant = { - }; - - static const struct rkvdec_variant rk3399_rkvdec_variant = { -+ .config = &config_rkvdec, - .capabilities = RKVDEC_CAPABILITY_HEVC | - RKVDEC_CAPABILITY_H264 | - RKVDEC_CAPABILITY_VP9, -@@ -1285,6 +1295,7 @@ static int rkvdec_probe(struct platform_device *pdev) - - platform_set_drvdata(pdev, rkvdec); - rkvdec->dev = &pdev->dev; -+ rkvdec->config = variant->config; - rkvdec->capabilities = variant->capabilities; - rkvdec->quirks = variant->quirks; - mutex_init(&rkvdec->vdev_lock); -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -70,6 +70,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) - } - - struct rkvdec_variant { -+ const struct rkvdec_config *config; - unsigned int capabilities; - unsigned int quirks; - }; -@@ -112,6 +113,11 @@ struct rkvdec_coded_fmt_desc { - unsigned int capability; - }; - -+struct rkvdec_config { -+ struct rkvdec_coded_fmt_desc *coded_fmts; -+ size_t coded_fmts_num; -+}; -+ - struct rkvdec_dev { - struct v4l2_device v4l2_dev; - struct media_device mdev; -@@ -125,6 +131,7 @@ struct rkvdec_dev { - struct iommu_domain *empty_domain; - unsigned int capabilities; - unsigned int quirks; -+ const struct rkvdec_config *config; - }; - - struct rkvdec_ctx { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Tue, 10 Jun 2025 14:53:27 -0400 -Subject: media: rkvdec: Add RCB and SRAM support - -The RCB (Rows and Cols Buffers) are a set of buffers used by other -variations of the decoder to store temporary data. - -Those variation come with a dedicated SRAM area used to store those -buffers for better performances. - -The buffer sizes are either the width or height of the frame being -decoded multiplied by a documented factor and can be stored either -in SRAM or RAM. -A fallback to RAM is provided if the SRAM is full (e.g.: multiple -streams are being decoded at the same time). - -To manage the different kind of allocation, an enum is added to the -rkvdec_aux_buf struct to specify how the buffer was allocated, and -so, how to free it. - -This commit is in preparation of other variants support. - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/Makefile | 1 + - drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c | 174 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.h | 29 ++ - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 29 +- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 13 + - 5 files changed, 242 insertions(+), 4 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/Makefile -+++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -6,4 +6,5 @@ rockchip-vdec-y += \ - rkvdec-h264.o \ - rkvdec-h264-common.o \ - rkvdec-hevc.o \ -+ rkvdec-rcb.o \ - rkvdec-vp9.o -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.c -@@ -0,0 +1,174 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip video decoder Rows and Cols Buffers manager -+ * -+ * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#include "rkvdec.h" -+#include "rkvdec-rcb.h" -+ -+#include -+#include -+#include -+ -+struct rkvdec_rcb_config { -+ struct rkvdec_aux_buf *rcb_bufs; -+ size_t rcb_count; -+}; -+ -+static size_t rkvdec_rcb_size(const struct rcb_size_info *size_info, -+ unsigned int width, unsigned int height) -+{ -+ return size_info->multiplier * (size_info->axis == PIC_HEIGHT ? height : width); -+} -+ -+dma_addr_t rkvdec_rcb_buf_dma_addr(struct rkvdec_ctx *ctx, int id) -+{ -+ return ctx->rcb_config->rcb_bufs[id].dma; -+} -+ -+size_t rkvdec_rcb_buf_size(struct rkvdec_ctx *ctx, int id) -+{ -+ return ctx->rcb_config->rcb_bufs[id].size; -+} -+ -+int rkvdec_rcb_buf_count(struct rkvdec_ctx *ctx) -+{ -+ return ctx->rcb_config->rcb_count; -+} -+ -+void rkvdec_free_rcb(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *dev = ctx->dev; -+ struct rkvdec_rcb_config *cfg = ctx->rcb_config; -+ unsigned long virt_addr; -+ int i; -+ -+ if (!cfg) -+ return; -+ -+ for (i = 0; i < cfg->rcb_count; i++) { -+ size_t rcb_size = cfg->rcb_bufs[i].size; -+ -+ if (!cfg->rcb_bufs[i].cpu) -+ continue; -+ -+ switch (cfg->rcb_bufs[i].type) { -+ case RKVDEC2_ALLOC_SRAM: -+ virt_addr = (unsigned long)cfg->rcb_bufs[i].cpu; -+ -+ if (dev->iommu_domain) -+ iommu_unmap(dev->iommu_domain, virt_addr, rcb_size); -+ gen_pool_free(dev->sram_pool, virt_addr, rcb_size); -+ break; -+ case RKVDEC2_ALLOC_DMA: -+ dma_free_coherent(dev->dev, -+ rcb_size, -+ cfg->rcb_bufs[i].cpu, -+ cfg->rcb_bufs[i].dma); -+ break; -+ } -+ } -+ -+ if (cfg->rcb_bufs) -+ devm_kfree(dev->dev, cfg->rcb_bufs); -+ -+ devm_kfree(dev->dev, cfg); -+} -+ -+int rkvdec_allocate_rcb(struct rkvdec_ctx *ctx, -+ const struct rcb_size_info *size_info, -+ size_t rcb_count) -+{ -+ int ret, i; -+ u32 width, height; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_rcb_config *cfg; -+ -+ ctx->rcb_config = devm_kzalloc(rkvdec->dev, sizeof(*ctx->rcb_config), GFP_KERNEL); -+ if (!ctx->rcb_config) -+ return -ENOMEM; -+ -+ cfg = ctx->rcb_config; -+ -+ cfg->rcb_bufs = devm_kzalloc(rkvdec->dev, sizeof(*cfg->rcb_bufs) * rcb_count, GFP_KERNEL); -+ if (!cfg->rcb_bufs) { -+ ret = -ENOMEM; -+ goto err_alloc; -+ } -+ -+ width = ctx->decoded_fmt.fmt.pix_mp.width; -+ height = ctx->decoded_fmt.fmt.pix_mp.height; -+ -+ for (i = 0; i < rcb_count; i++) { -+ void *cpu = NULL; -+ dma_addr_t dma; -+ size_t rcb_size = rkvdec_rcb_size(&size_info[i], width, height); -+ enum rkvdec_alloc_type alloc_type = RKVDEC2_ALLOC_SRAM; -+ -+ /* Try allocating an SRAM buffer */ -+ if (ctx->dev->sram_pool) { -+ if (rkvdec->iommu_domain) -+ rcb_size = ALIGN(rcb_size, 0x1000); -+ -+ cpu = gen_pool_dma_zalloc_align(ctx->dev->sram_pool, -+ rcb_size, -+ &dma, -+ 0x1000); -+ } -+ -+ /* If an IOMMU is used, map the SRAM address through it */ -+ if (cpu && rkvdec->iommu_domain) { -+ unsigned long virt_addr = (unsigned long)cpu; -+ phys_addr_t phys_addr = dma; -+ -+ ret = iommu_map(rkvdec->iommu_domain, virt_addr, phys_addr, -+ rcb_size, IOMMU_READ | IOMMU_WRITE, 0); -+ if (ret) { -+ gen_pool_free(ctx->dev->sram_pool, -+ (unsigned long)cpu, -+ rcb_size); -+ cpu = NULL; -+ goto ram_fallback; -+ } -+ -+ /* -+ * The registers will be configured with the virtual -+ * address so that it goes through the IOMMU -+ */ -+ dma = virt_addr; -+ } -+ -+ram_fallback: -+ /* Fallback to RAM */ -+ if (!cpu) { -+ cpu = dma_alloc_coherent(ctx->dev->dev, -+ rcb_size, -+ &dma, -+ GFP_KERNEL); -+ alloc_type = RKVDEC2_ALLOC_DMA; -+ } -+ -+ if (!cpu) { -+ ret = -ENOMEM; -+ goto err_alloc; -+ } -+ -+ cfg->rcb_bufs[i].cpu = cpu; -+ cfg->rcb_bufs[i].dma = dma; -+ cfg->rcb_bufs[i].size = rcb_size; -+ cfg->rcb_bufs[i].type = alloc_type; -+ -+ cfg->rcb_count += 1; -+ } -+ -+ return 0; -+ -+err_alloc: -+ rkvdec_free_rcb(ctx); -+ -+ return ret; -+} -+ -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-rcb.h -@@ -0,0 +1,29 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Rockchip video decoder Rows and Cols Buffers manager -+ * -+ * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#include -+ -+struct rkvdec_ctx; -+ -+enum rcb_axis { -+ PIC_WIDTH = 0, -+ PIC_HEIGHT = 1 -+}; -+ -+struct rcb_size_info { -+ u8 multiplier; -+ enum rcb_axis axis; -+}; -+ -+int rkvdec_allocate_rcb(struct rkvdec_ctx *ctx, -+ const struct rcb_size_info *size_info, -+ size_t rcb_count); -+dma_addr_t rkvdec_rcb_buf_dma_addr(struct rkvdec_ctx *ctx, int id); -+size_t rkvdec_rcb_buf_size(struct rkvdec_ctx *ctx, int id); -+int rkvdec_rcb_buf_count(struct rkvdec_ctx *ctx); -+void rkvdec_free_rcb(struct rkvdec_ctx *ctx); -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -10,6 +10,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -28,6 +29,7 @@ - - #include "rkvdec.h" - #include "rkvdec-regs.h" -+#include "rkvdec-rcb.h" - - static bool rkvdec_image_fmt_match(enum rkvdec_image_fmt fmt1, - enum rkvdec_image_fmt fmt2) -@@ -770,6 +772,7 @@ static int rkvdec_start_streaming(struct vb2_queue *q, unsigned int count) - { - struct rkvdec_ctx *ctx = vb2_get_drv_priv(q); - const struct rkvdec_coded_fmt_desc *desc; -+ const struct rkvdec_config *cfg = ctx->dev->config; - int ret; - - if (V4L2_TYPE_IS_CAPTURE(q->type)) -@@ -779,13 +782,22 @@ static int rkvdec_start_streaming(struct vb2_queue *q, unsigned int count) - if (WARN_ON(!desc)) - return -EINVAL; - -+ ret = rkvdec_allocate_rcb(ctx, cfg->rcb_size_info, cfg->rcb_num); -+ if (ret) -+ return ret; -+ - if (desc->ops->start) { - ret = desc->ops->start(ctx); - if (ret) -- return ret; -+ goto err_ops_start; - } - - return 0; -+ -+err_ops_start: -+ rkvdec_free_rcb(ctx); -+ -+ return ret; - } - - static void rkvdec_queue_cleanup(struct vb2_queue *vq, u32 state) -@@ -821,6 +833,8 @@ static void rkvdec_stop_streaming(struct vb2_queue *q) - - if (desc->ops->stop) - desc->ops->stop(ctx); -+ -+ rkvdec_free_rcb(ctx); - } - - rkvdec_queue_cleanup(q, VB2_BUF_STATE_ERROR); -@@ -1324,15 +1338,14 @@ static int rkvdec_probe(struct platform_device *pdev) - return ret; - } - -- if (iommu_get_domain_for_dev(&pdev->dev)) { -+ rkvdec->iommu_domain = iommu_get_domain_for_dev(&pdev->dev); -+ if (rkvdec->iommu_domain) { - rkvdec->empty_domain = iommu_paging_domain_alloc(rkvdec->dev); - - if (!rkvdec->empty_domain) - dev_warn(rkvdec->dev, "cannot alloc new empty domain\n"); - } - -- vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); -- - irq = platform_get_irq(pdev, 0); - if (irq <= 0) - return -ENXIO; -@@ -1345,6 +1358,10 @@ static int rkvdec_probe(struct platform_device *pdev) - return ret; - } - -+ rkvdec->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0); -+ if (!rkvdec->sram_pool && rkvdec->config->rcb_num > 0) -+ dev_info(&pdev->dev, "No sram node, RCB will be stored in RAM\n"); -+ - pm_runtime_set_autosuspend_delay(&pdev->dev, 100); - pm_runtime_use_autosuspend(&pdev->dev); - pm_runtime_enable(&pdev->dev); -@@ -1358,6 +1375,10 @@ static int rkvdec_probe(struct platform_device *pdev) - err_disable_runtime_pm: - pm_runtime_dont_use_autosuspend(&pdev->dev); - pm_runtime_disable(&pdev->dev); -+ -+ if (rkvdec->sram_pool) -+ gen_pool_destroy(rkvdec->sram_pool); -+ - return ret; - } - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -29,6 +30,7 @@ - #define RKVDEC_QUIRK_DISABLE_QOS BIT(0) - - struct rkvdec_ctx; -+struct rkvdec_rcb_config; - - struct rkvdec_ctrl_desc { - struct v4l2_ctrl_config cfg; -@@ -116,6 +118,8 @@ struct rkvdec_coded_fmt_desc { - struct rkvdec_config { - struct rkvdec_coded_fmt_desc *coded_fmts; - size_t coded_fmts_num; -+ struct rcb_size_info *rcb_size_info; -+ size_t rcb_num; - }; - - struct rkvdec_dev { -@@ -128,6 +132,8 @@ struct rkvdec_dev { - void __iomem *regs; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; -+ struct gen_pool *sram_pool; -+ struct iommu_domain *iommu_domain; - struct iommu_domain *empty_domain; - unsigned int capabilities; - unsigned int quirks; -@@ -142,6 +148,7 @@ struct rkvdec_ctx { - struct v4l2_ctrl_handler ctrl_hdl; - struct rkvdec_dev *dev; - enum rkvdec_image_fmt image_fmt; -+ struct rkvdec_rcb_config *rcb_config; - void *priv; - }; - -@@ -150,10 +157,16 @@ static inline struct rkvdec_ctx *fh_to_rkvdec_ctx(struct v4l2_fh *fh) - return container_of(fh, struct rkvdec_ctx, fh); - } - -+enum rkvdec_alloc_type { -+ RKVDEC2_ALLOC_DMA = 0, -+ RKVDEC2_ALLOC_SRAM = 1, -+}; -+ - struct rkvdec_aux_buf { - void *cpu; - dma_addr_t dma; - size_t size; -+ enum rkvdec_alloc_type type; - }; - - void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Tue, 10 Jun 2025 15:13:46 -0400 -Subject: media: rkvdec: Support per-variant interrupt handler - -Preparation commit for supporting different variants with different -interrupt management. - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 15 ++++++++-- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 1 + - 2 files changed, 13 insertions(+), 3 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -1207,10 +1207,9 @@ static void rkvdec_iommu_restore(struct rkvdec_dev *rkvdec) - } - } - --static irqreturn_t rkvdec_irq_handler(int irq, void *priv) -+static irqreturn_t rk3399_irq_handler(struct rkvdec_ctx *ctx) - { -- struct rkvdec_dev *rkvdec = priv; -- struct rkvdec_ctx *ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); -+ struct rkvdec_dev *rkvdec = ctx->dev; - enum vb2_buffer_state state; - u32 status; - -@@ -1231,6 +1230,15 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - return IRQ_HANDLED; - } - -+static irqreturn_t rkvdec_irq_handler(int irq, void *priv) -+{ -+ struct rkvdec_dev *rkvdec = priv; -+ struct rkvdec_ctx *ctx = v4l2_m2m_get_curr_priv(rkvdec->m2m_dev); -+ const struct rkvdec_config *cfg = rkvdec->config; -+ -+ return cfg->irq_handler(ctx); -+} -+ - static void rkvdec_watchdog_func(struct work_struct *work) - { - struct rkvdec_dev *rkvdec; -@@ -1249,6 +1257,7 @@ static void rkvdec_watchdog_func(struct work_struct *work) - static const struct rkvdec_config config_rkvdec = { - .coded_fmts = (struct rkvdec_coded_fmt_desc *)rkvdec_coded_fmts, - .coded_fmts_num = ARRAY_SIZE(rkvdec_coded_fmts), -+ .irq_handler = rk3399_irq_handler, - }; - - static const struct rkvdec_variant rk3288_rkvdec_variant = { -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -120,6 +120,7 @@ struct rkvdec_config { - size_t coded_fmts_num; - struct rcb_size_info *rcb_size_info; - size_t rcb_num; -+ irqreturn_t (*irq_handler)(struct rkvdec_ctx *ctx); - }; - - struct rkvdec_dev { --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Tue, 10 Jun 2025 16:40:09 -0400 -Subject: media: rkvdec: Enable all clocks without naming them - -For other variants, the clock names and number will differ. - -There is no need to keep track of the clock names in the driver so drop -them to avoid having a list for each variant. - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 24 +++------- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 1 + - 2 files changed, 7 insertions(+), 18 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -1297,15 +1297,10 @@ static const struct of_device_id of_rkvdec_match[] = { - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); - --static const char * const rkvdec_clk_names[] = { -- "axi", "ahb", "cabac", "core" --}; -- - static int rkvdec_probe(struct platform_device *pdev) - { - const struct rkvdec_variant *variant; - struct rkvdec_dev *rkvdec; -- unsigned int i; - int ret, irq; - - variant = of_device_get_match_data(&pdev->dev); -@@ -1324,19 +1319,12 @@ static int rkvdec_probe(struct platform_device *pdev) - mutex_init(&rkvdec->vdev_lock); - INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); - -- rkvdec->clocks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(rkvdec_clk_names), -- sizeof(*rkvdec->clocks), GFP_KERNEL); -- if (!rkvdec->clocks) -- return -ENOMEM; -- -- for (i = 0; i < ARRAY_SIZE(rkvdec_clk_names); i++) -- rkvdec->clocks[i].id = rkvdec_clk_names[i]; -- -- ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(rkvdec_clk_names), -- rkvdec->clocks); -- if (ret) -+ ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &rkvdec->clocks); -+ if (ret < 0) - return ret; - -+ rkvdec->clk_count = ret; -+ - rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(rkvdec->regs)) - return PTR_ERR(rkvdec->regs); -@@ -1410,7 +1398,7 @@ static int rkvdec_runtime_resume(struct device *dev) - { - struct rkvdec_dev *rkvdec = dev_get_drvdata(dev); - -- return clk_bulk_prepare_enable(ARRAY_SIZE(rkvdec_clk_names), -+ return clk_bulk_prepare_enable(rkvdec->clk_count, - rkvdec->clocks); - } - -@@ -1418,7 +1406,7 @@ static int rkvdec_runtime_suspend(struct device *dev) - { - struct rkvdec_dev *rkvdec = dev_get_drvdata(dev); - -- clk_bulk_disable_unprepare(ARRAY_SIZE(rkvdec_clk_names), -+ clk_bulk_disable_unprepare(rkvdec->clk_count, - rkvdec->clocks); - return 0; - } -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -130,6 +130,7 @@ struct rkvdec_dev { - struct v4l2_m2m_dev *m2m_dev; - struct device *dev; - struct clk_bulk_data *clocks; -+ unsigned int clk_count; - void __iomem *regs; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Tue, 10 Jun 2025 15:53:52 -0400 -Subject: media: rkvdec: Add H264 support for the VDPU381 variant - -This decoder variant is found in Rockchip RK3588 SoC family. - -Like for rkvdec on rk3399, it supports the NV12, NV15, NV16 and NV20 -output formats and level up to 5.1. - -The maximum width and height have been significantly increased -supporting up to 65520 pixels for both. - -Also make sure to only expose the first core and ignore the other -until mutli-core is supported. - -Fluster score for JVT-AVC_V1 is 129/135. - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/Makefile | 1 + - drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h | 2 + - drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c | 2 - - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c | 469 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-regs.h | 427 +++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 173 +++- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 6 + - 7 files changed, 1076 insertions(+), 4 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/Makefile -+++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -7,4 +7,5 @@ rockchip-vdec-y += \ - rkvdec-h264-common.o \ - rkvdec-hevc.o \ - rkvdec-rcb.o \ -+ rkvdec-vdpu381-h264.o \ - rkvdec-vp9.o -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h -@@ -66,6 +66,8 @@ struct rkvdec_rps { - u32 reserved1[66]; - } __packed; - -+extern const s8 rkvdec_h264_cabac_table[4][464][2]; -+ - void lookup_ref_buf_idx(struct rkvdec_ctx *ctx, struct rkvdec_h264_run *run); - void assemble_hw_rps(struct v4l2_h264_reflist_builder *builder, - struct rkvdec_h264_run *run, -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c -@@ -16,8 +16,6 @@ - #include "rkvdec-regs.h" - #include "rkvdec-h264-common.h" - --extern const s8 rkvdec_h264_cabac_table[4][464][2]; -- - /* Size with u32 units. */ - #define RKV_CABAC_INIT_BUFFER_SIZE (3680 + 128) - #define RKV_ERROR_INFO_SIZE (256 * 144 * 4) -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-h264.c -@@ -0,0 +1,469 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip VDPU381 Video Decoder H264 backend -+ * -+ * Copyright (C) 2024 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#include -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-rcb.h" -+#include "rkvdec-h264-common.h" -+#include "rkvdec-vdpu381-regs.h" -+ -+struct rkvdec_sps { -+ u16 seq_parameter_set_id: 4; -+ u16 profile_idc: 8; -+ u16 constraint_set3_flag: 1; -+ u16 chroma_format_idc: 2; -+ u16 bit_depth_luma: 3; -+ u16 bit_depth_chroma: 3; -+ u16 qpprime_y_zero_transform_bypass_flag: 1; -+ u16 log2_max_frame_num_minus4: 4; -+ u16 max_num_ref_frames: 5; -+ u16 pic_order_cnt_type: 2; -+ u16 log2_max_pic_order_cnt_lsb_minus4: 4; -+ u16 delta_pic_order_always_zero_flag: 1; -+ u16 pic_width_in_mbs: 12; -+ u16 pic_height_in_mbs: 12; -+ u16 frame_mbs_only_flag: 1; -+ u16 mb_adaptive_frame_field_flag: 1; -+ u16 direct_8x8_inference_flag: 1; -+ u16 mvc_extension_enable: 1; -+ u16 num_views: 2; -+ -+ u16 reserved_bits: 12; -+ u16 reserved[11]; -+} __packed; -+ -+struct rkvdec_pps { -+ u16 pic_parameter_set_id: 8; -+ u16 pps_seq_parameter_set_id: 5; -+ u16 entropy_coding_mode_flag: 1; -+ u16 bottom_field_pic_order_in_frame_present_flag: 1; -+ u16 num_ref_idx_l0_default_active_minus1: 5; -+ u16 num_ref_idx_l1_default_active_minus1: 5; -+ u16 weighted_pred_flag: 1; -+ u16 weighted_bipred_idc: 2; -+ u16 pic_init_qp_minus26: 7; -+ u16 pic_init_qs_minus26: 6; -+ u16 chroma_qp_index_offset: 5; -+ u16 deblocking_filter_control_present_flag: 1; -+ u16 constrained_intra_pred_flag: 1; -+ u16 redundant_pic_cnt_present: 1; -+ u16 transform_8x8_mode_flag: 1; -+ u16 second_chroma_qp_index_offset: 5; -+ u16 scaling_list_enable_flag: 1; -+ u32 scaling_list_address; -+ u16 is_longterm; -+ -+ u8 reserved[3]; -+} __packed; -+ -+struct rkvdec_sps_pps { -+ struct rkvdec_sps sps; -+ struct rkvdec_pps pps; -+} __packed; -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_h264_priv_tbl { -+ s8 cabac_table[4][464][2]; -+ struct rkvdec_h264_scaling_list scaling_list; -+ struct rkvdec_sps_pps param_set[256]; -+ struct rkvdec_rps rps; -+}; -+ -+struct rkvdec_h264_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct rkvdec_h264_reflists reflists; -+ struct rkvdec_vdpu381_regs_h264 regs; -+}; -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_h264_run *run) -+{ -+ struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -+ const struct v4l2_ctrl_h264_sps *sps = run->sps; -+ const struct v4l2_ctrl_h264_pps *pps = run->pps; -+ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -+ const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; -+ struct rkvdec_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps *hw_ps; -+ dma_addr_t scaling_list_address; -+ u32 scaling_distance; -+ u32 i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 32 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ /* write sps */ -+ hw_ps->sps.seq_parameter_set_id = sps->seq_parameter_set_id; -+ hw_ps->sps.profile_idc = sps->profile_idc; -+ hw_ps->sps.constraint_set3_flag = !!(sps->constraint_set_flags & (1 << 3)); -+ hw_ps->sps.chroma_format_idc = sps->chroma_format_idc; -+ hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8; -+ hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8; -+ hw_ps->sps.qpprime_y_zero_transform_bypass_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS); -+ hw_ps->sps.log2_max_frame_num_minus4 = sps->log2_max_frame_num_minus4; -+ hw_ps->sps.max_num_ref_frames = sps->max_num_ref_frames; -+ hw_ps->sps.pic_order_cnt_type = sps->pic_order_cnt_type; -+ hw_ps->sps.log2_max_pic_order_cnt_lsb_minus4 = -+ sps->log2_max_pic_order_cnt_lsb_minus4; -+ hw_ps->sps.delta_pic_order_always_zero_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); -+ hw_ps->sps.mvc_extension_enable = 1; -+ hw_ps->sps.num_views = 1; -+ -+ /* -+ * Use the SPS values since they are already in macroblocks -+ * dimensions, height can be field height (halved) if -+ * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY is not set and also it allows -+ * decoding smaller images into larger allocation which can be used -+ * to implementing SVC spatial layer support. -+ */ -+ hw_ps->sps.pic_width_in_mbs = sps->pic_width_in_mbs_minus1 + 1; -+ hw_ps->sps.pic_height_in_mbs = sps->pic_height_in_map_units_minus1 + 1; -+ hw_ps->sps.frame_mbs_only_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); -+ hw_ps->sps.mb_adaptive_frame_field_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); -+ hw_ps->sps.direct_8x8_inference_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); -+ -+ /* write pps */ -+ hw_ps->pps.pic_parameter_set_id = pps->pic_parameter_set_id; -+ hw_ps->pps.pps_seq_parameter_set_id = pps->seq_parameter_set_id; -+ hw_ps->pps.entropy_coding_mode_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); -+ hw_ps->pps.bottom_field_pic_order_in_frame_present_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); -+ hw_ps->pps.num_ref_idx_l0_default_active_minus1 = -+ pps->num_ref_idx_l0_default_active_minus1; -+ hw_ps->pps.num_ref_idx_l1_default_active_minus1 = -+ pps->num_ref_idx_l1_default_active_minus1; -+ hw_ps->pps.weighted_pred_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED); -+ hw_ps->pps.weighted_bipred_idc = pps->weighted_bipred_idc; -+ hw_ps->pps.pic_init_qp_minus26 = pps->pic_init_qp_minus26; -+ hw_ps->pps.pic_init_qs_minus26 = pps->pic_init_qs_minus26; -+ hw_ps->pps.chroma_qp_index_offset = pps->chroma_qp_index_offset; -+ hw_ps->pps.deblocking_filter_control_present_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); -+ hw_ps->pps.constrained_intra_pred_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); -+ hw_ps->pps.redundant_pic_cnt_present = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); -+ hw_ps->pps.transform_8x8_mode_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); -+ hw_ps->pps.second_chroma_qp_index_offset = pps->second_chroma_qp_index_offset; -+ hw_ps->pps.scaling_list_enable_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT); -+ -+ /* -+ * To be on the safe side, program the scaling matrix address -+ */ -+ scaling_distance = offsetof(struct rkvdec_h264_priv_tbl, scaling_list); -+ scaling_list_address = h264_ctx->priv_tbl.dma + scaling_distance; -+ hw_ps->pps.scaling_list_address = scaling_list_address; -+ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -+ hw_ps->pps.is_longterm |= (1 << i); -+ } -+} -+ -+static void rkvdec_write_regs(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -+ -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_COMMON_REGS, -+ &h264_ctx->regs.common, -+ sizeof(h264_ctx->regs.common)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_CODEC_PARAMS_REGS, -+ &h264_ctx->regs.h264_param, -+ sizeof(h264_ctx->regs.h264_param)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_COMMON_ADDR_REGS, -+ &h264_ctx->regs.common_addr, -+ sizeof(h264_ctx->regs.common_addr)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_CODEC_ADDR_REGS, -+ &h264_ctx->regs.h264_addr, -+ sizeof(h264_ctx->regs.h264_addr)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_POC_HIGHBIT_REGS, -+ &h264_ctx->regs.h264_highpoc, -+ sizeof(h264_ctx->regs.h264_highpoc)); -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_h264_run *run) -+{ -+ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -+ const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; -+ struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -+ dma_addr_t priv_start_addr = h264_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ struct rkvdec_vdpu381_regs_h264 *regs = &h264_ctx->regs; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t dst_addr; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; -+ u32 offset; -+ u32 pixels; -+ u32 i; -+ -+ memset(regs, 0, sizeof(*regs)); -+ -+ /* Set H264 mode */ -+ regs->common.reg009.dec_mode = VDPU381_MODE_H264; -+ -+ /* Set config */ -+ regs->common.reg011.buf_empty_en = 1; -+ regs->common.reg011.dec_clkgate_e = 1; -+ regs->common.reg011.dec_timeout_e = 1; -+ regs->common.reg011.pix_range_detection_e = 1; -+ -+ /* -+ * Even though the scan list address can be set in RPS, -+ * with some frames, it will try to use the address set in the register. -+ */ -+ regs->common.reg012.scanlist_addr_valid_en = 1; -+ -+ /* Set IDR flag */ -+ regs->common.reg013.cur_pic_is_idr = -+ !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC); -+ -+ /* Set input stream length */ -+ regs->common.stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ -+ /* Set max slice number */ -+ regs->common.reg017.slice_num = MAX_SLICE_NUMBER; -+ -+ /* Set strides */ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ -+ pixels = dst_fmt->height * dst_fmt->width; -+ -+ regs->common.reg018.y_hor_virstride = hor_virstride / 16; -+ regs->common.reg019.uv_hor_virstride = hor_virstride / 16; -+ regs->common.reg020.y_virstride = y_virstride / 16; -+ -+ /* Activate block gating */ -+ regs->common.reg026.swreg_block_gating_e = 0xfffef; -+ regs->common.reg026.reg_cfg_gating_en = 1; -+ -+ /* Set timeout threshold */ -+ if (pixels < RKVDEC_1080P_PIXELS) -+ regs->common.timeout_threshold = RKVDEC_TIMEOUT_1080p; -+ else if (pixels < RKVDEC_4K_PIXELS) -+ regs->common.timeout_threshold = RKVDEC_TIMEOUT_4K; -+ else if (pixels < RKVDEC_8K_PIXELS) -+ regs->common.timeout_threshold = RKVDEC_TIMEOUT_8K; -+ else -+ regs->common.timeout_threshold = RKVDEC_TIMEOUT_MAX; -+ -+ /* Set TOP and BOTTOM POCs */ -+ regs->h264_param.cur_top_poc = dec_params->top_field_order_cnt; -+ regs->h264_param.cur_bot_poc = dec_params->bottom_field_order_cnt; -+ -+ /* Set ref pic address & poc */ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ struct vb2_buffer *vb_buf = run->ref_buf[i]; -+ dma_addr_t buf_dma; -+ -+ /* -+ * If a DPB entry is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ if (!vb_buf) -+ vb_buf = &dst_buf->vb2_buf; -+ -+ buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ -+ /* Set reference addresses */ -+ regs->h264_addr.ref_base[i] = buf_dma; -+ -+ /* Set COLMV addresses */ -+ regs->h264_addr.colmv_base[i] = buf_dma + ctx->colmv_offset; -+ -+ struct rkvdec_vdpu381_h264_ref_info *ref_info = -+ ®s->h264_param.ref_info_regs[i / 4].ref_info[i % 4]; -+ -+ ref_info->ref_field = -+ !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD); -+ ref_info->ref_colmv_use_flag = -+ !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE); -+ ref_info->ref_topfield_used = -+ !!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF); -+ ref_info->ref_botfield_used = -+ !!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF); -+ -+ regs->h264_param.ref_pocs[i * 2] = -+ dpb[i].top_field_order_cnt; -+ regs->h264_param.ref_pocs[i * 2 + 1] = -+ dpb[i].bottom_field_order_cnt; -+ } -+ -+ /* Set rlc base address (input stream) */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ regs->common_addr.rlc_base = rlc_addr; -+ regs->common_addr.rlcwrite_base = rlc_addr; -+ -+ /* Set output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ regs->common_addr.decout_base = dst_addr; -+ regs->common_addr.error_ref_base = dst_addr; -+ -+ /* Set colmv address */ -+ regs->common_addr.colmv_cur_base = dst_addr + ctx->colmv_offset; -+ -+ /* Set RCB addresses */ -+ for (i = 0; i < rkvdec_rcb_buf_count(ctx); i++) -+ regs->common_addr.rcb_base[i] = rkvdec_rcb_buf_dma_addr(ctx, i); -+ -+ /* Set hw pps address */ -+ offset = offsetof(struct rkvdec_h264_priv_tbl, param_set); -+ regs->h264_addr.pps_base = priv_start_addr + offset; -+ -+ /* Set hw rps address */ -+ offset = offsetof(struct rkvdec_h264_priv_tbl, rps); -+ regs->h264_addr.rps_base = priv_start_addr + offset; -+ -+ /* Set cabac table */ -+ offset = offsetof(struct rkvdec_h264_priv_tbl, cabac_table); -+ regs->h264_addr.cabactbl_base = priv_start_addr + offset; -+ -+ offset = offsetof(struct rkvdec_h264_priv_tbl, scaling_list); -+ regs->h264_addr.scanlist_addr = priv_start_addr + offset; -+ -+ rkvdec_write_regs(ctx); -+} -+ -+static int rkvdec_h264_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_h264_priv_tbl *priv_tbl; -+ struct rkvdec_h264_ctx *h264_ctx; -+ struct v4l2_ctrl *ctrl; -+ int ret; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); -+ if (ret) -+ return ret; -+ -+ h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL); -+ if (!h264_ctx) -+ return -ENOMEM; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &h264_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ h264_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ h264_ctx->priv_tbl.cpu = priv_tbl; -+ memcpy(priv_tbl->cabac_table, rkvdec_h264_cabac_table, -+ sizeof(rkvdec_h264_cabac_table)); -+ -+ ctx->priv = h264_ctx; -+ return 0; -+ -+err_free_ctx: -+ kfree(h264_ctx); -+ return ret; -+} -+ -+static void rkvdec_h264_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, h264_ctx->priv_tbl.size, -+ h264_ctx->priv_tbl.cpu, h264_ctx->priv_tbl.dma); -+ kfree(h264_ctx); -+} -+ -+static int rkvdec_h264_run(struct rkvdec_ctx *ctx) -+{ -+ struct v4l2_h264_reflist_builder reflist_builder; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -+ struct rkvdec_h264_priv_tbl *tbl = h264_ctx->priv_tbl.cpu; -+ struct rkvdec_h264_run run; -+ u32 watchdog_time; -+ -+ rkvdec_h264_run_preamble(ctx, &run); -+ -+ /* Build the P/B{0,1} ref lists. */ -+ v4l2_h264_init_reflist_builder(&reflist_builder, run.decode_params, -+ run.sps, run.decode_params->dpb); -+ v4l2_h264_build_p_ref_list(&reflist_builder, h264_ctx->reflists.p); -+ v4l2_h264_build_b_ref_lists(&reflist_builder, h264_ctx->reflists.b0, -+ h264_ctx->reflists.b1); -+ -+ assemble_hw_scaling_list(&run, &tbl->scaling_list); -+ assemble_hw_pps(ctx, &run); -+ lookup_ref_buf_idx(ctx, &run); -+ assemble_hw_rps(&reflist_builder, &run, &h264_ctx->reflists, &tbl->rps); -+ -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ /* Set watchdog at 2 times the hardware timeout threshold */ -+ u64 timeout_threshold = h264_ctx->regs.common.timeout_threshold; -+ unsigned long axi_rate = clk_get_rate(rkvdec->axi_clk); -+ -+ if (axi_rate) -+ watchdog_time = 2 * (1000 * timeout_threshold) / axi_rate; -+ else -+ watchdog_time = 2000; -+ schedule_delayed_work(&rkvdec->watchdog_work, -+ msecs_to_jiffies(watchdog_time)); -+ -+ /* Start decoding! */ -+ writel(VDPU381_DEC_E_BIT, rkvdec->regs + VDPU381_REG_DEC_E); -+ -+ return 0; -+} -+ -+static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) -+ return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_h264_fmt_ops = { -+ .adjust_fmt = rkvdec_h264_adjust_fmt, -+ .get_image_fmt = rkvdec_h264_get_image_fmt, -+ .start = rkvdec_h264_start, -+ .stop = rkvdec_h264_stop, -+ .run = rkvdec_h264_run, -+ .try_ctrl = rkvdec_h264_try_ctrl, -+}; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-regs.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-regs.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-regs.h -@@ -0,0 +1,427 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Rockchip VDPU381 Video Decoder driver registers description -+ * -+ * Copyright (C) 2024 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#include -+ -+#ifndef _RKVDEC_REGS_H_ -+#define _RKVDEC_REGS_H_ -+ -+#define OFFSET_COMMON_REGS (8 * sizeof(u32)) -+#define OFFSET_CODEC_PARAMS_REGS (64 * sizeof(u32)) -+#define OFFSET_COMMON_ADDR_REGS (128 * sizeof(u32)) -+#define OFFSET_CODEC_ADDR_REGS (160 * sizeof(u32)) -+#define OFFSET_POC_HIGHBIT_REGS (200 * sizeof(u32)) -+ -+#define VDPU381_MODE_HEVC 0 -+#define VDPU381_MODE_H264 1 -+#define VDPU381_MODE_VP9 2 -+#define VDPU381_MODE_AVS2 3 -+ -+#define MAX_SLICE_NUMBER 0x3fff -+ -+#define RKVDEC_1080P_PIXELS (1920 * 1080) -+#define RKVDEC_4K_PIXELS (4096 * 2304) -+#define RKVDEC_8K_PIXELS (7680 * 4320) -+#define RKVDEC_TIMEOUT_1080p (0xefffff) -+#define RKVDEC_TIMEOUT_4K (0x2cfffff) -+#define RKVDEC_TIMEOUT_8K (0x4ffffff) -+#define RKVDEC_TIMEOUT_MAX (0xffffffff) -+ -+#define VDPU381_REG_DEC_E 0x028 -+#define VDPU381_DEC_E_BIT 1 -+ -+#define VDPU381_REG_IMPORTANT_EN 0x02c -+#define VDPU381_DEC_IRQ_DISABLE BIT(4) -+ -+#define VDPU381_REG_STA_INT 0x380 -+#define VDPU381_STA_INT_DEC_RDY_STA BIT(2) -+#define VDPU381_STA_INT_ERROR BIT(4) -+#define VDPU381_STA_INT_TIMEOUT BIT(5) -+#define VDPU381_STA_INT_SOFTRESET_RDY BIT(9) -+ -+/* base: OFFSET_COMMON_REGS */ -+struct rkvdec_vdpu381_regs_common { -+ struct rkvdec_vdpu381_in_out { -+ u32 in_endian : 1; -+ u32 in_swap32_e : 1; -+ u32 in_swap64_e : 1; -+ u32 str_endian : 1; -+ u32 str_swap32_e : 1; -+ u32 str_swap64_e : 1; -+ u32 out_endian : 1; -+ u32 out_swap32_e : 1; -+ u32 out_cbcr_swap : 1; -+ u32 out_swap64_e : 1; -+ u32 reserved : 22; -+ } reg008; -+ -+ struct rkvdec_vdpu381_dec_mode { -+ u32 dec_mode : 10; -+ u32 reserved : 22; -+ } reg009; -+ -+ struct rkvdec_vdpu381_dec_e { -+ u32 dec_e : 1; -+ u32 reserved : 31; -+ } reg010; -+ -+ struct rkvdec_vdpu381_important_en { -+ u32 reserved : 1; -+ u32 dec_clkgate_e : 1; -+ u32 dec_e_strmd_clkgate_dis : 1; -+ u32 reserved0 : 1; -+ -+ u32 dec_irq_dis : 1; -+ u32 dec_timeout_e : 1; -+ u32 buf_empty_en : 1; -+ u32 reserved1 : 3; -+ -+ u32 dec_e_rewrite_valid : 1; -+ u32 reserved2 : 9; -+ u32 softrst_en_p : 1; -+ u32 force_softreset_valid : 1; -+ u32 reserved3 : 2; -+ u32 pix_range_detection_e : 1; -+ u32 reserved4 : 7; -+ } reg011; -+ -+ struct rkvdec_vdpu381_sencodary_en { -+ u32 wr_ddr_align_en : 1; -+ u32 colmv_compress_en : 1; -+ u32 fbc_e : 1; -+ u32 reserved0 : 1; -+ -+ u32 buspr_slot_disable : 1; -+ u32 error_info_en : 1; -+ u32 info_collect_en : 1; -+ u32 wait_reset_en : 1; -+ -+ u32 scanlist_addr_valid_en : 1; -+ u32 scale_down_en : 1; -+ u32 error_cfg_wr_disable : 1; -+ u32 reserved1 : 21; -+ } reg012; -+ -+ struct rkvdec_vdpu381_en_mode_set { -+ u32 timeout_mode : 1; -+ u32 req_timeout_rst_sel : 1; -+ u32 reserved0 : 1; -+ u32 dec_commonirq_mode : 1; -+ u32 reserved1 : 2; -+ u32 stmerror_waitdecfifo_empty : 1; -+ u32 reserved2 : 2; -+ u32 h26x_streamd_error_mode : 1; -+ u32 reserved3 : 2; -+ u32 allow_not_wr_unref_bframe : 1; -+ u32 fbc_output_wr_disable : 1; -+ u32 reserved4 : 1; -+ u32 colmv_error_mode : 1; -+ -+ u32 reserved5 : 2; -+ u32 h26x_error_mode : 1; -+ u32 reserved6 : 2; -+ u32 ycacherd_prior : 1; -+ u32 reserved7 : 2; -+ u32 cur_pic_is_idr : 1; -+ u32 reserved8 : 1; -+ u32 right_auto_rst_disable : 1; -+ u32 frame_end_err_rst_flag : 1; -+ u32 rd_prior_mode : 1; -+ u32 rd_ctrl_prior_mode : 1; -+ u32 reserved9 : 1; -+ u32 filter_outbuf_mode : 1; -+ } reg013; -+ -+ struct rkvdec_vdpu381_fbc_param_set { -+ u32 fbc_force_uncompress : 1; -+ -+ u32 reserved0 : 2; -+ u32 allow_16x8_cp_flag : 1; -+ u32 reserved1 : 2; -+ -+ u32 fbc_h264_exten_4or8_flag : 1; -+ u32 reserved2 : 25; -+ } reg014; -+ -+ struct rkvdec_vdpu381_stream_param_set { -+ u32 rlc_mode_direct_write : 1; -+ u32 rlc_mode : 1; -+ u32 reserved0 : 3; -+ -+ u32 strm_start_bit : 7; -+ u32 reserved1 : 20; -+ } reg015; -+ -+ u32 stream_len; -+ -+ struct rkvdec_vdpu381_slice_number { -+ u32 slice_num : 25; -+ u32 reserved : 7; -+ } reg017; -+ -+ struct rkvdec_vdpu381_y_hor_stride { -+ u32 y_hor_virstride : 16; -+ u32 reserved : 16; -+ } reg018; -+ -+ struct rkvdec_vdpu381_uv_hor_stride { -+ u32 uv_hor_virstride : 16; -+ u32 reserved : 16; -+ } reg019; -+ -+ struct rkvdec_vdpu381_y_stride { -+ u32 y_virstride : 28; -+ u32 reserved : 4; -+ } reg020; -+ -+ struct rkvdec_vdpu381_error_ctrl_set { -+ u32 inter_error_prc_mode : 1; -+ u32 error_intra_mode : 1; -+ u32 error_deb_en : 1; -+ u32 picidx_replace : 5; -+ u32 error_spread_e : 1; -+ u32 reserved0 : 3; -+ u32 error_inter_pred_cross_slice : 1; -+ u32 reserved1 : 11; -+ u32 roi_error_ctu_cal_en : 1; -+ u32 reserved2 : 7; -+ } reg021; -+ -+ struct rkvdec_vdpu381_err_roi_ctu_offset_start { -+ u32 roi_x_ctu_offset_st : 12; -+ u32 reserved0 : 4; -+ u32 roi_y_ctu_offset_st : 12; -+ u32 reserved1 : 4; -+ } reg022; -+ -+ struct rkvdec_vdpu381_err_roi_ctu_offset_end { -+ u32 roi_x_ctu_offset_end : 12; -+ u32 reserved0 : 4; -+ u32 roi_y_ctu_offset_end : 12; -+ u32 reserved1 : 4; -+ } reg023; -+ -+ struct rkvdec_vdpu381_cabac_error_en_lowbits { -+ u32 cabac_err_en_lowbits : 32; -+ } reg024; -+ -+ struct rkvdec_vdpu381_cabac_error_en_highbits { -+ u32 cabac_err_en_highbits : 30; -+ u32 reserved : 2; -+ } reg025; -+ -+ struct rkvdec_vdpu381_block_gating_en { -+ u32 swreg_block_gating_e : 20; -+ u32 reserved : 11; -+ u32 reg_cfg_gating_en : 1; -+ } reg026; -+ -+ struct SW027_CORE_SAFE_PIXELS { -+ u32 core_safe_x_pixels : 16; -+ u32 core_safe_y_pixels : 16; -+ } reg027; -+ -+ struct rkvdec_vdpu381_multiply_core_ctrl { -+ u32 swreg_vp9_wr_prob_idx : 3; -+ u32 reserved0 : 1; -+ u32 swreg_vp9_rd_prob_idx : 3; -+ u32 reserved1 : 1; -+ -+ u32 swreg_ref_req_advance_flag : 1; -+ u32 sw_colmv_req_advance_flag : 1; -+ u32 sw_poc_only_highbit_flag : 1; -+ u32 sw_poc_arb_flag : 1; -+ -+ u32 reserved2 : 4; -+ u32 sw_film_idx : 10; -+ u32 reserved3 : 2; -+ u32 sw_pu_req_mismatch_dis : 1; -+ u32 sw_colmv_req_mismatch_dis : 1; -+ u32 reserved4 : 2; -+ } reg028; -+ -+ struct SW029_SCALE_DOWN_CTRL { -+ u32 scale_down_hor_ratio : 2; -+ u32 reserved0 : 6; -+ u32 scale_down_vrz_ratio : 2; -+ u32 reserved1 : 22; -+ } reg029; -+ -+ struct SW032_Y_SCALE_DOWN_TILE8x8_HOR_STRIDE { -+ u32 y_scale_down_hor_stride : 20; -+ u32 reserved0 : 12; -+ } reg030; -+ -+ struct SW031_UV_SCALE_DOWN_TILE8x8_HOR_STRIDE { -+ u32 uv_scale_down_hor_stride : 20; -+ u32 reserved0 : 12; -+ } reg031; -+ -+ u32 timeout_threshold; -+} __packed; -+ -+/* base: OFFSET_COMMON_ADDR_REGS */ -+struct rkvdec_vdpu381_regs_common_addr { -+ u32 rlc_base; -+ u32 rlcwrite_base; -+ u32 decout_base; -+ u32 colmv_cur_base; -+ u32 error_ref_base; -+ u32 rcb_base[10]; -+} __packed; -+ -+struct rkvdec_vdpu381_h26x_set { -+ u32 h26x_frame_orslice : 1; -+ u32 h26x_rps_mode : 1; -+ u32 h26x_stream_mode : 1; -+ u32 h26x_stream_lastpacket : 1; -+ u32 h264_firstslice_flag : 1; -+ u32 reserved : 27; -+} __packed; -+ -+/* base: OFFSET_CODEC_PARAMS_REGS */ -+struct rkvdec_vdpu381_regs_h264_params { -+ struct rkvdec_vdpu381_h26x_set reg064; -+ -+ u32 cur_top_poc; -+ u32 cur_bot_poc; -+ u32 ref_pocs[32]; -+ -+ struct rkvdec_vdpu381_h264_info { -+ struct rkvdec_vdpu381_h264_ref_info { -+ u32 ref_field : 1; -+ u32 ref_topfield_used : 1; -+ u32 ref_botfield_used : 1; -+ u32 ref_colmv_use_flag : 1; -+ u32 ref_reserved : 4; -+ } __packed ref_info[4]; -+ } __packed ref_info_regs[4]; -+ -+ u32 reserved_103_111[9]; -+ -+ struct rkvdec_vdpu381_error_ref_info { -+ u32 avs2_ref_error_field : 1; -+ u32 avs2_ref_error_topfield : 1; -+ u32 ref_error_topfield_used : 1; -+ u32 ref_error_botfield_used : 1; -+ u32 reserved : 28; -+ } reg112; -+} __packed; -+ -+struct rkvdec_vdpu381_regs_hevc_params { -+ struct rkvdec_vdpu381_h26x_set reg064; -+ -+ u32 cur_top_poc; -+ u32 cur_bot_poc; -+ -+ u32 reg067_082_ref_poc[16]; -+ -+ u32 reserved_083_098[16]; -+ -+ struct rkvdec_vdpu381_hevc_ref_valid { -+ u32 hevc_ref_valid_0 : 1; -+ u32 hevc_ref_valid_1 : 1; -+ u32 hevc_ref_valid_2 : 1; -+ u32 hevc_ref_valid_3 : 1; -+ u32 reserve0 : 4; -+ u32 hevc_ref_valid_4 : 1; -+ u32 hevc_ref_valid_5 : 1; -+ u32 hevc_ref_valid_6 : 1; -+ u32 hevc_ref_valid_7 : 1; -+ u32 reserve1 : 4; -+ u32 hevc_ref_valid_8 : 1; -+ u32 hevc_ref_valid_9 : 1; -+ u32 hevc_ref_valid_10 : 1; -+ u32 hevc_ref_valid_11 : 1; -+ u32 reserve2 : 4; -+ u32 hevc_ref_valid_12 : 1; -+ u32 hevc_ref_valid_13 : 1; -+ u32 hevc_ref_valid_14 : 1; -+ u32 reserve3 : 5; -+ } reg099; -+ -+ u32 reserved_100_102[3]; -+ -+ struct rkvdec_vdpu381_hevc_mvc0 { -+ u32 ref_pic_layer_same_with_cur : 16; -+ u32 reserve : 16; -+ } reg103; -+ -+ struct rkvdec_vdpu381_hevc_mvc1 { -+ u32 poc_lsb_not_present_flag : 1; -+ u32 num_direct_ref_layers : 6; -+ u32 reserve0 : 1; -+ -+ u32 num_reflayer_pics : 6; -+ u32 default_ref_layers_active_flag : 1; -+ u32 max_one_active_ref_layer_flag : 1; -+ -+ u32 poc_reset_info_present_flag : 1; -+ u32 vps_poc_lsb_aligned_flag : 1; -+ u32 mvc_poc15_valid_flag : 1; -+ u32 reserve1 : 13; -+ } reg104; -+ -+ u32 reserved_105_111[7]; -+ -+ struct rkvdec_vdpu381_hevc_ref_info { -+ u32 avs2_ref_error_field : 1; -+ u32 avs2_ref_error_topfield : 1; -+ u32 ref_error_topfield_used : 1; -+ u32 ref_error_botfield_used : 1; -+ u32 reserve : 28; -+ } reg112; -+ -+} __packed; -+ -+/* base: OFFSET_CODEC_ADDR_REGS */ -+struct rkvdec_vdpu381_regs_h26x_addr { -+ u32 reserved_160; -+ u32 pps_base; -+ u32 reserved_162; -+ u32 rps_base; -+ u32 ref_base[16]; -+ u32 scanlist_addr; -+ u32 colmv_base[16]; -+ u32 cabactbl_base; -+} __packed; -+ -+struct rkvdec_vdpu381_regs_h26x_highpoc { -+ struct rkvdec_vdpu381_ref_poc_highbit { -+ u32 ref0_poc_highbit : 4; -+ u32 ref1_poc_highbit : 4; -+ u32 ref2_poc_highbit : 4; -+ u32 ref3_poc_highbit : 4; -+ u32 ref4_poc_highbit : 4; -+ u32 ref5_poc_highbit : 4; -+ u32 ref6_poc_highbit : 4; -+ u32 ref7_poc_highbit : 4; -+ } reg200[4]; -+ struct rkvdec_vdpu381_cur_poc_highbit { -+ u32 cur_poc_highbit : 4; -+ u32 reserved : 28; -+ } reg204; -+} __packed; -+ -+struct rkvdec_vdpu381_regs_h264 { -+ struct rkvdec_vdpu381_regs_common common; -+ struct rkvdec_vdpu381_regs_h264_params h264_param; -+ struct rkvdec_vdpu381_regs_common_addr common_addr; -+ struct rkvdec_vdpu381_regs_h26x_addr h264_addr; -+ struct rkvdec_vdpu381_regs_h26x_highpoc h264_highpoc; -+} __packed; -+ -+struct rkvdec_vdpu381_regs_hevc { -+ struct rkvdec_vdpu381_regs_common common; -+ struct rkvdec_vdpu381_regs_hevc_params hevc_param; -+ struct rkvdec_vdpu381_regs_common_addr common_addr; -+ struct rkvdec_vdpu381_regs_h26x_addr hevc_addr; -+ struct rkvdec_vdpu381_regs_h26x_highpoc hevc_highpoc; -+} __packed; -+ -+#endif /* __RKVDEC_REGS_H__ */ -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -29,6 +29,7 @@ - - #include "rkvdec.h" - #include "rkvdec-regs.h" -+#include "rkvdec-vdpu381-regs.h" - #include "rkvdec-rcb.h" - - static bool rkvdec_image_fmt_match(enum rkvdec_image_fmt fmt1, -@@ -85,11 +86,50 @@ static bool rkvdec_is_valid_fmt(struct rkvdec_ctx *ctx, u32 fourcc, - return false; - } - -+#define VDPU38X_STRIDE_ALIGN 16 -+ -+/** -+ * The default v4l2_fill_pixfmt_mp() function doesn't allow for specific alignment values. -+ * As the VDPU381 and VDPU383 need lines to be aligned on 16, use our own implementation here. -+ */ -+static int vdpu38x_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pix_mp, u32 pixelformat, -+ u32 width, u32 height) -+{ -+ const struct v4l2_format_info *info = v4l2_format_info(pix_mp->pixelformat); -+ struct v4l2_plane_pix_format *plane = &pix_mp->plane_fmt[0]; -+ -+ if (!info) -+ return -EINVAL; -+ -+ pix_mp->num_planes = 1; -+ -+ memset(plane, 0, sizeof(*plane)); -+ -+ plane->bytesperline = pix_mp->width * info->bpp[0] / info->bpp_div[0]; -+ plane->bytesperline = ALIGN(plane->bytesperline, VDPU38X_STRIDE_ALIGN); -+ -+ for (int i = 0; i < info->comp_planes; i++) { -+ unsigned int vdiv = i ? info->vdiv : 1; -+ unsigned int hdiv = i ? info->hdiv : 1; -+ unsigned int stride = DIV_ROUND_UP(pix_mp->width, hdiv) -+ * info->bpp[i] / info->bpp_div[i]; -+ unsigned int height = DIV_ROUND_UP(pix_mp->height, vdiv); -+ -+ plane->sizeimage += ALIGN(stride, VDPU38X_STRIDE_ALIGN) * height; -+ } -+ -+ return 0; -+} -+ - static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - struct v4l2_pix_format_mplane *pix_mp) - { -- v4l2_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, -- pix_mp->width, pix_mp->height); -+ const struct rkvdec_config *cfg = ctx->dev->config; -+ -+ cfg->fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, pix_mp->width, pix_mp->height); -+ -+ ctx->colmv_offset = pix_mp->plane_fmt[0].sizeimage; -+ - pix_mp->plane_fmt[0].sizeimage += 128 * - DIV_ROUND_UP(pix_mp->width, 16) * - DIV_ROUND_UP(pix_mp->height, 16); -@@ -367,6 +407,26 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { - } - }; - -+static const struct rkvdec_coded_fmt_desc vdpu381_coded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_H264_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 65520, -+ .step_width = 64, -+ .min_height = 16, -+ .max_height = 65520, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_h264_ctrls, -+ .ops = &rkvdec_vdpu381_h264_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_decoded_fmts, -+ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ .capability = RKVDEC_CAPABILITY_H264, -+ }, -+}; -+ - static bool rkvdec_is_capable(struct rkvdec_ctx *ctx, unsigned int capability) - { - return (ctx->dev->capabilities & capability) == capability; -@@ -1230,6 +1290,35 @@ static irqreturn_t rk3399_irq_handler(struct rkvdec_ctx *ctx) - return IRQ_HANDLED; - } - -+static irqreturn_t vdpu381_irq_handler(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ enum vb2_buffer_state state; -+ bool need_reset = 0; -+ u32 status; -+ -+ status = readl(rkvdec->regs + VDPU381_REG_STA_INT); -+ writel(0, rkvdec->regs + VDPU381_REG_STA_INT); -+ -+ if (status & VDPU381_STA_INT_DEC_RDY_STA) { -+ state = VB2_BUF_STATE_DONE; -+ } else { -+ state = VB2_BUF_STATE_ERROR; -+ if (status & (VDPU381_STA_INT_SOFTRESET_RDY | -+ VDPU381_STA_INT_TIMEOUT | -+ VDPU381_STA_INT_ERROR)) -+ rkvdec_iommu_restore(rkvdec); -+ } -+ -+ if (need_reset) -+ rkvdec_iommu_restore(rkvdec); -+ -+ if (cancel_delayed_work(&rkvdec->watchdog_work)) -+ rkvdec_job_finish(ctx, state); -+ -+ return IRQ_HANDLED; -+} -+ - static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - { - struct rkvdec_dev *rkvdec = priv; -@@ -1254,10 +1343,76 @@ static void rkvdec_watchdog_func(struct work_struct *work) - } - } - -+/* -+ * Some SoCs, like RK3588 have multiple identical VDPU cores, but the -+ * kernel is currently missing support for multi-core handling. Exposing -+ * separate devices for each core to userspace is bad, since that does -+ * not allow scheduling tasks properly (and creates ABI). With this workaround -+ * the driver will only probe for the first core and early exit for the other -+ * cores. Once the driver gains multi-core support, the same technique -+ * for detecting the first core can be used to cluster all cores together. -+ */ -+static int rkvdec_disable_multicore(struct rkvdec_dev *rkvdec) -+{ -+ struct device_node *node = NULL; -+ const char *compatible; -+ bool is_first_core; -+ int ret; -+ -+ /* Intentionally ignores the fallback strings */ -+ ret = of_property_read_string(rkvdec->dev->of_node, "compatible", &compatible); -+ if (ret) -+ return ret; -+ -+ /* The first compatible and available node found is considered the main core */ -+ do { -+ node = of_find_compatible_node(node, NULL, compatible); -+ if (of_device_is_available(node)) -+ break; -+ } while (node); -+ -+ if (!node) -+ return -EINVAL; -+ -+ is_first_core = (rkvdec->dev->of_node == node); -+ -+ of_node_put(node); -+ -+ if (!is_first_core) { -+ dev_info(rkvdec->dev, "missing multi-core support, ignoring this instance\n"); -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+ - static const struct rkvdec_config config_rkvdec = { - .coded_fmts = (struct rkvdec_coded_fmt_desc *)rkvdec_coded_fmts, - .coded_fmts_num = ARRAY_SIZE(rkvdec_coded_fmts), - .irq_handler = rk3399_irq_handler, -+ .fill_pixfmt_mp = v4l2_fill_pixfmt_mp, -+}; -+ -+static struct rcb_size_info vdpu381_rcb_sizes[] = { -+ {6, PIC_WIDTH}, // intrar -+ {1, PIC_WIDTH}, // transdr (Is actually 0.4*pic_width) -+ {1, PIC_HEIGHT}, // transdc (Is actually 0.1*pic_height) -+ {3, PIC_WIDTH}, // streamdr -+ {6, PIC_WIDTH}, // interr -+ {3, PIC_HEIGHT}, // interc -+ {22, PIC_WIDTH}, // dblkr -+ {6, PIC_WIDTH}, // saor -+ {11, PIC_WIDTH}, // fbcr -+ {67, PIC_HEIGHT}, // filtc col -+}; -+ -+static const struct rkvdec_config config_vdpu381 = { -+ .coded_fmts = (struct rkvdec_coded_fmt_desc *)vdpu381_coded_fmts, -+ .coded_fmts_num = ARRAY_SIZE(vdpu381_coded_fmts), -+ .rcb_size_info = vdpu381_rcb_sizes, -+ .rcb_num = ARRAY_SIZE(vdpu381_rcb_sizes), -+ .irq_handler = vdpu381_irq_handler, -+ .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, - }; - - static const struct rkvdec_variant rk3288_rkvdec_variant = { -@@ -1280,6 +1435,11 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { - RKVDEC_CAPABILITY_VP9, - }; - -+static const struct rkvdec_variant rk3588_vdpu381_variant = { -+ .config = &config_vdpu381, -+ .capabilities = RKVDEC_CAPABILITY_H264, -+}; -+ - static const struct of_device_id of_rkvdec_match[] = { - { - .compatible = "rockchip,rk3288-vdec", -@@ -1293,6 +1453,10 @@ static const struct of_device_id of_rkvdec_match[] = { - .compatible = "rockchip,rk3399-vdec", - .data = &rk3399_rkvdec_variant, - }, -+ { -+ .compatible = "rockchip,rk3588-vdec", -+ .data = &rk3588_vdpu381_variant, -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1319,11 +1483,16 @@ static int rkvdec_probe(struct platform_device *pdev) - mutex_init(&rkvdec->vdev_lock); - INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); - -+ ret = rkvdec_disable_multicore(rkvdec); -+ if (ret) -+ return ret; -+ - ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &rkvdec->clocks); - if (ret < 0) - return ret; - - rkvdec->clk_count = ret; -+ rkvdec->axi_clk = devm_clk_get(&pdev->dev, "axi"); - - rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(rkvdec->regs)) -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -121,6 +121,8 @@ struct rkvdec_config { - struct rcb_size_info *rcb_size_info; - size_t rcb_num; - irqreturn_t (*irq_handler)(struct rkvdec_ctx *ctx); -+ int (*fill_pixfmt_mp)(struct v4l2_pix_format_mplane *pix_mp, u32 pixelformat, -+ u32 width, u32 height); - }; - - struct rkvdec_dev { -@@ -131,6 +133,7 @@ struct rkvdec_dev { - struct device *dev; - struct clk_bulk_data *clocks; - unsigned int clk_count; -+ struct clk *axi_clk; - void __iomem *regs; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; -@@ -151,6 +154,7 @@ struct rkvdec_ctx { - struct rkvdec_dev *dev; - enum rkvdec_image_fmt image_fmt; - struct rkvdec_rcb_config *rcb_config; -+ u32 colmv_offset; - void *priv; - }; - -@@ -179,4 +183,6 @@ extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; - -+extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_h264_fmt_ops; -+ - #endif /* RKVDEC_H_ */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Tue, 10 Jun 2025 17:45:17 -0400 -Subject: media: rkvdec: Add H264 support for the VDPU383 variant - -This variant is used on the RK3576 SoC. - -The moving vectors size requirements are slightly different so support -for a colmv_size function per variant is added. - -Also, the link registers are used to start the decoder and read IRQ status. -Per variant support for named register sections is added. - -The fluster score is 128/135 for JVT-AVC_V1. -The other test suites are not supported yet. - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/Kconfig | 1 + - drivers/media/platform/rockchip/rkvdec/Makefile | 3 + - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c | 413 ++++++- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h | 84 +- - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c | 5 +- - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c | 588 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c | 582 +++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-regs.h | 284 +++++ - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 212 +++- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 9 + - 10 files changed, 2109 insertions(+), 72 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/Kconfig b/drivers/media/platform/rockchip/rkvdec/Kconfig -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/Kconfig -+++ b/drivers/media/platform/rockchip/rkvdec/Kconfig -@@ -8,6 +8,7 @@ config VIDEO_ROCKCHIP_VDEC - select VIDEOBUF2_VMALLOC - select V4L2_MEM2MEM_DEV - select V4L2_H264 -+ select V4L2_HEVC - select V4L2_VP9 - help - Support for the Rockchip Video Decoder IP present on Rockchip SoCs, -diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/Makefile -+++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -6,6 +6,9 @@ rockchip-vdec-y += \ - rkvdec-h264.o \ - rkvdec-h264-common.o \ - rkvdec-hevc.o \ -+ rkvdec-hevc-common.o \ - rkvdec-rcb.o \ - rkvdec-vdpu381-h264.o \ -+ rkvdec-vdpu381-hevc.o \ -+ rkvdec-vdpu383-h264.o \ - rkvdec-vp9.o -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -@@ -18,6 +18,143 @@ - #include "rkvdec.h" - #include "rkvdec-hevc-common.h" - -+#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -+ -+/* Store the Short term ref pic set calculated values */ -+struct calculated_rps_st_set { -+ u8 num_delta_pocs; -+ u8 num_negative_pics; -+ u8 num_positive_pics; -+ u8 used_by_curr_pic_s0[16]; -+ u8 used_by_curr_pic_s1[16]; -+ s32 delta_poc_s0[16]; -+ s32 delta_poc_s1[16]; -+}; -+ -+enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_ctrl *ctrl) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -+ -+ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS) -+ return RKVDEC_IMG_FMT_ANY; -+ -+ if (sps->bit_depth_luma_minus8 == 0) -+ return RKVDEC_IMG_FMT_420_8BIT; -+ else if (sps->bit_depth_luma_minus8 == 2) -+ return RKVDEC_IMG_FMT_420_10BIT; -+ -+ return RKVDEC_IMG_FMT_ANY; -+} -+ -+void compute_tiles_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, -+ u16 width, u16 height, s32 pic_in_cts_width, -+ s32 pic_in_cts_height, u16 *column_width, u16 *row_height) -+{ -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ int i; -+ -+ for (i = 0; i < pps->num_tile_columns_minus1 + 1; i++) -+ column_width[i] = ((i + 1) * pic_in_cts_width) / -+ (pps->num_tile_columns_minus1 + 1) - -+ (i * pic_in_cts_width) / -+ (pps->num_tile_columns_minus1 + 1); -+ -+ for (i = 0; i < pps->num_tile_rows_minus1 + 1; i++) -+ row_height[i] = ((i + 1) * pic_in_cts_height) / -+ (pps->num_tile_rows_minus1 + 1) - -+ (i * pic_in_cts_height) / -+ (pps->num_tile_rows_minus1 + 1); -+} -+ -+void compute_tiles_non_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, -+ u16 width, u16 height, s32 pic_in_cts_width, -+ s32 pic_in_cts_height, u16 *column_width, u16 *row_height) -+{ -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ s32 sum = 0; -+ int i; -+ -+ for (i = 0; i < pps->num_tile_columns_minus1; i++) { -+ column_width[i] = pps->column_width_minus1[i] + 1; -+ sum += column_width[i]; -+ } -+ column_width[i] = pic_in_cts_width - sum; -+ -+ sum = 0; -+ for (i = 0; i < pps->num_tile_rows_minus1; i++) { -+ row_height[i] = pps->row_height_minus1[i] + 1; -+ sum += row_height[i]; -+ } -+ row_height[i] = pic_in_cts_height - sum; -+} -+ -+static void set_ref_poc(struct rkvdec_rps_short_term_ref_set *set, int poc, int value, int flag) -+{ -+ switch (poc) { -+ case 0: -+ set->delta_poc0 = value; -+ set->used_flag0 = flag; -+ break; -+ case 1: -+ set->delta_poc1 = value; -+ set->used_flag1 = flag; -+ break; -+ case 2: -+ set->delta_poc2 = value; -+ set->used_flag2 = flag; -+ break; -+ case 3: -+ set->delta_poc3 = value; -+ set->used_flag3 = flag; -+ break; -+ case 4: -+ set->delta_poc4 = value; -+ set->used_flag4 = flag; -+ break; -+ case 5: -+ set->delta_poc5 = value; -+ set->used_flag5 = flag; -+ break; -+ case 6: -+ set->delta_poc6 = value; -+ set->used_flag6 = flag; -+ break; -+ case 7: -+ set->delta_poc7 = value; -+ set->used_flag7 = flag; -+ break; -+ case 8: -+ set->delta_poc8 = value; -+ set->used_flag8 = flag; -+ break; -+ case 9: -+ set->delta_poc9 = value; -+ set->used_flag9 = flag; -+ break; -+ case 10: -+ set->delta_poc10 = value; -+ set->used_flag10 = flag; -+ break; -+ case 11: -+ set->delta_poc11 = value; -+ set->used_flag11 = flag; -+ break; -+ case 12: -+ set->delta_poc12 = value; -+ set->used_flag12 = flag; -+ break; -+ case 13: -+ set->delta_poc13 = value; -+ set->used_flag13 = flag; -+ break; -+ case 14: -+ set->delta_poc14 = value; -+ set->used_flag14 = flag; -+ break; -+ } -+} -+ - /* - * Flip one or more matrices along their main diagonal and flatten them - * before writing it to the memory. -@@ -50,13 +187,15 @@ static void transpose_and_flatten_matrices(u8 *output, const u8 *input, - } - } - --static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) -+static void assemble_scalingfactor0(struct rkvdec_dev *rkvdec, u8 *output, -+ const struct v4l2_ctrl_hevc_scaling_matrix *input) - { - int offset = 0; - - transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); - offset = 6 * 16 * sizeof(u8); -- transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); -+ transpose_and_flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_8x8, 6, 8); - offset += 6 * 64 * sizeof(u8); - transpose_and_flatten_matrices(output + offset, - (const u8 *)input->scaling_list_16x16, 6, 8); -@@ -92,18 +231,19 @@ static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_m - memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); - } - --static void translate_scaling_list(struct scaling_factor *output, -+static void translate_scaling_list(struct rkvdec_dev *rkvdec, struct scaling_factor *output, - const struct v4l2_ctrl_hevc_scaling_matrix *input) - { -- assemble_scalingfactor0(output->scalingfactor0, input); -+ assemble_scalingfactor0(rkvdec, output->scalingfactor0, input); - memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); - assemble_scalingdc(output->scalingdc, input); - memset(output->reserved, 0, 4 * sizeof(u8)); - } - --void assemble_hw_scaling_list(struct rkvdec_hevc_run *run, -- struct scaling_factor *scaling_factor, -- struct v4l2_ctrl_hevc_scaling_matrix *cache) -+void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_dev *rkvdec, -+ struct rkvdec_hevc_run *run, -+ struct scaling_factor *scaling_list, -+ struct v4l2_ctrl_hevc_scaling_matrix *cache) - { - const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; - -@@ -111,15 +251,220 @@ void assemble_hw_scaling_list(struct rkvdec_hevc_run *run, - sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) - return; - -- translate_scaling_list(scaling_factor, scaling); -+ translate_scaling_list(rkvdec, scaling_list, scaling); - - memcpy(cache, scaling, - sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); - } - --struct vb2_buffer * --get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, -- unsigned int dpb_idx) -+static void rkvdec_hevc_assemble_hw_lt_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ -+ if (!run->ext_sps_lt_rps) -+ return; -+ -+ for (int i = 0; i < sps->num_long_term_ref_pics_sps; i++) { -+ rps->refs[i].lt_ref_pic_poc_lsb = -+ run->ext_sps_lt_rps[i].lt_ref_pic_poc_lsb_sps; -+ rps->refs[i].used_by_curr_pic_lt_flag = -+ !!(run->ext_sps_lt_rps[i].flags & V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT); -+ } -+} -+ -+static void rkvdec_hevc_assemble_hw_st_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, -+ struct calculated_rps_st_set *calculated_rps_st_sets) -+{ -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ -+ for (int i = 0; i < sps->num_short_term_ref_pic_sets; i++) { -+ int poc = 0; -+ int j = 0; -+ const struct calculated_rps_st_set *set = &calculated_rps_st_sets[i]; -+ -+ rps->short_term_ref_sets[i].num_negative = set->num_negative_pics; -+ rps->short_term_ref_sets[i].num_positive = set->num_positive_pics; -+ -+ for (; j < set->num_negative_pics; j++) { -+ set_ref_poc(&rps->short_term_ref_sets[i], j, -+ set->delta_poc_s0[j], set->used_by_curr_pic_s0[j]); -+ } -+ poc = j; -+ -+ for (j = 0; j < set->num_positive_pics; j++) { -+ set_ref_poc(&rps->short_term_ref_sets[i], poc + j, -+ set->delta_poc_s1[j], set->used_by_curr_pic_s1[j]); -+ } -+ } -+} -+ -+/* -+ * Compute the short term ref pic set parameters based on its reference short term ref pic -+ */ -+static void st_ref_pic_set_prediction(struct rkvdec_hevc_run *run, int idx, -+ struct calculated_rps_st_set *calculated_rps_st_sets) -+{ -+ const struct v4l2_ctrl_hevc_ext_sps_st_rps *rps_data = &run->ext_sps_st_rps[idx]; -+ struct calculated_rps_st_set *st_rps = &calculated_rps_st_sets[idx]; -+ struct calculated_rps_st_set *ref_rps; -+ u8 st_rps_idx = idx; -+ u8 ref_rps_idx = 0; -+ s16 delta_rps = 0; -+ u8 use_delta_flag[16] = { 0 }; -+ u8 used_by_curr_pic_flag[16] = { 0 }; -+ int i, j; -+ int dPoc; -+ -+ ref_rps_idx = st_rps_idx - (rps_data->delta_idx_minus1 + 1); /* 7-59 */ -+ delta_rps = (1 - 2 * rps_data->delta_rps_sign) * -+ (rps_data->abs_delta_rps_minus1 + 1); /* 7-60 */ -+ -+ ref_rps = &calculated_rps_st_sets[ref_rps_idx]; -+ -+ for (j = 0; j <= ref_rps->num_delta_pocs; j++) { -+ used_by_curr_pic_flag[j] = !!(rps_data->used_by_curr_pic & (1 << j)); -+ use_delta_flag[j] = !!(rps_data->use_delta_flag & (1 << j)); -+ } -+ -+ /* 7-61: calculate num_negative_pics, delta_poc_s0 and used_by_curr_pic_s0 */ -+ i = 0; -+ for (j = (ref_rps->num_positive_pics - 1); j >= 0; j--) { -+ dPoc = ref_rps->delta_poc_s1[j] + delta_rps; -+ if (dPoc < 0 && use_delta_flag[ref_rps->num_negative_pics + j]) { -+ st_rps->delta_poc_s0[i] = dPoc; -+ st_rps->used_by_curr_pic_s0[i++] = -+ used_by_curr_pic_flag[ref_rps->num_negative_pics + j]; -+ } -+ } -+ if (delta_rps < 0 && use_delta_flag[ref_rps->num_delta_pocs]) { -+ st_rps->delta_poc_s0[i] = delta_rps; -+ st_rps->used_by_curr_pic_s0[i++] = used_by_curr_pic_flag[ref_rps->num_delta_pocs]; -+ } -+ for (j = 0; j < ref_rps->num_negative_pics; j++) { -+ dPoc = ref_rps->delta_poc_s0[j] + delta_rps; -+ if (dPoc < 0 && use_delta_flag[j]) { -+ st_rps->delta_poc_s0[i] = dPoc; -+ st_rps->used_by_curr_pic_s0[i++] = used_by_curr_pic_flag[j]; -+ } -+ } -+ st_rps->num_negative_pics = i; -+ -+ /* 7-62: calculate num_positive_pics, delta_poc_s1 and used_by_curr_pic_s1 */ -+ i = 0; -+ for (j = (ref_rps->num_negative_pics - 1); j >= 0; j--) { -+ dPoc = ref_rps->delta_poc_s0[j] + delta_rps; -+ if (dPoc > 0 && use_delta_flag[j]) { -+ st_rps->delta_poc_s1[i] = dPoc; -+ st_rps->used_by_curr_pic_s1[i++] = used_by_curr_pic_flag[j]; -+ } -+ } -+ if (delta_rps > 0 && use_delta_flag[ref_rps->num_delta_pocs]) { -+ st_rps->delta_poc_s1[i] = delta_rps; -+ st_rps->used_by_curr_pic_s1[i++] = used_by_curr_pic_flag[ref_rps->num_delta_pocs]; -+ } -+ for (j = 0; j < ref_rps->num_positive_pics; j++) { -+ dPoc = ref_rps->delta_poc_s1[j] + delta_rps; -+ if (dPoc > 0 && use_delta_flag[ref_rps->num_negative_pics + j]) { -+ st_rps->delta_poc_s1[i] = dPoc; -+ st_rps->used_by_curr_pic_s1[i++] = -+ used_by_curr_pic_flag[ref_rps->num_negative_pics + j]; -+ } -+ } -+ st_rps->num_positive_pics = i; -+ -+ st_rps->num_delta_pocs = st_rps->num_positive_pics + st_rps->num_negative_pics; -+} -+ -+/* -+ * Compute the short term ref pic set parameters based on the control's data. -+ */ -+static void st_ref_pic_set_calculate(struct rkvdec_hevc_run *run, int idx, -+ struct calculated_rps_st_set *calculated_rps_st_sets) -+{ -+ const struct v4l2_ctrl_hevc_ext_sps_st_rps *rps_data = &run->ext_sps_st_rps[idx]; -+ struct calculated_rps_st_set *st_rps = &calculated_rps_st_sets[idx]; -+ int j, i = 0; -+ -+ /* 7-63 */ -+ st_rps->num_negative_pics = rps_data->num_negative_pics; -+ /* 7-64 */ -+ st_rps->num_positive_pics = rps_data->num_positive_pics; -+ -+ for (i = 0; i < st_rps->num_negative_pics; i++) { -+ /* 7-65 */ -+ st_rps->used_by_curr_pic_s0[i] = !!(rps_data->used_by_curr_pic & (1 << i)); -+ -+ if (i == 0) { -+ /* 7-67 */ -+ st_rps->delta_poc_s0[i] = -(rps_data->delta_poc_s0_minus1[i] + 1); -+ } else { -+ /* 7-69 */ -+ st_rps->delta_poc_s0[i] = -+ st_rps->delta_poc_s0[i - 1] - -+ (rps_data->delta_poc_s0_minus1[i] + 1); -+ } -+ } -+ -+ for (j = 0; j < st_rps->num_positive_pics; j++) { -+ /* 7-66 */ -+ st_rps->used_by_curr_pic_s1[j] = !!(rps_data->used_by_curr_pic & (1 << (i + j))); -+ -+ if (j == 0) { -+ /* 7-68 */ -+ st_rps->delta_poc_s1[j] = rps_data->delta_poc_s1_minus1[j] + 1; -+ } else { -+ /* 7-70 */ -+ st_rps->delta_poc_s1[j] = -+ st_rps->delta_poc_s1[j - 1] + -+ (rps_data->delta_poc_s1_minus1[j] + 1); -+ } -+ } -+ -+ /* 7-71 */ -+ st_rps->num_delta_pocs = st_rps->num_positive_pics + st_rps->num_negative_pics; -+} -+ -+static void rkvdec_hevc_prepare_hw_st_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, -+ struct v4l2_ctrl_hevc_ext_sps_st_rps *cache) -+{ -+ int idx; -+ -+ if (!run->ext_sps_st_rps) -+ return; -+ -+ if (!memcmp(cache, run->ext_sps_st_rps, sizeof(struct v4l2_ctrl_hevc_ext_sps_st_rps))) -+ return; -+ -+ struct calculated_rps_st_set *calculated_rps_st_sets = -+ kzalloc(sizeof(struct calculated_rps_st_set) * -+ run->sps->num_short_term_ref_pic_sets, GFP_KERNEL); -+ -+ for (idx = 0; idx < run->sps->num_short_term_ref_pic_sets; idx++) { -+ const struct v4l2_ctrl_hevc_ext_sps_st_rps *rps_data = &run->ext_sps_st_rps[idx]; -+ -+ if (rps_data->flags & V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED) -+ st_ref_pic_set_prediction(run, idx, calculated_rps_st_sets); -+ else -+ st_ref_pic_set_calculate(run, idx, calculated_rps_st_sets); -+ } -+ -+ rkvdec_hevc_assemble_hw_st_rps(run, rps, calculated_rps_st_sets); -+ -+ kfree(calculated_rps_st_sets); -+ -+ memcpy(cache, run->ext_sps_st_rps, sizeof(struct v4l2_ctrl_hevc_ext_sps_st_rps)); -+} -+ -+void rkvdec_hevc_assemble_hw_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, -+ struct v4l2_ctrl_hevc_ext_sps_st_rps *st_cache) -+{ -+ rkvdec_hevc_prepare_hw_st_rps(run, rps, st_cache); -+ rkvdec_hevc_assemble_hw_lt_rps(run, rps); -+} -+ -+struct vb2_buffer *get_ref_buf(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run, -+ unsigned int dpb_idx) - { - struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; - const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; -@@ -140,9 +485,8 @@ get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, - return buf; - } - --#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 -- --int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f) -+int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, -+ struct v4l2_format *f) - { - struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; - -@@ -153,40 +497,19 @@ int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f) - return 0; - } - --enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, -- struct v4l2_ctrl *ctrl) --{ -- const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; -- -- if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS) -- return RKVDEC_IMG_FMT_ANY; -- -- if (sps->bit_depth_luma_minus8 == 0) { -- if (sps->chroma_format_idc == 2) -- return RKVDEC_IMG_FMT_422_8BIT; -- else -- return RKVDEC_IMG_FMT_420_8BIT; -- } else if (sps->bit_depth_luma_minus8 == 2) { -- if (sps->chroma_format_idc == 2) -- return RKVDEC_IMG_FMT_422_10BIT; -- else -- return RKVDEC_IMG_FMT_420_10BIT; -- } -- -- return RKVDEC_IMG_FMT_ANY; --} -- --static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, -+int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, - const struct v4l2_ctrl_hevc_sps *sps) - { -+ /* Only 4:0:0 and 4:2:0 is supported */ - if (sps->chroma_format_idc > 1) -- /* Only 4:0:0 and 4:2:0 are supported */ - return -EINVAL; -+ -+ /* Luma and chroma bit depth mismatch */ - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) -- /* Luma and chroma bit depth mismatch */ - return -EINVAL; -+ -+ /* Only 8-bit and 10-bit are supported */ - if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) -- /* Only 8-bit and 10-bit is supported */ - return -EINVAL; - - if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || -@@ -197,7 +520,7 @@ static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, - } - - void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, -- struct rkvdec_hevc_run *run) -+ struct rkvdec_hevc_run *run) - { - struct v4l2_ctrl *ctrl; - -@@ -217,6 +540,12 @@ void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, - ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, - V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); - run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS); -+ run->ext_sps_st_rps = ctrl ? ctrl->p_cur.p : NULL; -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS); -+ run->ext_sps_lt_rps = ctrl ? ctrl->p_cur.p : NULL; - - rkvdec_run_preamble(ctx, &run->base); - } -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h -@@ -15,14 +15,68 @@ - * Jeffy Chen - */ - -+#include -+ -+#include "rkvdec.h" -+ -+struct rkvdec_rps_refs { -+ u16 lt_ref_pic_poc_lsb; -+ u16 used_by_curr_pic_lt_flag : 1; -+ u16 reserved : 15; -+} __packed; -+ -+struct rkvdec_rps_short_term_ref_set { -+ u32 num_negative : 4; -+ u32 num_positive : 4; -+ u32 delta_poc0 : 16; -+ u32 used_flag0 : 1; -+ u32 delta_poc1 : 16; -+ u32 used_flag1 : 1; -+ u32 delta_poc2 : 16; -+ u32 used_flag2 : 1; -+ u32 delta_poc3 : 16; -+ u32 used_flag3 : 1; -+ u32 delta_poc4 : 16; -+ u32 used_flag4 : 1; -+ u32 delta_poc5 : 16; -+ u32 used_flag5 : 1; -+ u32 delta_poc6 : 16; -+ u32 used_flag6 : 1; -+ u32 delta_poc7 : 16; -+ u32 used_flag7 : 1; -+ u32 delta_poc8 : 16; -+ u32 used_flag8 : 1; -+ u32 delta_poc9 : 16; -+ u32 used_flag9 : 1; -+ u32 delta_poc10 : 16; -+ u32 used_flag10 : 1; -+ u32 delta_poc11 : 16; -+ u32 used_flag11 : 1; -+ u32 delta_poc12 : 16; -+ u32 used_flag12 : 1; -+ u32 delta_poc13 : 16; -+ u32 used_flag13 : 1; -+ u32 delta_poc14 : 16; -+ u32 used_flag14 : 1; -+ u32 reserved_bits : 25; -+ u32 reserved[3]; -+} __packed; -+ -+struct rkvdec_rps { -+ struct rkvdec_rps_refs refs[32]; -+ struct rkvdec_rps_short_term_ref_set short_term_ref_sets[64]; -+} __packed; -+ - struct rkvdec_hevc_run { -- struct rkvdec_run base; -- const struct v4l2_ctrl_hevc_slice_params *slices_params; -- const struct v4l2_ctrl_hevc_decode_params *decode_params; -- const struct v4l2_ctrl_hevc_sps *sps; -- const struct v4l2_ctrl_hevc_pps *pps; -- const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -- int num_slices; -+ struct rkvdec_run base; -+ const struct v4l2_ctrl_hevc_decode_params *decode_params; -+ const struct v4l2_ctrl_hevc_slice_params *slices_params; -+ const struct v4l2_ctrl_hevc_sps *sps; -+ const struct v4l2_ctrl_hevc_pps *pps; -+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; -+ const struct v4l2_ctrl_hevc_ext_sps_st_rps *ext_sps_st_rps; -+ const struct v4l2_ctrl_hevc_ext_sps_lt_rps *ext_sps_lt_rps; -+ int num_slices; - }; - - struct scaling_factor { -@@ -32,15 +86,27 @@ struct scaling_factor { - u8 reserved[4]; /*16Bytes align*/ - }; - -+#define RKV_HEVC_CABAC_TABLE_SIZE 27456 -+extern const u8 rkvdec_hevc_cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; -+ - enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, - struct v4l2_ctrl *ctrl); --void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_hevc_run *run, -+void compute_tiles_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, -+ u16 width, u16 height, s32 pic_in_cts_width, -+ s32 pic_in_cts_height, u16 *column_width, u16 *row_height); -+void compute_tiles_non_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size, -+ u16 width, u16 height, s32 pic_in_cts_width, -+ s32 pic_in_cts_height, u16 *column_width, u16 *row_height); -+void rkvdec_hevc_assemble_hw_rps(struct rkvdec_hevc_run *run, struct rkvdec_rps *rps, -+ struct v4l2_ctrl_hevc_ext_sps_st_rps *st_cache); -+void rkvdec_hevc_assemble_hw_scaling_list(struct rkvdec_dev *rkvdec, -+ struct rkvdec_hevc_run *run, - struct scaling_factor *scaling_factor, - struct v4l2_ctrl_hevc_scaling_matrix *cache); - struct vb2_buffer *get_ref_buf(struct rkvdec_ctx *ctx, - struct rkvdec_hevc_run *run, - unsigned int dpb_idx); - int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f); --//int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, const struct v4l2_ctrl_hevc_sps *sps); -+int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, const struct v4l2_ctrl_hevc_sps *sps); - int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl); - void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run); -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c -@@ -25,9 +25,6 @@ - #define RKV_RPS_SIZE (32 / 4) - #define RKV_RPS_LEN 600 - --#define RKV_HEVC_CABAC_TABLE_SIZE 27456 --extern const u8 rkvdec_hevc_cabac_table[RKV_HEVC_CABAC_TABLE_SIZE]; -- - struct rkvdec_sps_pps_packet { - u32 info[RKV_PPS_SIZE]; - }; -@@ -550,7 +547,7 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) - - rkvdec_hevc_run_preamble(ctx, &run); - -- rkvdec_hevc_assemble_hw_scaling_list(&run, &tbl->scaling_list, -+ rkvdec_hevc_assemble_hw_scaling_list(rkvdec, &run, &tbl->scaling_list, - &hevc_ctx->scaling_matrix_cache); - assemble_hw_pps(ctx, &run); - assemble_hw_rps(ctx, &run); -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu381-hevc.c -@@ -0,0 +1,588 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip VDPU381 HEVC backend -+ * -+ * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-rcb.h" -+#include "rkvdec-hevc-common.h" -+#include "rkvdec-vdpu381-regs.h" -+ -+// SPS -+struct rkvdec_hevc_sps { -+ u16 video_parameters_set_id : 4; -+ u16 seq_parameters_set_id_sps : 4; -+ u16 chroma_format_idc : 2; -+ u16 width : 16; -+ u16 height : 16; -+ u16 bit_depth_luma : 4; -+ u16 bit_depth_chroma : 4; -+ u16 max_pic_order_count_lsb : 5; -+ u16 diff_max_min_luma_coding_block_size : 2; -+ u16 min_luma_coding_block_size : 3; -+ u16 min_transform_block_size : 3; -+ u16 diff_max_min_transform_block_size : 2; -+ u16 max_transform_hierarchy_depth_inter : 3; -+ u16 max_transform_hierarchy_depth_intra : 3; -+ u16 scaling_list_enabled_flag : 1; -+ u16 amp_enabled_flag : 1; -+ u16 sample_adaptive_offset_enabled_flag : 1; -+ u16 pcm_enabled_flag : 1; -+ u16 pcm_sample_bit_depth_luma : 4; -+ u16 pcm_sample_bit_depth_chroma : 4; -+ u16 pcm_loop_filter_disabled_flag : 1; -+ u16 diff_max_min_pcm_luma_coding_block_size : 3; -+ u16 min_pcm_luma_coding_block_size : 3; -+ u16 num_short_term_ref_pic_sets : 7; -+ u16 long_term_ref_pics_present_flag : 1; -+ u16 num_long_term_ref_pics_sps : 6; -+ u16 sps_temporal_mvp_enabled_flag : 1; -+ u16 strong_intra_smoothing_enabled_flag : 1; -+ u16 reserved_0 : 7; -+ u16 sps_max_dec_pic_buffering_minus1 : 4; -+ u16 reserved_0_2 : 3; -+ u16 reserved_f : 8; -+} __packed; -+ -+//PPS -+struct rkvdec_hevc_pps { -+ u16 picture_parameters_set_id : 6; -+ u16 seq_parameters_set_id_pps : 4; -+ u16 dependent_slice_segments_enabled_flag : 1; -+ u16 output_flag_present_flag : 1; -+ u16 num_extra_slice_header_bits : 13; -+ u16 sign_data_hiding_enabled_flag : 1; -+ u16 cabac_init_present_flag : 1; -+ u16 num_ref_idx_l0_default_active : 4; -+ u16 num_ref_idx_l1_default_active : 4; -+ u16 init_qp_minus26 : 7; -+ u16 constrained_intra_pred_flag : 1; -+ u16 transform_skip_enabled_flag : 1; -+ u16 cu_qp_delta_enabled_flag : 1; -+ u16 log2_min_cb_size : 3; -+ u16 pps_cb_qp_offset : 5; -+ u16 pps_cr_qp_offset : 5; -+ u16 pps_slice_chroma_qp_offsets_present_flag : 1; -+ u16 weighted_pred_flag : 1; -+ u16 weighted_bipred_flag : 1; -+ u16 transquant_bypass_enabled_flag : 1; -+ u16 tiles_enabled_flag : 1; -+ u16 entropy_coding_sync_enabled_flag : 1; -+ u16 pps_loop_filter_across_slices_enabled_flag : 1; -+ u16 loop_filter_across_tiles_enabled_flag : 1; -+ u16 deblocking_filter_override_enabled_flag : 1; -+ u16 pps_deblocking_filter_disabled_flag : 1; -+ u16 pps_beta_offset_div2 : 4; -+ u16 pps_tc_offset_div2 : 4; -+ u16 lists_modification_present_flag : 1; -+ u16 log2_parallel_merge_level : 3; -+ u16 slice_segment_header_extension_present_flag : 1; -+ u16 zeroes : 3; -+ u16 num_tile_columns : 5; -+ u16 num_tile_rows : 5; -+ u16 sps_pps_mode : 4; -+ u16 reserved_bits : 14; -+ u16 reserved; -+} __packed; -+ -+struct rkvdec_hevc_tile { -+ u16 value0 : 12; -+ u16 value1 : 12; -+} __packed; -+ -+struct rkvdec_sps_pps_packet { -+ struct rkvdec_hevc_sps sps; -+ struct rkvdec_hevc_pps pps; -+ struct rkvdec_hevc_tile column_width[10]; -+ struct rkvdec_hevc_tile row_height[11]; -+ u32 zeroes[3]; -+ u32 zeroes_bits : 6; -+ u32 padding_bits : 2; -+ u32 padding; -+} __packed; -+ -+struct rkvdec_hevc_priv_tbl { -+ struct rkvdec_sps_pps_packet param_set[64]; -+ struct rkvdec_rps rps; -+ struct scaling_factor scaling_list; -+ u8 cabac_table[27456]; -+}; -+ -+struct rkvdec_hevc_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+ struct v4l2_ctrl_hevc_ext_sps_st_rps st_cache; -+ struct rkvdec_vdpu381_regs_hevc regs; -+}; -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_hevc_ctx *h264_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps_packet *hw_ps; -+ bool tiles_enabled; -+ s32 max_cu_width; -+ s32 pic_in_cts_width; -+ s32 pic_in_cts_height; -+ u16 log2_min_cb_size, width, height; -+ u16 column_width[20]; -+ u16 row_height[22]; -+ u8 pcm_enabled; -+ u32 i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 32 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ /* write sps */ -+ hw_ps->sps.video_parameters_set_id = sps->video_parameter_set_id; -+ hw_ps->sps.seq_parameters_set_id_sps = sps->seq_parameter_set_id; -+ hw_ps->sps.chroma_format_idc = sps->chroma_format_idc; -+ -+ log2_min_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ width = sps->pic_width_in_luma_samples; -+ height = sps->pic_height_in_luma_samples; -+ hw_ps->sps.width = width; -+ hw_ps->sps.height = height; -+ hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8 + 8; -+ hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8 + 8; -+ hw_ps->sps.max_pic_order_count_lsb = sps->log2_max_pic_order_cnt_lsb_minus4 + 4; -+ hw_ps->sps.diff_max_min_luma_coding_block_size = -+ sps->log2_diff_max_min_luma_coding_block_size; -+ hw_ps->sps.min_luma_coding_block_size = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ hw_ps->sps.min_transform_block_size = sps->log2_min_luma_transform_block_size_minus2 + 2; -+ hw_ps->sps.diff_max_min_transform_block_size = -+ sps->log2_diff_max_min_luma_transform_block_size; -+ hw_ps->sps.max_transform_hierarchy_depth_inter = sps->max_transform_hierarchy_depth_inter; -+ hw_ps->sps.max_transform_hierarchy_depth_intra = sps->max_transform_hierarchy_depth_intra; -+ hw_ps->sps.scaling_list_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED); -+ hw_ps->sps.amp_enabled_flag = !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED); -+ hw_ps->sps.sample_adaptive_offset_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET); -+ -+ pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED); -+ hw_ps->sps.pcm_enabled_flag = pcm_enabled; -+ hw_ps->sps.pcm_sample_bit_depth_luma = -+ pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0; -+ hw_ps->sps.pcm_sample_bit_depth_chroma = -+ pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0; -+ hw_ps->sps.pcm_loop_filter_disabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED); -+ hw_ps->sps.diff_max_min_pcm_luma_coding_block_size = -+ sps->log2_diff_max_min_pcm_luma_coding_block_size; -+ hw_ps->sps.min_pcm_luma_coding_block_size = -+ pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0; -+ hw_ps->sps.num_short_term_ref_pic_sets = sps->num_short_term_ref_pic_sets; -+ hw_ps->sps.long_term_ref_pics_present_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT); -+ hw_ps->sps.num_long_term_ref_pics_sps = sps->num_long_term_ref_pics_sps; -+ hw_ps->sps.sps_temporal_mvp_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED); -+ hw_ps->sps.strong_intra_smoothing_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED); -+ hw_ps->sps.sps_max_dec_pic_buffering_minus1 = sps->sps_max_dec_pic_buffering_minus1; -+ hw_ps->sps.reserved_f = 0xff; -+ -+ /* write pps */ -+ hw_ps->pps.picture_parameters_set_id = pps->pic_parameter_set_id; -+ hw_ps->pps.seq_parameters_set_id_pps = sps->seq_parameter_set_id; -+ hw_ps->pps.dependent_slice_segments_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED); -+ hw_ps->pps.output_flag_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT); -+ hw_ps->pps.num_extra_slice_header_bits = pps->num_extra_slice_header_bits; -+ hw_ps->pps.sign_data_hiding_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED); -+ hw_ps->pps.cabac_init_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT); -+ hw_ps->pps.num_ref_idx_l0_default_active = pps->num_ref_idx_l0_default_active_minus1 + 1; -+ hw_ps->pps.num_ref_idx_l1_default_active = pps->num_ref_idx_l1_default_active_minus1 + 1; -+ hw_ps->pps.init_qp_minus26 = pps->init_qp_minus26; -+ hw_ps->pps.constrained_intra_pred_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED); -+ hw_ps->pps.transform_skip_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED); -+ hw_ps->pps.cu_qp_delta_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED); -+ hw_ps->pps.log2_min_cb_size = log2_min_cb_size + -+ sps->log2_diff_max_min_luma_coding_block_size - -+ pps->diff_cu_qp_delta_depth; -+ hw_ps->pps.pps_cb_qp_offset = pps->pps_cb_qp_offset; -+ hw_ps->pps.pps_cr_qp_offset = pps->pps_cr_qp_offset; -+ hw_ps->pps.pps_slice_chroma_qp_offsets_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT); -+ hw_ps->pps.weighted_pred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED); -+ hw_ps->pps.weighted_bipred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED); -+ hw_ps->pps.transquant_bypass_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED); -+ -+ tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED); -+ hw_ps->pps.tiles_enabled_flag = tiles_enabled; -+ hw_ps->pps.entropy_coding_sync_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED); -+ hw_ps->pps.pps_loop_filter_across_slices_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED); -+ hw_ps->pps.loop_filter_across_tiles_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED); -+ hw_ps->pps.deblocking_filter_override_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED); -+ hw_ps->pps.pps_deblocking_filter_disabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER); -+ hw_ps->pps.pps_beta_offset_div2 = pps->pps_beta_offset_div2; -+ hw_ps->pps.pps_tc_offset_div2 = pps->pps_tc_offset_div2; -+ hw_ps->pps.lists_modification_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT); -+ hw_ps->pps.log2_parallel_merge_level = pps->log2_parallel_merge_level_minus2 + 2; -+ hw_ps->pps.slice_segment_header_extension_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT); -+ hw_ps->pps.num_tile_columns = tiles_enabled ? pps->num_tile_columns_minus1 + 1 : 0; -+ hw_ps->pps.num_tile_rows = tiles_enabled ? pps->num_tile_rows_minus1 + 1 : 0; -+ hw_ps->pps.sps_pps_mode = 0; -+ hw_ps->pps.reserved_bits = 0x3fff; -+ hw_ps->pps.reserved = 0xffff; -+ -+ // Setup tiles information -+ memset(column_width, 0, sizeof(column_width)); -+ memset(row_height, 0, sizeof(row_height)); -+ -+ max_cu_width = 1 << (sps->log2_diff_max_min_luma_coding_block_size + log2_min_cb_size); -+ pic_in_cts_width = (width + max_cu_width - 1) / max_cu_width; -+ pic_in_cts_height = (height + max_cu_width - 1) / max_cu_width; -+ -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) { -+ compute_tiles_uniform(run, log2_min_cb_size, width, height, -+ pic_in_cts_width, pic_in_cts_height, -+ column_width, row_height); -+ } else { -+ compute_tiles_non_uniform(run, log2_min_cb_size, width, height, -+ pic_in_cts_width, pic_in_cts_height, -+ column_width, row_height); -+ } -+ } else { -+ column_width[0] = (width + max_cu_width - 1) / max_cu_width; -+ row_height[0] = (height + max_cu_width - 1) / max_cu_width; -+ } -+ -+ for (i = 0; i < 20; i++) { -+ if (column_width[i] > 0) -+ column_width[i]--; -+ -+ if (i & 1) -+ hw_ps->column_width[i / 2].value1 = column_width[i]; -+ else -+ hw_ps->column_width[i / 2].value0 = column_width[i]; -+ } -+ -+ for (i = 0; i < 22; i++) { -+ if (row_height[i] > 0) -+ row_height[i]--; -+ -+ if (i & 1) -+ hw_ps->row_height[i / 2].value1 = row_height[i]; -+ else -+ hw_ps->row_height[i / 2].value0 = row_height[i]; -+ } -+ -+ hw_ps->padding = 0xffffffff; -+ hw_ps->padding_bits = 0x3; -+} -+ -+static void set_ref_valid(struct rkvdec_vdpu381_regs_hevc *regs, int id, u32 valid) -+{ -+ switch (id) { -+ case 0: -+ regs->hevc_param.reg099.hevc_ref_valid_0 = valid; -+ break; -+ case 1: -+ regs->hevc_param.reg099.hevc_ref_valid_1 = valid; -+ break; -+ case 2: -+ regs->hevc_param.reg099.hevc_ref_valid_2 = valid; -+ break; -+ case 3: -+ regs->hevc_param.reg099.hevc_ref_valid_3 = valid; -+ break; -+ case 4: -+ regs->hevc_param.reg099.hevc_ref_valid_4 = valid; -+ break; -+ case 5: -+ regs->hevc_param.reg099.hevc_ref_valid_5 = valid; -+ break; -+ case 6: -+ regs->hevc_param.reg099.hevc_ref_valid_6 = valid; -+ break; -+ case 7: -+ regs->hevc_param.reg099.hevc_ref_valid_7 = valid; -+ break; -+ case 8: -+ regs->hevc_param.reg099.hevc_ref_valid_8 = valid; -+ break; -+ case 9: -+ regs->hevc_param.reg099.hevc_ref_valid_9 = valid; -+ break; -+ case 10: -+ regs->hevc_param.reg099.hevc_ref_valid_10 = valid; -+ break; -+ case 11: -+ regs->hevc_param.reg099.hevc_ref_valid_11 = valid; -+ break; -+ case 12: -+ regs->hevc_param.reg099.hevc_ref_valid_12 = valid; -+ break; -+ case 13: -+ regs->hevc_param.reg099.hevc_ref_valid_13 = valid; -+ break; -+ case 14: -+ regs->hevc_param.reg099.hevc_ref_valid_14 = valid; -+ break; -+ } -+} -+ -+static void rkvdec_write_regs(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_COMMON_REGS, -+ &hevc_ctx->regs.common, -+ sizeof(hevc_ctx->regs.common)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_CODEC_PARAMS_REGS, -+ &hevc_ctx->regs.hevc_param, -+ sizeof(hevc_ctx->regs.hevc_param)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_COMMON_ADDR_REGS, -+ &hevc_ctx->regs.common_addr, -+ sizeof(hevc_ctx->regs.common_addr)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_CODEC_ADDR_REGS, -+ &hevc_ctx->regs.hevc_addr, -+ sizeof(hevc_ctx->regs.hevc_addr)); -+ rkvdec_memcpy_toio(rkvdec->regs + OFFSET_POC_HIGHBIT_REGS, -+ &hevc_ctx->regs.hevc_highpoc, -+ sizeof(hevc_ctx->regs.hevc_highpoc)); -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_decode_params *dec_params = run->decode_params; -+ const struct v4l2_hevc_dpb_entry *dpb = dec_params->dpb; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_vdpu381_regs_hevc *regs = &hevc_ctx->regs; -+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ u32 hor_virstride = 0; -+ u32 ver_virstride = 0; -+ u32 y_virstride = 0; -+ u32 offset; -+ u32 pixels; -+ dma_addr_t dst_addr; -+ u32 i; -+ -+ memset(regs, 0, sizeof(*regs)); -+ -+ /* Set HEVC mode */ -+ regs->common.reg009.dec_mode = VDPU381_MODE_HEVC; -+ -+ /* Set config */ -+ regs->common.reg011.buf_empty_en = 1; -+ regs->common.reg011.dec_clkgate_e = 1; -+ regs->common.reg011.dec_timeout_e = 1; -+ regs->common.reg011.pix_range_detection_e = 1; -+ -+ /* Set IDR flag */ -+ regs->common.reg013.cur_pic_is_idr = -+ !!(dec_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC); -+ -+ /* Set input stream length */ -+ regs->common.stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ -+ /* Set max slice number */ -+ regs->common.reg017.slice_num = 1; -+ -+ /* Set strides */ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ pixels = dst_fmt->height * dst_fmt->width; -+ -+ regs->common.reg018.y_hor_virstride = hor_virstride / 16; -+ regs->common.reg019.uv_hor_virstride = hor_virstride / 16; -+ regs->common.reg020.y_virstride = y_virstride / 16; -+ -+ /* Activate block gating */ -+ regs->common.reg026.swreg_block_gating_e = 0xfffef; -+ regs->common.reg026.reg_cfg_gating_en = 1; -+ -+ /* Set timeout threshold */ -+ if (pixels < RKVDEC_1080P_PIXELS) -+ regs->common.timeout_threshold = RKVDEC_TIMEOUT_1080p; -+ else if (pixels < RKVDEC_4K_PIXELS) -+ regs->common.timeout_threshold = RKVDEC_TIMEOUT_4K; -+ else if (pixels < RKVDEC_8K_PIXELS) -+ regs->common.timeout_threshold = RKVDEC_TIMEOUT_8K; -+ -+ /* Set POC val */ -+ regs->hevc_param.cur_top_poc = dec_params->pic_order_cnt_val; -+ -+ /* Set ref pic address & poc */ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); -+ dma_addr_t buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ u32 valid = !!(dec_params->num_active_dpb_entries > i); -+ -+ /* Set reference addresses */ -+ regs->hevc_addr.ref_base[i] = buf_dma; -+ -+ /* Set COLMV addresses */ -+ regs->hevc_addr.colmv_base[i] = buf_dma + ctx->colmv_offset; -+ -+ regs->hevc_param.reg067_082_ref_poc[i] = -+ dpb[i].pic_order_cnt_val; -+ -+ set_ref_valid(regs, i, valid); -+ regs->hevc_param.reg103.ref_pic_layer_same_with_cur |= 1 << i; -+ } -+ -+ /* Set rlc base address (input stream) */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ regs->common_addr.rlc_base = rlc_addr; -+ regs->common_addr.rlcwrite_base = rlc_addr; -+ -+ /* Set output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ regs->common_addr.decout_base = dst_addr; -+ regs->common_addr.error_ref_base = dst_addr; -+ -+ /* Set colmv address */ -+ regs->common_addr.colmv_cur_base = dst_addr + ctx->colmv_offset; -+ -+ /* Set RCB addresses */ -+ for (i = 0; i < rkvdec_rcb_buf_count(ctx); i++) -+ regs->common_addr.rcb_base[i] = rkvdec_rcb_buf_dma_addr(ctx, i); -+ -+ /* Set hw pps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -+ regs->hevc_addr.pps_base = priv_start_addr + offset; -+ -+ /* Set hw rps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -+ regs->hevc_addr.rps_base = priv_start_addr + offset; -+ -+ /* Set cabac table */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -+ regs->hevc_addr.cabactbl_base = priv_start_addr + offset; -+ -+ /* Set scaling matrix */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); -+ regs->hevc_addr.scanlist_addr = priv_start_addr + offset; -+ -+ rkvdec_write_regs(ctx); -+} -+ -+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_priv_tbl *priv_tbl; -+ struct rkvdec_hevc_ctx *hevc_ctx; -+ struct v4l2_ctrl *ctrl; -+ int ret; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ if (ret) -+ return ret; -+ -+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); -+ if (!hevc_ctx) -+ return -ENOMEM; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ hevc_ctx->priv_tbl.cpu = priv_tbl; -+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, -+ sizeof(rkvdec_hevc_cabac_table)); -+ -+ ctx->priv = hevc_ctx; -+ return 0; -+ -+err_free_ctx: -+ kfree(hevc_ctx); -+ return ret; -+} -+ -+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, -+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); -+ kfree(hevc_ctx); -+} -+ -+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_run run; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -+ -+ rkvdec_hevc_run_preamble(ctx, &run); -+ -+ rkvdec_hevc_assemble_hw_scaling_list(rkvdec, -+ &run, -+ &tbl->scaling_list, -+ &hevc_ctx->scaling_matrix_cache); -+ assemble_hw_pps(ctx, &run); -+ rkvdec_hevc_assemble_hw_rps(&run, &tbl->rps, &hevc_ctx->st_cache); -+ -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); -+ -+ /* Start decoding! */ -+ writel(VDPU381_DEC_E_BIT, rkvdec->regs + VDPU381_REG_DEC_E); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_hevc_fmt_ops = { -+ .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .start = rkvdec_hevc_start, -+ .stop = rkvdec_hevc_stop, -+ .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .get_image_fmt = rkvdec_hevc_get_image_fmt, -+}; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c -@@ -0,0 +1,582 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip Video Decoder VDPU383 H264 backend -+ * -+ * Copyright (C) 2024 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "rkvdec-rcb.h" -+#include "rkvdec-vdpu383-regs.h" -+#include "rkvdec-h264-common.h" -+ -+struct rkvdec_sps { -+ u16 seq_parameter_set_id: 4; -+ u16 profile_idc: 8; -+ u16 constraint_set3_flag: 1; -+ u16 chroma_format_idc: 2; -+ u16 bit_depth_luma: 3; -+ u16 bit_depth_chroma: 3; -+ u16 qpprime_y_zero_transform_bypass_flag: 1; -+ u16 log2_max_frame_num_minus4: 4; -+ u16 max_num_ref_frames: 5; -+ u16 pic_order_cnt_type: 2; -+ u16 log2_max_pic_order_cnt_lsb_minus4: 4; -+ u16 delta_pic_order_always_zero_flag: 1; -+ -+ u16 pic_width_in_mbs: 16; -+ u16 pic_height_in_mbs: 16; -+ -+ u16 frame_mbs_only_flag: 1; -+ u16 mb_adaptive_frame_field_flag: 1; -+ u16 direct_8x8_inference_flag: 1; -+ u16 mvc_extension_enable: 1; -+ u16 num_views: 2; -+ u16 view_id0: 10; -+ u16 view_id1: 10; -+} __packed; -+ -+struct rkvdec_pps { -+ u32 pic_parameter_set_id: 8; -+ u32 pps_seq_parameter_set_id: 5; -+ u32 entropy_coding_mode_flag: 1; -+ u32 bottom_field_pic_order_in_frame_present_flag: 1; -+ u32 num_ref_idx_l0_default_active_minus1: 5; -+ u32 num_ref_idx_l1_default_active_minus1: 5; -+ u32 weighted_pred_flag: 1; -+ u32 weighted_bipred_idc: 2; -+ u32 pic_init_qp_minus26: 7; -+ u32 pic_init_qs_minus26: 6; -+ u32 chroma_qp_index_offset: 5; -+ u32 deblocking_filter_control_present_flag: 1; -+ u32 constrained_intra_pred_flag: 1; -+ u32 redundant_pic_cnt_present: 1; -+ u32 transform_8x8_mode_flag: 1; -+ u32 second_chroma_qp_index_offset: 5; -+ u32 scaling_list_enable_flag: 1; -+ u32 is_longterm: 16; -+ u32 voidx: 16; -+ -+ // dpb -+ u32 pic_field_flag: 1; -+ u32 pic_associated_flag: 1; -+ u32 cur_top_field: 32; -+ u32 cur_bot_field: 32; -+ -+ u32 top_field_order_cnt0: 32; -+ u32 bot_field_order_cnt0: 32; -+ u32 top_field_order_cnt1: 32; -+ u32 bot_field_order_cnt1: 32; -+ u32 top_field_order_cnt2: 32; -+ u32 bot_field_order_cnt2: 32; -+ u32 top_field_order_cnt3: 32; -+ u32 bot_field_order_cnt3: 32; -+ u32 top_field_order_cnt4: 32; -+ u32 bot_field_order_cnt4: 32; -+ u32 top_field_order_cnt5: 32; -+ u32 bot_field_order_cnt5: 32; -+ u32 top_field_order_cnt6: 32; -+ u32 bot_field_order_cnt6: 32; -+ u32 top_field_order_cnt7: 32; -+ u32 bot_field_order_cnt7: 32; -+ u32 top_field_order_cnt8: 32; -+ u32 bot_field_order_cnt8: 32; -+ u32 top_field_order_cnt9: 32; -+ u32 bot_field_order_cnt9: 32; -+ u32 top_field_order_cnt10: 32; -+ u32 bot_field_order_cnt10: 32; -+ u32 top_field_order_cnt11: 32; -+ u32 bot_field_order_cnt11: 32; -+ u32 top_field_order_cnt12: 32; -+ u32 bot_field_order_cnt12: 32; -+ u32 top_field_order_cnt13: 32; -+ u32 bot_field_order_cnt13: 32; -+ u32 top_field_order_cnt14: 32; -+ u32 bot_field_order_cnt14: 32; -+ u32 top_field_order_cnt15: 32; -+ u32 bot_field_order_cnt15: 32; -+ -+ u32 ref_field_flags: 16; -+ u32 ref_topfield_used: 16; -+ u32 ref_botfield_used: 16; -+ u32 ref_colmv_use_flag: 16; -+ -+ u32 reserved0: 30; -+ u32 reserved[3]; -+} __packed; -+ -+struct rkvdec_sps_pps { -+ struct rkvdec_sps sps; -+ struct rkvdec_pps pps; -+} __packed; -+ -+/* Data structure describing auxiliary buffer format. */ -+struct rkvdec_h264_priv_tbl { -+ s8 cabac_table[4][464][2]; -+ struct rkvdec_h264_scaling_list scaling_list; -+ struct rkvdec_sps_pps param_set[256]; -+ struct rkvdec_rps rps; -+} __packed; -+ -+struct rkvdec_h264_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct rkvdec_h264_reflists reflists; -+ struct vdpu383_regs_h26x regs; -+}; -+ -+static void set_field_order_cnt(struct rkvdec_sps_pps *hw_ps, int id, u32 top, u32 bottom) -+{ -+ switch (id) { -+ case 0: -+ hw_ps->pps.top_field_order_cnt0 = top; -+ hw_ps->pps.bot_field_order_cnt0 = bottom; -+ break; -+ case 1: -+ hw_ps->pps.top_field_order_cnt1 = top; -+ hw_ps->pps.bot_field_order_cnt1 = bottom; -+ break; -+ case 2: -+ hw_ps->pps.top_field_order_cnt2 = top; -+ hw_ps->pps.bot_field_order_cnt2 = bottom; -+ break; -+ case 3: -+ hw_ps->pps.top_field_order_cnt3 = top; -+ hw_ps->pps.bot_field_order_cnt3 = bottom; -+ break; -+ case 4: -+ hw_ps->pps.top_field_order_cnt4 = top; -+ hw_ps->pps.bot_field_order_cnt4 = bottom; -+ break; -+ case 5: -+ hw_ps->pps.top_field_order_cnt5 = top; -+ hw_ps->pps.bot_field_order_cnt5 = bottom; -+ break; -+ case 6: -+ hw_ps->pps.top_field_order_cnt6 = top; -+ hw_ps->pps.bot_field_order_cnt6 = bottom; -+ break; -+ case 7: -+ hw_ps->pps.top_field_order_cnt7 = top; -+ hw_ps->pps.bot_field_order_cnt7 = bottom; -+ break; -+ case 8: -+ hw_ps->pps.top_field_order_cnt8 = top; -+ hw_ps->pps.bot_field_order_cnt8 = bottom; -+ break; -+ case 9: -+ hw_ps->pps.top_field_order_cnt9 = top; -+ hw_ps->pps.bot_field_order_cnt9 = bottom; -+ break; -+ case 10: -+ hw_ps->pps.top_field_order_cnt10 = top; -+ hw_ps->pps.bot_field_order_cnt10 = bottom; -+ break; -+ case 11: -+ hw_ps->pps.top_field_order_cnt11 = top; -+ hw_ps->pps.bot_field_order_cnt11 = bottom; -+ break; -+ case 12: -+ hw_ps->pps.top_field_order_cnt12 = top; -+ hw_ps->pps.bot_field_order_cnt12 = bottom; -+ break; -+ case 13: -+ hw_ps->pps.top_field_order_cnt13 = top; -+ hw_ps->pps.bot_field_order_cnt13 = bottom; -+ break; -+ case 14: -+ hw_ps->pps.top_field_order_cnt14 = top; -+ hw_ps->pps.bot_field_order_cnt14 = bottom; -+ break; -+ case 15: -+ hw_ps->pps.top_field_order_cnt15 = top; -+ hw_ps->pps.bot_field_order_cnt15 = bottom; -+ break; -+ } -+} -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_h264_run *run) -+{ -+ struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -+ const struct v4l2_ctrl_h264_sps *sps = run->sps; -+ const struct v4l2_ctrl_h264_pps *pps = run->pps; -+ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -+ const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb; -+ struct rkvdec_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; -+ struct rkvdec_sps_pps *hw_ps; -+ u32 pic_width, pic_height; -+ u32 i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 32 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ /* write sps */ -+ hw_ps->sps.seq_parameter_set_id = sps->seq_parameter_set_id; -+ hw_ps->sps.profile_idc = sps->profile_idc; -+ hw_ps->sps.constraint_set3_flag = !!(sps->constraint_set_flags & (1 << 3)); -+ hw_ps->sps.chroma_format_idc = sps->chroma_format_idc; -+ hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8; -+ hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8; -+ hw_ps->sps.qpprime_y_zero_transform_bypass_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS); -+ hw_ps->sps.log2_max_frame_num_minus4 = sps->log2_max_frame_num_minus4; -+ hw_ps->sps.max_num_ref_frames = sps->max_num_ref_frames; -+ hw_ps->sps.pic_order_cnt_type = sps->pic_order_cnt_type; -+ hw_ps->sps.log2_max_pic_order_cnt_lsb_minus4 = -+ sps->log2_max_pic_order_cnt_lsb_minus4; -+ hw_ps->sps.delta_pic_order_always_zero_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO); -+ hw_ps->sps.mvc_extension_enable = 0; -+ hw_ps->sps.num_views = 0; -+ -+ /* -+ * Use the SPS values since they are already in macroblocks -+ * dimensions, height can be field height (halved) if -+ * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY is not set and also it allows -+ * decoding smaller images into larger allocation which can be used -+ * to implementing SVC spatial layer support. -+ */ -+ pic_width = 16 * (sps->pic_width_in_mbs_minus1 + 1); -+ pic_height = 16 * (sps->pic_height_in_map_units_minus1 + 1); -+ if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY)) -+ pic_height *= 2; -+ if (!!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC)) -+ pic_height /= 2; -+ -+ hw_ps->sps.pic_width_in_mbs = pic_width; -+ hw_ps->sps.pic_height_in_mbs = pic_height; -+ -+ hw_ps->sps.frame_mbs_only_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY); -+ hw_ps->sps.mb_adaptive_frame_field_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); -+ hw_ps->sps.direct_8x8_inference_flag = -+ !!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE); -+ -+ /* write pps */ -+ hw_ps->pps.pic_parameter_set_id = pps->pic_parameter_set_id; -+ hw_ps->pps.pps_seq_parameter_set_id = pps->seq_parameter_set_id; -+ hw_ps->pps.entropy_coding_mode_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); -+ hw_ps->pps.bottom_field_pic_order_in_frame_present_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); -+ hw_ps->pps.num_ref_idx_l0_default_active_minus1 = -+ pps->num_ref_idx_l0_default_active_minus1; -+ hw_ps->pps.num_ref_idx_l1_default_active_minus1 = -+ pps->num_ref_idx_l1_default_active_minus1; -+ hw_ps->pps.weighted_pred_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED); -+ hw_ps->pps.weighted_bipred_idc = pps->weighted_bipred_idc; -+ hw_ps->pps.pic_init_qp_minus26 = pps->pic_init_qp_minus26; -+ hw_ps->pps.pic_init_qs_minus26 = pps->pic_init_qs_minus26; -+ hw_ps->pps.chroma_qp_index_offset = pps->chroma_qp_index_offset; -+ hw_ps->pps.deblocking_filter_control_present_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT); -+ hw_ps->pps.constrained_intra_pred_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED); -+ hw_ps->pps.redundant_pic_cnt_present = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT); -+ hw_ps->pps.transform_8x8_mode_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE); -+ hw_ps->pps.second_chroma_qp_index_offset = pps->second_chroma_qp_index_offset; -+ hw_ps->pps.scaling_list_enable_flag = -+ !!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT); -+ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM) -+ hw_ps->pps.is_longterm |= (1 << i); -+ -+ set_field_order_cnt(hw_ps, i, dpb[i].top_field_order_cnt, -+ dpb[i].bottom_field_order_cnt); -+ -+ hw_ps->pps.ref_field_flags |= -+ (!!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD)) << i; -+ hw_ps->pps.ref_colmv_use_flag |= -+ (!!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) << i; -+ hw_ps->pps.ref_topfield_used |= -+ (!!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF)) << i; -+ hw_ps->pps.ref_botfield_used |= -+ (!!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF)) << i; -+ } -+ -+ hw_ps->pps.pic_field_flag = -+ !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC); -+ hw_ps->pps.pic_associated_flag = -+ !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD); -+ -+ hw_ps->pps.cur_top_field = dec_params->top_field_order_cnt; -+ hw_ps->pps.cur_bot_field = dec_params->bottom_field_order_cnt; -+} -+ -+static void rkvdec_write_regs(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -+ -+ rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_COMMON_REGS, -+ &h264_ctx->regs.common, -+ sizeof(h264_ctx->regs.common)); -+ rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_COMMON_ADDR_REGS, -+ &h264_ctx->regs.common_addr, -+ sizeof(h264_ctx->regs.common_addr)); -+ rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_CODEC_PARAMS_REGS, -+ &h264_ctx->regs.h26x_params, -+ sizeof(h264_ctx->regs.h26x_params)); -+ rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_CODEC_ADDR_REGS, -+ &h264_ctx->regs.h26x_addr, -+ sizeof(h264_ctx->regs.h26x_addr)); -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_h264_run *run) -+{ -+ const struct v4l2_ctrl_h264_decode_params *dec_params = run->decode_params; -+ struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -+ dma_addr_t priv_start_addr = h264_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ struct vdpu383_regs_h26x *regs = &h264_ctx->regs; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t dst_addr; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; -+ u32 offset; -+ u32 pixels; -+ u32 i; -+ -+ memset(regs, 0, sizeof(*regs)); -+ -+ /* Set H264 mode */ -+ regs->common.reg008_dec_mode = VDPU383_MODE_H264; -+ -+ /* Set input stream length */ -+ regs->h26x_params.reg066_stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ -+ /* Set strides */ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ -+ pixels = dst_fmt->height * dst_fmt->width; -+ -+ regs->h26x_params.reg068_hor_virstride = hor_virstride / 16; -+ regs->h26x_params.reg069_raster_uv_hor_virstride = hor_virstride / 16; -+ regs->h26x_params.reg070_y_virstride = y_virstride / 16; -+ -+ /* Activate block gating */ -+ regs->common.reg010.strmd_auto_gating_e = 1; -+ regs->common.reg010.inter_auto_gating_e = 1; -+ regs->common.reg010.intra_auto_gating_e = 1; -+ regs->common.reg010.transd_auto_gating_e = 1; -+ regs->common.reg010.recon_auto_gating_e = 1; -+ regs->common.reg010.filterd_auto_gating_e = 1; -+ regs->common.reg010.bus_auto_gating_e = 1; -+ regs->common.reg010.ctrl_auto_gating_e = 1; -+ regs->common.reg010.rcb_auto_gating_e = 1; -+ regs->common.reg010.err_prc_auto_gating_e = 1; -+ -+ /* Set timeout threshold */ -+ if (pixels < VDPU383_1080P_PIXELS) -+ regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_1080p; -+ else if (pixels < VDPU383_4K_PIXELS) -+ regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_4K; -+ else if (pixels < VDPU383_8K_PIXELS) -+ regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_8K; -+ else -+ regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_MAX; -+ -+ regs->common.reg016.error_proc_disable = 1; -+ -+ /* Set ref pic address & poc */ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ struct vb2_buffer *vb_buf = run->ref_buf[i]; -+ dma_addr_t buf_dma; -+ -+ /* -+ * If a DPB entry is unused or invalid, address of current destination -+ * buffer is returned. -+ */ -+ if (!vb_buf) -+ vb_buf = &dst_buf->vb2_buf; -+ -+ buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ -+ /* Set reference addresses */ -+ regs->h26x_addr.reg170_185_ref_base[i] = buf_dma; -+ regs->h26x_addr.reg195_210_payload_st_ref_base[i] = buf_dma; -+ -+ /* Set COLMV addresses */ -+ regs->h26x_addr.reg217_232_colmv_ref_base[i] = buf_dma + ctx->colmv_offset; -+ } -+ -+ /* Set rlc base address (input stream) */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ regs->common_addr.reg128_strm_base = rlc_addr; -+ -+ /* Set output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ regs->h26x_addr.reg168_decout_base = dst_addr; -+ regs->h26x_addr.reg169_error_ref_base = dst_addr; -+ regs->h26x_addr.reg192_payload_st_cur_base = dst_addr; -+ -+ /* Set colmv address */ -+ regs->h26x_addr.reg216_colmv_cur_base = dst_addr + ctx->colmv_offset; -+ -+ /* Set RCB addresses */ -+ for (i = 0; i < rkvdec_rcb_buf_count(ctx); i++) { -+ regs->common_addr.reg140_162_rcb_info[i].offset = rkvdec_rcb_buf_dma_addr(ctx, i); -+ regs->common_addr.reg140_162_rcb_info[i].size = rkvdec_rcb_buf_size(ctx, i); -+ } -+ -+ /* Set hw pps address */ -+ offset = offsetof(struct rkvdec_h264_priv_tbl, param_set); -+ regs->common_addr.reg131_gbl_base = priv_start_addr + offset; -+ regs->h26x_params.reg067_global_len = sizeof(struct rkvdec_sps_pps) / 16; -+ -+ /* Set hw rps address */ -+ offset = offsetof(struct rkvdec_h264_priv_tbl, rps); -+ regs->common_addr.reg129_rps_base = priv_start_addr + offset; -+ -+ /* Set cabac table */ -+ offset = offsetof(struct rkvdec_h264_priv_tbl, cabac_table); -+ regs->common_addr.reg130_cabactbl_base = priv_start_addr + offset; -+ -+ /* Set scaling list address */ -+ offset = offsetof(struct rkvdec_h264_priv_tbl, scaling_list); -+ regs->common_addr.reg132_scanlist_addr = priv_start_addr + offset; -+ -+ rkvdec_write_regs(ctx); -+} -+ -+static int rkvdec_h264_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_h264_priv_tbl *priv_tbl; -+ struct rkvdec_h264_ctx *h264_ctx; -+ struct v4l2_ctrl *ctrl; -+ int ret; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_H264_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); -+ if (ret) -+ return ret; -+ -+ h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL); -+ if (!h264_ctx) -+ return -ENOMEM; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &h264_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ h264_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ h264_ctx->priv_tbl.cpu = priv_tbl; -+ memcpy(priv_tbl->cabac_table, rkvdec_h264_cabac_table, -+ sizeof(rkvdec_h264_cabac_table)); -+ -+ ctx->priv = h264_ctx; -+ -+ return 0; -+ -+err_free_ctx: -+ kfree(h264_ctx); -+ return ret; -+} -+ -+static void rkvdec_h264_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, h264_ctx->priv_tbl.size, -+ h264_ctx->priv_tbl.cpu, h264_ctx->priv_tbl.dma); -+ kfree(h264_ctx); -+} -+ -+static int rkvdec_h264_run(struct rkvdec_ctx *ctx) -+{ -+ struct v4l2_h264_reflist_builder reflist_builder; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_h264_ctx *h264_ctx = ctx->priv; -+ struct rkvdec_h264_run run; -+ struct rkvdec_h264_priv_tbl *tbl = h264_ctx->priv_tbl.cpu; -+ u32 watchdog_time; -+ u64 timeout_threshold; -+ unsigned long axi_rate; -+ -+ rkvdec_h264_run_preamble(ctx, &run); -+ -+ /* Build the P/B{0,1} ref lists. */ -+ v4l2_h264_init_reflist_builder(&reflist_builder, run.decode_params, -+ run.sps, run.decode_params->dpb); -+ v4l2_h264_build_p_ref_list(&reflist_builder, h264_ctx->reflists.p); -+ v4l2_h264_build_b_ref_lists(&reflist_builder, h264_ctx->reflists.b0, -+ h264_ctx->reflists.b1); -+ -+ assemble_hw_scaling_list(&run, &tbl->scaling_list); -+ assemble_hw_pps(ctx, &run); -+ lookup_ref_buf_idx(ctx, &run); -+ assemble_hw_rps(&reflist_builder, &run, &h264_ctx->reflists, &tbl->rps); -+ -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ /* Set watchdog at 2 times the hardware timeout threshold */ -+ timeout_threshold = h264_ctx->regs.common.reg013_core_timeout_threshold; -+ axi_rate = clk_get_rate(rkvdec->axi_clk); -+ -+ if (axi_rate) -+ watchdog_time = 2 * (1000 * timeout_threshold) / axi_rate; -+ else -+ watchdog_time = 2000; -+ schedule_delayed_work(&rkvdec->watchdog_work, -+ msecs_to_jiffies(watchdog_time)); -+ -+ /* Start decoding! */ -+ writel(timeout_threshold, rkvdec->link + VDPU383_LINK_TIMEOUT_THRESHOLD); -+ writel(0, rkvdec->link + VDPU383_LINK_IP_ENABLE); -+ writel(VDPU383_DEC_E_BIT, rkvdec->link + VDPU383_LINK_DEC_ENABLE); -+ -+ return 0; -+} -+ -+static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) -+{ -+ if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) -+ return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_h264_fmt_ops = { -+ .adjust_fmt = rkvdec_h264_adjust_fmt, -+ .get_image_fmt = rkvdec_h264_get_image_fmt, -+ .start = rkvdec_h264_start, -+ .stop = rkvdec_h264_stop, -+ .run = rkvdec_h264_run, -+ .try_ctrl = rkvdec_h264_try_ctrl, -+}; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-regs.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-regs.h -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-regs.h -@@ -0,0 +1,284 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Rockchip Video Decoder VDPU383 driver registers description -+ * -+ * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#ifndef _RKVDEC_VDPU838_REGS_H_ -+#define _RKVDEC_VDPU838_REGS_H_ -+ -+#include -+ -+#define VDPU383_OFFSET_COMMON_REGS (8 * sizeof(u32)) -+#define VDPU383_OFFSET_CODEC_PARAMS_REGS (64 * sizeof(u32)) -+#define VDPU383_OFFSET_COMMON_ADDR_REGS (128 * sizeof(u32)) -+#define VDPU383_OFFSET_CODEC_ADDR_REGS (168 * sizeof(u32)) -+#define VDPU383_OFFSET_POC_HIGHBIT_REGS (200 * sizeof(u32)) -+ -+#define VDPU383_MODE_HEVC 0 -+#define VDPU383_MODE_H264 1 -+ -+#define VDPU383_1080P_PIXELS (1920 * 1080) -+#define VDPU383_4K_PIXELS (4096 * 2304) -+#define VDPU383_8K_PIXELS (7680 * 4320) -+#define VDPU383_TIMEOUT_1080p (0xffffff) -+#define VDPU383_TIMEOUT_4K (0x2cfffff) -+#define VDPU383_TIMEOUT_8K (0x4ffffff) -+#define VDPU383_TIMEOUT_MAX (0xffffffff) -+ -+#define VDPU383_LINK_TIMEOUT_THRESHOLD 0x54 -+ -+#define VDPU383_LINK_IP_ENABLE 0x58 -+#define VDPU383_IP_CRU_MODE BIT(24) -+ -+#define VDPU383_LINK_DEC_ENABLE 0x40 -+#define VDPU383_DEC_E_BIT BIT(0) -+ -+#define VDPU383_LINK_INT_EN 0x048 -+#define VDPU383_INT_EN_IRQ BIT(0) -+#define VDPU383_INT_EN_LINE_IRQ BIT(1) -+ -+#define VDPU383_LINK_STA_INT 0x04c -+#define VDPU383_STA_INT_DEC_RDY_STA BIT(0) -+#define VDPU383_STA_INT_SOFTRESET_RDY (BIT(10) | BIT(11)) -+#define VDPU383_STA_INT_ALL 0x3ff -+ -+struct vdpu383_regs_common { -+ u32 reg008_dec_mode; -+ -+ struct swreg9_important_en { -+ u32 fbc_e : 1; -+ u32 tile_e : 1; -+ u32 reserve0 : 2; -+ u32 buf_empty_en : 1; -+ u32 scale_down_en : 1; -+ u32 reserve1 : 1; -+ u32 pix_range_det_e : 1; -+ u32 av1_fgs_en : 1; -+ u32 reserve2 : 7; -+ u32 line_irq_en : 1; -+ u32 out_cbcr_swap : 1; -+ u32 fbc_force_uncompress : 1; -+ u32 fbc_sparse_mode : 1; -+ u32 reserve3 : 12; -+ } reg009; -+ -+ struct swreg010_block_gating_en { -+ u32 strmd_auto_gating_e : 1; -+ u32 inter_auto_gating_e : 1; -+ u32 intra_auto_gating_e : 1; -+ u32 transd_auto_gating_e : 1; -+ u32 recon_auto_gating_e : 1; -+ u32 filterd_auto_gating_e : 1; -+ u32 bus_auto_gating_e : 1; -+ u32 ctrl_auto_gating_e : 1; -+ u32 rcb_auto_gating_e : 1; -+ u32 err_prc_auto_gating_e : 1; -+ u32 reserve0 : 22; -+ } reg010; -+ -+ struct swreg011_cfg_para { -+ u32 reserve0 : 9; -+ u32 dec_timeout_dis : 1; -+ u32 reserve1 : 22; -+ } reg011; -+ -+ struct swreg012_cache_hash_mask { -+ u32 reserve0 : 7; -+ u32 cache_hash_mask : 25; -+ } reg012; -+ -+ u32 reg013_core_timeout_threshold; -+ -+ struct swreg014_line_irq_ctrl { -+ u32 dec_line_irq_step : 16; -+ u32 dec_line_offset_y_st : 16; -+ } reg014; -+ -+ struct swreg015_irq_sta { -+ u32 rkvdec_frame_rdy_sta : 1; -+ u32 rkvdec_strm_error_sta : 1; -+ u32 rkvdec_core_timeout_sta : 1; -+ u32 rkvdec_ip_timeout_sta : 1; -+ u32 rkvdec_bus_error_sta : 1; -+ u32 rkvdec_buffer_empty_sta : 1; -+ u32 rkvdec_colmv_ref_error_sta : 1; -+ u32 rkvdec_error_spread_sta : 1; -+ u32 create_core_timeout_sta : 1; -+ u32 wlast_miss_match_sta : 1; -+ u32 rkvdec_core_rst_rdy_sta : 1; -+ u32 rkvdec_ip_rst_rdy_sta : 1; -+ u32 force_busidle_rdy_sta : 1; -+ u32 ltb_pause_rdy_sta : 1; -+ u32 ltb_end_flag : 1; -+ u32 unsupport_decmode_error_sta : 1; -+ u32 wmask_bits : 15; -+ u32 reserve0 : 1; -+ } reg015; -+ -+ struct swreg016_error_ctrl_set { -+ u32 error_proc_disable : 1; -+ u32 reserve0 : 7; -+ u32 error_spread_disable : 1; -+ u32 reserve1 : 15; -+ u32 roi_error_ctu_cal_en : 1; -+ u32 reserve2 : 7; -+ } reg016; -+ -+ struct swreg017_err_roi_ctu_offset_start { -+ u32 roi_x_ctu_offset_st : 12; -+ u32 reserve0 : 4; -+ u32 roi_y_ctu_offset_st : 12; -+ u32 reserve1 : 4; -+ } reg017; -+ -+ struct swreg018_err_roi_ctu_offset_end { -+ u32 roi_x_ctu_offset_end : 12; -+ u32 reserve0 : 4; -+ u32 roi_y_ctu_offset_end : 12; -+ u32 reserve1 : 4; -+ } reg018; -+ -+ struct swreg019_error_ref_info { -+ u32 avs2_ref_error_field : 1; -+ u32 avs2_ref_error_topfield : 1; -+ u32 ref_error_topfield_used : 1; -+ u32 ref_error_botfield_used : 1; -+ u32 reserve0 : 28; -+ } reg019; -+ -+ u32 reg020_cabac_error_en_lowbits; -+ u32 reg021_cabac_error_en_highbits; -+ -+ u32 reg022_reserved; -+ -+ struct swreg023_invalid_pixel_fill { -+ u32 fill_y : 10; -+ u32 fill_u : 10; -+ u32 fill_v : 10; -+ u32 reserve0 : 2; -+ } reg023; -+ -+ u32 reg024_026_reserved[3]; -+ -+ struct swreg027_align_en { -+ u32 reserve0 : 4; -+ u32 ctu_align_wr_en : 1; -+ u32 reserve1 : 27; -+ } reg027; -+ -+ struct swreg028_debug_perf_latency_ctrl0 { -+ u32 axi_perf_work_e : 1; -+ u32 reserve0 : 2; -+ u32 axi_cnt_type : 1; -+ u32 rd_latency_id : 8; -+ u32 reserve1 : 4; -+ u32 rd_latency_thr : 12; -+ u32 reserve2 : 4; -+ } reg028; -+ -+ struct swreg029_debug_perf_latency_ctrl1 { -+ u32 addr_align_type : 2; -+ u32 ar_cnt_id_type : 1; -+ u32 aw_cnt_id_type : 1; -+ u32 ar_count_id : 8; -+ u32 reserve0 : 4; -+ u32 aw_count_id : 8; -+ u32 rd_band_width_mode : 1; -+ u32 reserve1 : 7; -+ } reg029; -+ -+ struct swreg030_qos_ctrl { -+ u32 axi_wr_qos_level : 4; -+ u32 reserve0 : 4; -+ u32 axi_wr_qos : 4; -+ u32 reserve1 : 4; -+ u32 axi_rd_qos_level : 4; -+ u32 reserve2 : 4; -+ u32 axi_rd_qos : 4; -+ u32 reserve3 : 4; -+ } reg030; -+}; -+ -+struct vdpu383_regs_common_addr { -+ u32 reg128_strm_base; -+ u32 reg129_rps_base; -+ u32 reg130_cabactbl_base; -+ u32 reg131_gbl_base; -+ u32 reg132_scanlist_addr; -+ u32 reg133_scale_down_base; -+ u32 reg134_fgs_base; -+ u32 reg135_139_reserved[5]; -+ -+ struct rcb_info { -+ u32 offset; -+ u32 size; -+ } reg140_162_rcb_info[11]; -+}; -+ -+struct vdpu383_regs_h26x_addr { -+ u32 reg168_decout_base; -+ u32 reg169_error_ref_base; -+ u32 reg170_185_ref_base[16]; -+ u32 reg186_191_reserved[6]; -+ u32 reg192_payload_st_cur_base; -+ u32 reg193_fbc_payload_offset; -+ u32 reg194_payload_st_error_ref_base; -+ u32 reg195_210_payload_st_ref_base[16]; -+ u32 reg211_215_reserved[5]; -+ u32 reg216_colmv_cur_base; -+ u32 reg217_232_colmv_ref_base[16]; -+}; -+ -+struct vdpu383_regs_h26x_params { -+ u32 reg064_start_decoder; -+ u32 reg065_strm_start_bit; -+ u32 reg066_stream_len; -+ u32 reg067_global_len; -+ u32 reg068_hor_virstride; -+ u32 reg069_raster_uv_hor_virstride; -+ u32 reg070_y_virstride; -+ u32 reg071_scl_ref_hor_virstride; -+ u32 reg072_scl_ref_raster_uv_hor_virstride; -+ u32 reg073_scl_ref_virstride; -+ u32 reg074_fgs_ref_hor_virstride; -+ u32 reg075_079_reserved[5]; -+ u32 reg080_error_ref_hor_virstride; -+ u32 reg081_error_ref_raster_uv_hor_virstride; -+ u32 reg082_error_ref_virstride; -+ u32 reg083_ref0_hor_virstride; -+ u32 reg084_ref0_raster_uv_hor_virstride; -+ u32 reg085_ref0_virstride; -+ u32 reg086_ref1_hor_virstride; -+ u32 reg087_ref1_raster_uv_hor_virstride; -+ u32 reg088_ref1_virstride; -+ u32 reg089_ref2_hor_virstride; -+ u32 reg090_ref2_raster_uv_hor_virstride; -+ u32 reg091_ref2_virstride; -+ u32 reg092_ref3_hor_virstride; -+ u32 reg093_ref3_raster_uv_hor_virstride; -+ u32 reg094_ref3_virstride; -+ u32 reg095_ref4_hor_virstride; -+ u32 reg096_ref4_raster_uv_hor_virstride; -+ u32 reg097_ref4_virstride; -+ u32 reg098_ref5_hor_virstride; -+ u32 reg099_ref5_raster_uv_hor_virstride; -+ u32 reg100_ref5_virstride; -+ u32 reg101_ref6_hor_virstride; -+ u32 reg102_ref6_raster_uv_hor_virstride; -+ u32 reg103_ref6_virstride; -+ u32 reg104_ref7_hor_virstride; -+ u32 reg105_ref7_raster_uv_hor_virstride; -+ u32 reg106_ref7_virstride; -+}; -+ -+struct vdpu383_regs_h26x { -+ struct vdpu383_regs_common common; /* 8-30 */ -+ struct vdpu383_regs_h26x_params h26x_params; /* 64-74, 80-106 */ -+ struct vdpu383_regs_common_addr common_addr; /* 128-134, 140-161 */ -+ struct vdpu383_regs_h26x_addr h26x_addr; /* 168-185, 192-210, 216-232 */ -+} __packed; -+ -+#endif /* __RKVDEC_VDPU838_REGS_H__ */ -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -9,6 +9,7 @@ - * Copyright (C) 2011 Samsung Electronics Co., Ltd. - */ - -+#include - #include - #include - #include -@@ -30,6 +31,7 @@ - #include "rkvdec.h" - #include "rkvdec-regs.h" - #include "rkvdec-vdpu381-regs.h" -+#include "rkvdec-vdpu383-regs.h" - #include "rkvdec-rcb.h" - - static bool rkvdec_image_fmt_match(enum rkvdec_image_fmt fmt1, -@@ -121,6 +123,16 @@ static int vdpu38x_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pix_mp, u32 pix - return 0; - } - -+static u32 rkvdec_colmv_size(u16 width, u16 height) -+{ -+ return 128 * DIV_ROUND_UP(width, 16) * DIV_ROUND_UP(height, 16); -+} -+ -+static u32 rkvdec_vdpu383_colmv_size(u16 width, u16 height) -+{ -+ return ALIGN(width, 64) * ALIGN(height, 16); -+} -+ - static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - struct v4l2_pix_format_mplane *pix_mp) - { -@@ -130,9 +142,7 @@ static void rkvdec_fill_decoded_pixfmt(struct rkvdec_ctx *ctx, - - ctx->colmv_offset = pix_mp->plane_fmt[0].sizeimage; - -- pix_mp->plane_fmt[0].sizeimage += 128 * -- DIV_ROUND_UP(pix_mp->width, 16) * -- DIV_ROUND_UP(pix_mp->height, 16); -+ pix_mp->plane_fmt[0].sizeimage += cfg->colmv_size(pix_mp->width, pix_mp->height); - } - - static void rkvdec_reset_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f, -@@ -251,17 +261,6 @@ static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), - }; - --static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = { -- { -- .fourcc = V4L2_PIX_FMT_NV12, -- .image_fmt = RKVDEC_IMG_FMT_420_8BIT, -- }, -- { -- .fourcc = V4L2_PIX_FMT_NV15, -- .image_fmt = RKVDEC_IMG_FMT_420_10BIT, -- }, --}; -- - static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { - { - .cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, -@@ -309,6 +308,60 @@ static const struct rkvdec_ctrls rkvdec_h264_ctrls = { - .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs), - }; - -+static const struct rkvdec_ctrl_desc vdpu38x_hevc_ctrl_descs[] = { -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, -+ .cfg.ops = &rkvdec_ctrl_ops, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, -+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, -+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, -+ .cfg.menu_skip_mask = -+ BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE), -+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, -+ }, -+ { -+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, -+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, -+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_EXT_SPS_ST_RPS, -+ .cfg.dims = { 65 }, -+ }, -+ { -+ .cfg.id = V4L2_CID_STATELESS_HEVC_EXT_SPS_LT_RPS, -+ .cfg.dims = { 65 }, -+ }, -+}; -+ -+static const struct rkvdec_ctrls vdpu38x_hevc_ctrls = { -+ .ctrls = vdpu38x_hevc_ctrl_descs, -+ .num_ctrls = ARRAY_SIZE(vdpu38x_hevc_ctrl_descs), -+}; -+ - static const struct rkvdec_decoded_fmt_desc rkvdec_h264_decoded_fmts[] = { - { - .fourcc = V4L2_PIX_FMT_NV12, -@@ -328,6 +381,17 @@ static const struct rkvdec_decoded_fmt_desc rkvdec_h264_decoded_fmts[] = { - }, - }; - -+static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_NV12, -+ .image_fmt = RKVDEC_IMG_FMT_420_8BIT, -+ }, -+ { -+ .fourcc = V4L2_PIX_FMT_NV15, -+ .image_fmt = RKVDEC_IMG_FMT_420_10BIT, -+ }, -+}; -+ - static const struct rkvdec_ctrl_desc rkvdec_vp9_ctrl_descs[] = { - { - .cfg.id = V4L2_CID_STATELESS_VP9_FRAME, -@@ -425,6 +489,43 @@ static const struct rkvdec_coded_fmt_desc vdpu381_coded_fmts[] = { - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, - .capability = RKVDEC_CAPABILITY_H264, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 16, -+ .max_width = 65472, -+ .step_width = 16, -+ .min_height = 16, -+ .max_height = 65472, -+ .step_height = 16, -+ }, -+ .ctrls = &vdpu38x_hevc_ctrls, -+ .ops = &rkvdec_vdpu381_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ .capability = RKVDEC_CAPABILITY_HEVC, -+ }, -+}; -+ -+static const struct rkvdec_coded_fmt_desc vdpu383_coded_fmts[] = { -+ { -+ .fourcc = V4L2_PIX_FMT_H264_SLICE, -+ .frmsize = { -+ .min_width = 64, -+ .max_width = 65520, -+ .step_width = 64, -+ .min_height = 16, -+ .max_height = 65520, -+ .step_height = 16, -+ }, -+ .ctrls = &rkvdec_h264_ctrls, -+ .ops = &rkvdec_vdpu383_h264_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), -+ .decoded_fmts = rkvdec_h264_decoded_fmts, -+ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ .capability = RKVDEC_CAPABILITY_H264, -+ }, - }; - - static bool rkvdec_is_capable(struct rkvdec_ctx *ctx, unsigned int capability) -@@ -1319,6 +1420,35 @@ static irqreturn_t vdpu381_irq_handler(struct rkvdec_ctx *ctx) - return IRQ_HANDLED; - } - -+static irqreturn_t vdpu383_irq_handler(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ enum vb2_buffer_state state; -+ bool need_reset = 0; -+ u32 status; -+ -+ status = readl(rkvdec->link + VDPU383_LINK_STA_INT); -+ writel(FIELD_PREP_WM16(VDPU383_STA_INT_ALL, 0), rkvdec->link + VDPU383_LINK_STA_INT); -+ /* On vdpu383, the interrupts must be disabled */ -+ writel(FIELD_PREP_WM16(VDPU383_INT_EN_IRQ | VDPU383_INT_EN_LINE_IRQ, 0), -+ rkvdec->link + VDPU383_LINK_INT_EN); -+ -+ if (status & VDPU383_STA_INT_DEC_RDY_STA) { -+ state = VB2_BUF_STATE_DONE; -+ } else { -+ state = VB2_BUF_STATE_ERROR; -+ rkvdec_iommu_restore(rkvdec); -+ } -+ -+ if (need_reset) -+ rkvdec_iommu_restore(rkvdec); -+ -+ if (cancel_delayed_work(&rkvdec->watchdog_work)) -+ rkvdec_job_finish(ctx, state); -+ -+ return IRQ_HANDLED; -+} -+ - static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - { - struct rkvdec_dev *rkvdec = priv; -@@ -1391,6 +1521,7 @@ static const struct rkvdec_config config_rkvdec = { - .coded_fmts_num = ARRAY_SIZE(rkvdec_coded_fmts), - .irq_handler = rk3399_irq_handler, - .fill_pixfmt_mp = v4l2_fill_pixfmt_mp, -+ .colmv_size = rkvdec_colmv_size, - }; - - static struct rcb_size_info vdpu381_rcb_sizes[] = { -@@ -1413,6 +1544,33 @@ static const struct rkvdec_config config_vdpu381 = { - .rcb_num = ARRAY_SIZE(vdpu381_rcb_sizes), - .irq_handler = vdpu381_irq_handler, - .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, -+ .colmv_size = rkvdec_colmv_size, -+ .named_regs = true, -+}; -+ -+static struct rcb_size_info vdpu383_rcb_sizes[] = { -+ {6, PIC_WIDTH}, // streamd -+ {6, PIC_WIDTH}, // streamd_tile -+ {12, PIC_WIDTH}, // inter -+ {12, PIC_WIDTH}, // inter_tile -+ {16, PIC_WIDTH}, // intra -+ {10, PIC_WIDTH}, // intra_tile -+ {120, PIC_WIDTH}, // filterd -+ {120, PIC_WIDTH}, // filterd_protect -+ {120, PIC_WIDTH}, // filterd_tile_row -+ {180, PIC_HEIGHT}, // filterd_tile_col -+}; -+ -+const struct rkvdec_config config_vdpu383 = { -+ .coded_fmts = (struct rkvdec_coded_fmt_desc *)vdpu383_coded_fmts, -+ .coded_fmts_num = ARRAY_SIZE(vdpu383_coded_fmts), -+ .rcb_size_info = vdpu383_rcb_sizes, -+ .rcb_num = ARRAY_SIZE(vdpu383_rcb_sizes), -+ .irq_handler = vdpu383_irq_handler, -+ .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, -+ .colmv_size = rkvdec_vdpu383_colmv_size, -+ .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, -+ .named_regs = true, - }; - - static const struct rkvdec_variant rk3288_rkvdec_variant = { -@@ -1437,6 +1595,12 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { - - static const struct rkvdec_variant rk3588_vdpu381_variant = { - .config = &config_vdpu381, -+ .capabilities = RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_HEVC, -+}; -+ -+static const struct rkvdec_variant rk3576_vdpu383_variant = { -+ .config = &config_vdpu383, - .capabilities = RKVDEC_CAPABILITY_H264, - }; - -@@ -1457,6 +1621,10 @@ static const struct of_device_id of_rkvdec_match[] = { - .compatible = "rockchip,rk3588-vdec", - .data = &rk3588_vdpu381_variant, - }, -+ { -+ .compatible = "rockchip,rk3576-vdec", -+ .data = &rk3576_vdpu383_variant -+ }, - { /* sentinel */ } - }; - MODULE_DEVICE_TABLE(of, of_rkvdec_match); -@@ -1494,9 +1662,19 @@ static int rkvdec_probe(struct platform_device *pdev) - rkvdec->clk_count = ret; - rkvdec->axi_clk = devm_clk_get(&pdev->dev, "axi"); - -- rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); -- if (IS_ERR(rkvdec->regs)) -- return PTR_ERR(rkvdec->regs); -+ if (rkvdec->config->named_regs) { -+ rkvdec->regs = devm_platform_ioremap_resource_byname(pdev, "function"); -+ if (IS_ERR(rkvdec->regs)) -+ return PTR_ERR(rkvdec->regs); -+ -+ rkvdec->link = devm_platform_ioremap_resource_byname(pdev, "link"); -+ if (IS_ERR(rkvdec->link)) -+ return PTR_ERR(rkvdec->link); -+ } else { -+ rkvdec->regs = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(rkvdec->regs)) -+ return PTR_ERR(rkvdec->regs); -+ } - - ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); - if (ret) { -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -123,6 +123,8 @@ struct rkvdec_config { - irqreturn_t (*irq_handler)(struct rkvdec_ctx *ctx); - int (*fill_pixfmt_mp)(struct v4l2_pix_format_mplane *pix_mp, u32 pixelformat, - u32 width, u32 height); -+ u32 (*colmv_size)(u16 width, u16 height); -+ bool named_regs; - }; - - struct rkvdec_dev { -@@ -135,6 +137,7 @@ struct rkvdec_dev { - unsigned int clk_count; - struct clk *axi_clk; - void __iomem *regs; -+ void __iomem *link; - struct mutex vdev_lock; /* serializes ioctls */ - struct delayed_work watchdog_work; - struct gen_pool *sram_pool; -@@ -179,10 +182,16 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); - void rkvdec_memcpy_toio(void __iomem *dst, void *src, size_t len); - -+/* RKVDEC ops */ - extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; - extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; - -+/* VDPU381 ops */ - extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_hevc_fmt_ops; -+ -+/* VDPU383 ops */ -+extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_h264_fmt_ops; - - #endif /* RKVDEC_H_ */ --- -Armbian - -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Detlev Casanova -Date: Wed, 11 Jun 2025 17:04:28 -0400 -Subject: media: rkvdec: Add HEVC support for the VDPU383 variant - -The VDPU383 decoder is used on the RK3576 SoC and has support for HEVC. - -This patch also moves some functions to a common rkvdec-hevc-common.c -file and adds a specific scaling matrix flatten function. - -The fluster score for JCT-VC-HEVC_V1 is 146/147. - -Signed-off-by: Detlev Casanova ---- - drivers/media/platform/rockchip/rkvdec/Makefile | 1 + - drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c | 49 +- - drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c | 680 ++++++++++ - drivers/media/platform/rockchip/rkvdec/rkvdec.c | 94 +- - drivers/media/platform/rockchip/rkvdec/rkvdec.h | 2 + - 5 files changed, 783 insertions(+), 43 deletions(-) - -diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/Makefile -+++ b/drivers/media/platform/rockchip/rkvdec/Makefile -@@ -11,4 +11,5 @@ rockchip-vdec-y += \ - rkvdec-vdpu381-h264.o \ - rkvdec-vdpu381-hevc.o \ - rkvdec-vdpu383-h264.o \ -+ rkvdec-vdpu383-hevc.o \ - rkvdec-vp9.o -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c -@@ -155,60 +155,25 @@ static void set_ref_poc(struct rkvdec_rps_short_term_ref_set *set, int poc, int - } - } - --/* -- * Flip one or more matrices along their main diagonal and flatten them -- * before writing it to the memory. -- * Convert: -- * ABCD AEIM -- * EFGH => BFJN => AEIMBFJNCGKODHLP -- * IJKL CGKO -- * MNOP DHLP -- */ --static void transpose_and_flatten_matrices(u8 *output, const u8 *input, -- int matrices, int row_length) --{ -- int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value; -- -- matrix_size = row_length * row_length; -- for (i = 0; i < matrices; i++) { -- row = 0; -- x_offset = 0; -- matrix_offset = i * matrix_size; -- for (j = 0; j < matrix_size; j++) { -- y_offset = j - (row * row_length); -- rot_index = y_offset * row_length + x_offset; -- new_value = *(input + i * matrix_size + j); -- output[matrix_offset + rot_index] = new_value; -- if ((j + 1) % row_length == 0) { -- row += 1; -- x_offset += 1; -- } -- } -- } --} -- - static void assemble_scalingfactor0(struct rkvdec_dev *rkvdec, u8 *output, - const struct v4l2_ctrl_hevc_scaling_matrix *input) - { -+ const struct rkvdec_config *cfg = rkvdec->config; - int offset = 0; - -- transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); -+ cfg->flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); - offset = 6 * 16 * sizeof(u8); -- transpose_and_flatten_matrices(output + offset, -- (const u8 *)input->scaling_list_8x8, 6, 8); -+ cfg->flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); - offset += 6 * 64 * sizeof(u8); -- transpose_and_flatten_matrices(output + offset, -- (const u8 *)input->scaling_list_16x16, 6, 8); -+ cfg->flatten_matrices(output + offset, (const u8 *)input->scaling_list_16x16, 6, 8); - offset += 6 * 64 * sizeof(u8); - /* Add a 128 byte padding with 0s between the two 32x32 matrices */ -- transpose_and_flatten_matrices(output + offset, -- (const u8 *)input->scaling_list_32x32, 1, 8); -+ cfg->flatten_matrices(output + offset, (const u8 *)input->scaling_list_32x32, 1, 8); - offset += 64 * sizeof(u8); - memset(output + offset, 0, 128); - offset += 128 * sizeof(u8); -- transpose_and_flatten_matrices(output + offset, -- (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), -- 1, 8); -+ cfg->flatten_matrices(output + offset, -+ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), 1, 8); - offset += 64 * sizeof(u8); - memset(output + offset, 0, 128); - } -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c -new file mode 100644 -index 000000000000..111111111111 ---- /dev/null -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c -@@ -0,0 +1,680 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/* -+ * Rockchip VDPU383 HEVC backend -+ * -+ * Copyright (C) 2025 Collabora, Ltd. -+ * Detlev Casanova -+ */ -+ -+#include -+ -+#include "rkvdec.h" -+#include "rkvdec-rcb.h" -+#include "rkvdec-hevc-common.h" -+#include "rkvdec-vdpu383-regs.h" -+ -+struct rkvdec_hevc_sps_pps { -+ // SPS -+ u16 video_parameters_set_id : 4; -+ u16 seq_parameters_set_id_sps : 4; -+ u16 chroma_format_idc : 2; -+ u16 width : 16; -+ u16 height : 16; -+ u16 bit_depth_luma : 3; -+ u16 bit_depth_chroma : 3; -+ u16 max_pic_order_count_lsb : 5; -+ u16 diff_max_min_luma_coding_block_size : 2; -+ u16 min_luma_coding_block_size : 3; -+ u16 min_transform_block_size : 3; -+ u16 diff_max_min_transform_block_size : 2; -+ u16 max_transform_hierarchy_depth_inter : 3; -+ u16 max_transform_hierarchy_depth_intra : 3; -+ u16 scaling_list_enabled_flag : 1; -+ u16 amp_enabled_flag : 1; -+ u16 sample_adaptive_offset_enabled_flag : 1; -+ u16 pcm_enabled_flag : 1; -+ u16 pcm_sample_bit_depth_luma : 4; -+ u16 pcm_sample_bit_depth_chroma : 4; -+ u16 pcm_loop_filter_disabled_flag : 1; -+ u16 diff_max_min_pcm_luma_coding_block_size : 3; -+ u16 min_pcm_luma_coding_block_size : 3; -+ u16 num_short_term_ref_pic_sets : 7; -+ u16 long_term_ref_pics_present_flag : 1; -+ u16 num_long_term_ref_pics_sps : 6; -+ u16 sps_temporal_mvp_enabled_flag : 1; -+ u16 strong_intra_smoothing_enabled_flag : 1; -+ u16 reserved0 : 7; -+ u16 sps_max_dec_pic_buffering_minus1 : 4; -+ u16 separate_colour_plane_flag : 1; -+ u16 high_precision_offsets_enabled_flag : 1; -+ u16 persistent_rice_adaptation_enabled_flag : 1; -+ -+ // PPS -+ u16 picture_parameters_set_id : 6; -+ u16 seq_parameters_set_id_pps : 4; -+ u16 dependent_slice_segments_enabled_flag : 1; -+ u16 output_flag_present_flag : 1; -+ u16 num_extra_slice_header_bits : 13; -+ u16 sign_data_hiding_enabled_flag : 1; -+ u16 cabac_init_present_flag : 1; -+ u16 num_ref_idx_l0_default_active : 4; -+ u16 num_ref_idx_l1_default_active : 4; -+ u16 init_qp_minus26 : 7; -+ u16 constrained_intra_pred_flag : 1; -+ u16 transform_skip_enabled_flag : 1; -+ u16 cu_qp_delta_enabled_flag : 1; -+ u16 log2_min_cb_size : 3; -+ u16 pps_cb_qp_offset : 5; -+ u16 pps_cr_qp_offset : 5; -+ u16 pps_slice_chroma_qp_offsets_present_flag : 1; -+ u16 weighted_pred_flag : 1; -+ u16 weighted_bipred_flag : 1; -+ u16 transquant_bypass_enabled_flag : 1; -+ u16 tiles_enabled_flag : 1; -+ u16 entropy_coding_sync_enabled_flag : 1; -+ u16 pps_loop_filter_across_slices_enabled_flag : 1; -+ u16 loop_filter_across_tiles_enabled_flag : 1; -+ u16 deblocking_filter_override_enabled_flag : 1; -+ u16 pps_deblocking_filter_disabled_flag : 1; -+ u16 pps_beta_offset_div2 : 4; -+ u16 pps_tc_offset_div2 : 4; -+ u16 lists_modification_present_flag : 1; -+ u16 log2_parallel_merge_level : 3; -+ u16 slice_segment_header_extension_present_flag : 1; -+ u16 reserved1 : 3; -+ -+ // pps extensions -+ u16 log2_max_transform_skip_block_size : 2; -+ u16 cross_component_prediction_enabled_flag : 1; -+ u16 chroma_qp_offset_list_enabled_flag : 1; -+ u16 log2_min_cu_chroma_qp_delta_size : 3; -+ u16 cb_qp_offset_list0 : 5; -+ u16 cb_qp_offset_list1 : 5; -+ u16 cb_qp_offset_list2 : 5; -+ u16 cb_qp_offset_list3 : 5; -+ u16 cb_qp_offset_list4 : 5; -+ u16 cb_qp_offset_list5 : 5; -+ u16 cb_cr_offset_list0 : 5; -+ u16 cb_cr_offset_list1 : 5; -+ u16 cb_cr_offset_list2 : 5; -+ u16 cb_cr_offset_list3 : 5; -+ u16 cb_cr_offset_list4 : 5; -+ u16 cb_cr_offset_list5 : 5; -+ u16 chroma_qp_offset_list_len_minus1 : 3; -+ -+ /* mvc0 && mvc1 */ -+ u16 mvc_ff : 16; -+ u16 mvc_00 : 9; -+ -+ /* poc info */ -+ u16 reserved2 : 3; -+ u32 current_poc : 32; -+ u32 ref_pic_poc0 : 32; -+ u32 ref_pic_poc1 : 32; -+ u32 ref_pic_poc2 : 32; -+ u32 ref_pic_poc3 : 32; -+ u32 ref_pic_poc4 : 32; -+ u32 ref_pic_poc5 : 32; -+ u32 ref_pic_poc6 : 32; -+ u32 ref_pic_poc7 : 32; -+ u32 ref_pic_poc8 : 32; -+ u32 ref_pic_poc9 : 32; -+ u32 ref_pic_poc10 : 32; -+ u32 ref_pic_poc11 : 32; -+ u32 ref_pic_poc12 : 32; -+ u32 ref_pic_poc13 : 32; -+ u32 ref_pic_poc14 : 32; -+ u32 reserved3 : 32; -+ u32 ref_is_valid : 15; -+ u32 reserved4 : 1; -+ -+ /* tile info*/ -+ u16 num_tile_columns : 5; -+ u16 num_tile_rows : 5; -+ u32 column_width0 : 24; -+ u32 column_width1 : 24; -+ u32 column_width2 : 24; -+ u32 column_width3 : 24; -+ u32 column_width4 : 24; -+ u32 column_width5 : 24; -+ u32 column_width6 : 24; -+ u32 column_width7 : 24; -+ u32 column_width8 : 24; -+ u32 column_width9 : 24; -+ u32 row_height0 : 24; -+ u32 row_height1 : 24; -+ u32 row_height2 : 24; -+ u32 row_height3 : 24; -+ u32 row_height4 : 24; -+ u32 row_height5 : 24; -+ u32 row_height6 : 24; -+ u32 row_height7 : 24; -+ u32 row_height8 : 24; -+ u32 row_height9 : 24; -+ u32 row_height10 : 24; -+ u32 reserved5 : 2; -+ u32 padding; -+} __packed; -+ -+struct rkvdec_hevc_priv_tbl { -+ struct rkvdec_hevc_sps_pps param_set; -+ struct rkvdec_rps rps; -+ struct scaling_factor scaling_list; -+ u8 cabac_table[27456]; -+} __packed; -+ -+struct rkvdec_hevc_ctx { -+ struct rkvdec_aux_buf priv_tbl; -+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; -+ struct v4l2_ctrl_hevc_ext_sps_st_rps st_cache; -+ struct vdpu383_regs_h26x regs; -+}; -+ -+static void set_column_row(struct rkvdec_hevc_sps_pps *hw_ps, u16 column, u16 row, int i) -+{ -+ int shift = (i & 1) ? 12 : 0; -+ -+ switch (i / 2) { -+ case 0: -+ hw_ps->column_width0 |= column << shift; -+ hw_ps->row_height0 |= row << shift; -+ break; -+ case 1: -+ hw_ps->column_width1 |= column << shift; -+ hw_ps->row_height1 |= row << shift; -+ break; -+ case 2: -+ hw_ps->column_width2 |= column << shift; -+ hw_ps->row_height2 |= row << shift; -+ break; -+ case 3: -+ hw_ps->column_width3 |= column << shift; -+ hw_ps->row_height3 |= row << shift; -+ break; -+ case 4: -+ hw_ps->column_width4 |= column << shift; -+ hw_ps->row_height4 |= row << shift; -+ break; -+ case 5: -+ hw_ps->column_width5 |= column << shift; -+ hw_ps->row_height5 |= row << shift; -+ break; -+ case 6: -+ hw_ps->column_width6 |= column << shift; -+ hw_ps->row_height6 |= row << shift; -+ break; -+ case 7: -+ hw_ps->column_width7 |= column << shift; -+ hw_ps->row_height7 |= row << shift; -+ break; -+ case 8: -+ hw_ps->column_width8 |= column << shift; -+ hw_ps->row_height8 |= row << shift; -+ break; -+ case 9: -+ hw_ps->column_width9 |= column << shift; -+ hw_ps->row_height9 |= row << shift; -+ break; -+ case 10: -+ hw_ps->row_height10 |= row << shift; -+ break; -+ } -+} -+ -+static void set_pps_ref_pic_poc(struct rkvdec_hevc_sps_pps *hw_ps, u32 poc, int i) -+{ -+ switch (i) { -+ case 0: -+ hw_ps->ref_pic_poc0 = poc; -+ break; -+ case 1: -+ hw_ps->ref_pic_poc1 = poc; -+ break; -+ case 2: -+ hw_ps->ref_pic_poc2 = poc; -+ break; -+ case 3: -+ hw_ps->ref_pic_poc3 = poc; -+ break; -+ case 4: -+ hw_ps->ref_pic_poc4 = poc; -+ break; -+ case 5: -+ hw_ps->ref_pic_poc5 = poc; -+ break; -+ case 6: -+ hw_ps->ref_pic_poc6 = poc; -+ break; -+ case 7: -+ hw_ps->ref_pic_poc7 = poc; -+ break; -+ case 8: -+ hw_ps->ref_pic_poc8 = poc; -+ break; -+ case 9: -+ hw_ps->ref_pic_poc9 = poc; -+ break; -+ case 10: -+ hw_ps->ref_pic_poc10 = poc; -+ break; -+ case 11: -+ hw_ps->ref_pic_poc11 = poc; -+ break; -+ case 12: -+ hw_ps->ref_pic_poc12 = poc; -+ break; -+ case 13: -+ hw_ps->ref_pic_poc13 = poc; -+ break; -+ case 14: -+ hw_ps->ref_pic_poc14 = poc; -+ break; -+ } -+} -+ -+static void assemble_hw_pps(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ struct rkvdec_hevc_ctx *h264_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ const struct v4l2_ctrl_hevc_pps *pps = run->pps; -+ const struct v4l2_ctrl_hevc_decode_params *dec_params = run->decode_params; -+ struct rkvdec_hevc_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu; -+ struct rkvdec_hevc_sps_pps *hw_ps; -+ bool tiles_enabled; -+ s32 max_cu_width; -+ s32 pic_in_cts_width; -+ s32 pic_in_cts_height; -+ u16 log2_min_cb_size, width, height; -+ u16 column_width[22]; -+ u16 row_height[22]; -+ u8 pcm_enabled; -+ u32 i; -+ -+ /* -+ * HW read the SPS/PPS information from PPS packet index by PPS id. -+ * offset from the base can be calculated by PPS_id * 32 (size per PPS -+ * packet unit). so the driver copy SPS/PPS information to the exact PPS -+ * packet unit for HW accessing. -+ */ -+ hw_ps = &priv_tbl->param_set; -+ memset(hw_ps, 0, sizeof(*hw_ps)); -+ -+ /* write sps */ -+ hw_ps->video_parameters_set_id = sps->video_parameter_set_id; -+ hw_ps->seq_parameters_set_id_sps = sps->seq_parameter_set_id; -+ hw_ps->chroma_format_idc = sps->chroma_format_idc; -+ -+ log2_min_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ width = sps->pic_width_in_luma_samples; -+ height = sps->pic_height_in_luma_samples; -+ hw_ps->width = width; -+ hw_ps->height = height; -+ hw_ps->bit_depth_luma = sps->bit_depth_luma_minus8 + 8; -+ hw_ps->bit_depth_chroma = sps->bit_depth_chroma_minus8 + 8; -+ hw_ps->max_pic_order_count_lsb = sps->log2_max_pic_order_cnt_lsb_minus4 + 4; -+ hw_ps->diff_max_min_luma_coding_block_size = sps->log2_diff_max_min_luma_coding_block_size; -+ hw_ps->min_luma_coding_block_size = sps->log2_min_luma_coding_block_size_minus3 + 3; -+ hw_ps->min_transform_block_size = sps->log2_min_luma_transform_block_size_minus2 + 2; -+ hw_ps->diff_max_min_transform_block_size = -+ sps->log2_diff_max_min_luma_transform_block_size; -+ hw_ps->max_transform_hierarchy_depth_inter = sps->max_transform_hierarchy_depth_inter; -+ hw_ps->max_transform_hierarchy_depth_intra = sps->max_transform_hierarchy_depth_intra; -+ hw_ps->scaling_list_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED); -+ hw_ps->amp_enabled_flag = !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED); -+ hw_ps->sample_adaptive_offset_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET); -+ -+ pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED); -+ hw_ps->pcm_enabled_flag = pcm_enabled; -+ hw_ps->pcm_sample_bit_depth_luma = -+ pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0; -+ hw_ps->pcm_sample_bit_depth_chroma = -+ pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0; -+ hw_ps->pcm_loop_filter_disabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED); -+ hw_ps->diff_max_min_pcm_luma_coding_block_size = -+ sps->log2_diff_max_min_pcm_luma_coding_block_size; -+ hw_ps->min_pcm_luma_coding_block_size = -+ pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0; -+ hw_ps->num_short_term_ref_pic_sets = sps->num_short_term_ref_pic_sets; -+ hw_ps->long_term_ref_pics_present_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT); -+ hw_ps->num_long_term_ref_pics_sps = sps->num_long_term_ref_pics_sps; -+ hw_ps->sps_temporal_mvp_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED); -+ hw_ps->strong_intra_smoothing_enabled_flag = -+ !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED); -+ hw_ps->sps_max_dec_pic_buffering_minus1 = sps->sps_max_dec_pic_buffering_minus1; -+ -+ /* write pps */ -+ hw_ps->picture_parameters_set_id = pps->pic_parameter_set_id; -+ hw_ps->seq_parameters_set_id_pps = sps->seq_parameter_set_id; -+ hw_ps->dependent_slice_segments_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED); -+ hw_ps->output_flag_present_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT); -+ hw_ps->num_extra_slice_header_bits = pps->num_extra_slice_header_bits; -+ hw_ps->sign_data_hiding_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED); -+ hw_ps->cabac_init_present_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT); -+ hw_ps->num_ref_idx_l0_default_active = pps->num_ref_idx_l0_default_active_minus1 + 1; -+ hw_ps->num_ref_idx_l1_default_active = pps->num_ref_idx_l1_default_active_minus1 + 1; -+ hw_ps->init_qp_minus26 = pps->init_qp_minus26; -+ hw_ps->constrained_intra_pred_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED); -+ hw_ps->transform_skip_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED); -+ hw_ps->cu_qp_delta_enabled_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED); -+ hw_ps->log2_min_cb_size = log2_min_cb_size + -+ sps->log2_diff_max_min_luma_coding_block_size - -+ pps->diff_cu_qp_delta_depth; -+ hw_ps->pps_cb_qp_offset = pps->pps_cb_qp_offset; -+ hw_ps->pps_cr_qp_offset = pps->pps_cr_qp_offset; -+ hw_ps->pps_slice_chroma_qp_offsets_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT); -+ hw_ps->weighted_pred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED); -+ hw_ps->weighted_bipred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED); -+ hw_ps->transquant_bypass_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED); -+ tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED); -+ hw_ps->tiles_enabled_flag = tiles_enabled; -+ hw_ps->entropy_coding_sync_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED); -+ hw_ps->pps_loop_filter_across_slices_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED); -+ hw_ps->loop_filter_across_tiles_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED); -+ hw_ps->deblocking_filter_override_enabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED); -+ hw_ps->pps_deblocking_filter_disabled_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER); -+ hw_ps->pps_beta_offset_div2 = pps->pps_beta_offset_div2; -+ hw_ps->pps_tc_offset_div2 = pps->pps_tc_offset_div2; -+ hw_ps->lists_modification_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT); -+ hw_ps->log2_parallel_merge_level = pps->log2_parallel_merge_level_minus2 + 2; -+ hw_ps->slice_segment_header_extension_present_flag = -+ !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT); -+ hw_ps->num_tile_columns = tiles_enabled ? pps->num_tile_columns_minus1 + 1 : 1; -+ hw_ps->num_tile_rows = tiles_enabled ? pps->num_tile_rows_minus1 + 1 : 1; -+ hw_ps->mvc_ff = 0xffff; -+ -+ // Setup tiles information -+ memset(column_width, 0, sizeof(column_width)); -+ memset(row_height, 0, sizeof(row_height)); -+ -+ max_cu_width = 1 << (sps->log2_diff_max_min_luma_coding_block_size + log2_min_cb_size); -+ pic_in_cts_width = (width + max_cu_width - 1) / max_cu_width; -+ pic_in_cts_height = (height + max_cu_width - 1) / max_cu_width; -+ -+ if (tiles_enabled) { -+ if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) { -+ compute_tiles_uniform(run, log2_min_cb_size, width, height, -+ pic_in_cts_width, pic_in_cts_height, -+ column_width, row_height); -+ } else { -+ compute_tiles_non_uniform(run, log2_min_cb_size, width, height, -+ pic_in_cts_width, pic_in_cts_height, -+ column_width, row_height); -+ } -+ } else { -+ column_width[0] = (width + max_cu_width - 1) / max_cu_width; -+ row_height[0] = (height + max_cu_width - 1) / max_cu_width; -+ } -+ -+ for (i = 0; i < 22; i++) -+ set_column_row(hw_ps, column_width[i], row_height[i], i); -+ -+ // Setup POC information -+ hw_ps->current_poc = dec_params->pic_order_cnt_val; -+ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) { -+ u32 valid = !!(dec_params->num_active_dpb_entries > i); -+ -+ set_pps_ref_pic_poc(hw_ps, dec_params->dpb[i].pic_order_cnt_val, i); -+ hw_ps->ref_is_valid |= valid << i; -+ } -+} -+ -+static void rkvdec_write_regs(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_ctx *h265_ctx = ctx->priv; -+ -+ rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_COMMON_REGS, -+ &h265_ctx->regs.common, -+ sizeof(h265_ctx->regs.common)); -+ rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_COMMON_ADDR_REGS, -+ &h265_ctx->regs.common_addr, -+ sizeof(h265_ctx->regs.common_addr)); -+ rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_CODEC_PARAMS_REGS, -+ &h265_ctx->regs.h26x_params, -+ sizeof(h265_ctx->regs.h26x_params)); -+ rkvdec_memcpy_toio(rkvdec->regs + VDPU383_OFFSET_CODEC_ADDR_REGS, -+ &h265_ctx->regs.h26x_addr, -+ sizeof(h265_ctx->regs.h26x_addr)); -+} -+ -+static void config_registers(struct rkvdec_ctx *ctx, -+ struct rkvdec_hevc_run *run) -+{ -+ const struct v4l2_ctrl_hevc_decode_params *dec_params = run->decode_params; -+ struct rkvdec_hevc_ctx *h265_ctx = ctx->priv; -+ const struct v4l2_ctrl_hevc_sps *sps = run->sps; -+ dma_addr_t priv_start_addr = h265_ctx->priv_tbl.dma; -+ const struct v4l2_pix_format_mplane *dst_fmt; -+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; -+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; -+ struct vdpu383_regs_h26x *regs = &h265_ctx->regs; -+ const struct v4l2_format *f; -+ dma_addr_t rlc_addr; -+ dma_addr_t dst_addr; -+ u32 hor_virstride; -+ u32 ver_virstride; -+ u32 y_virstride; -+ u32 offset; -+ u32 pixels; -+ u32 i; -+ -+ memset(regs, 0, sizeof(*regs)); -+ -+ /* Set H264 mode */ -+ regs->common.reg008_dec_mode = VDPU383_MODE_HEVC; -+ -+ /* Set input stream length */ -+ regs->h26x_params.reg066_stream_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); -+ -+ /* Set strides */ -+ f = &ctx->decoded_fmt; -+ dst_fmt = &f->fmt.pix_mp; -+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; -+ ver_virstride = dst_fmt->height; -+ y_virstride = hor_virstride * ver_virstride; -+ -+ pixels = dst_fmt->height * dst_fmt->width; -+ -+ regs->h26x_params.reg068_hor_virstride = hor_virstride / 16; -+ regs->h26x_params.reg069_raster_uv_hor_virstride = hor_virstride / 16; -+ regs->h26x_params.reg070_y_virstride = y_virstride / 16; -+ -+ /* Activate block gating */ -+ regs->common.reg010.strmd_auto_gating_e = 1; -+ regs->common.reg010.inter_auto_gating_e = 1; -+ regs->common.reg010.intra_auto_gating_e = 1; -+ regs->common.reg010.transd_auto_gating_e = 1; -+ regs->common.reg010.recon_auto_gating_e = 1; -+ regs->common.reg010.filterd_auto_gating_e = 1; -+ regs->common.reg010.bus_auto_gating_e = 1; -+ regs->common.reg010.ctrl_auto_gating_e = 1; -+ regs->common.reg010.rcb_auto_gating_e = 1; -+ regs->common.reg010.err_prc_auto_gating_e = 1; -+ -+ /* Set timeout threshold */ -+ if (pixels < VDPU383_1080P_PIXELS) -+ regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_1080p; -+ else if (pixels < VDPU383_4K_PIXELS) -+ regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_4K; -+ else if (pixels < VDPU383_8K_PIXELS) -+ regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_8K; -+ else -+ regs->common.reg013_core_timeout_threshold = VDPU383_TIMEOUT_MAX; -+ -+ regs->common.reg016.error_proc_disable = 1; -+ -+ /* Set ref pic address & poc */ -+ for (i = 0; i < ARRAY_SIZE(dec_params->dpb) - 1; i++) { -+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); -+ dma_addr_t buf_dma; -+ -+ buf_dma = vb2_dma_contig_plane_dma_addr(vb_buf, 0); -+ -+ /* Set reference addresses */ -+ regs->h26x_addr.reg170_185_ref_base[i] = buf_dma; -+ regs->h26x_addr.reg195_210_payload_st_ref_base[i] = buf_dma; -+ -+ /* Set COLMV addresses */ -+ regs->h26x_addr.reg217_232_colmv_ref_base[i] = buf_dma + ctx->colmv_offset; -+ } -+ -+ /* Set rlc base address (input stream) */ -+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); -+ regs->common_addr.reg128_strm_base = rlc_addr; -+ -+ /* Set output base address */ -+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); -+ regs->h26x_addr.reg168_decout_base = dst_addr; -+ regs->h26x_addr.reg169_error_ref_base = dst_addr; -+ regs->h26x_addr.reg192_payload_st_cur_base = dst_addr; -+ -+ /* Set colmv address */ -+ regs->h26x_addr.reg216_colmv_cur_base = dst_addr + ctx->colmv_offset; -+ -+ /* Set RCB addresses */ -+ for (i = 0; i < rkvdec_rcb_buf_count(ctx); i++) { -+ regs->common_addr.reg140_162_rcb_info[i].offset = rkvdec_rcb_buf_dma_addr(ctx, i); -+ regs->common_addr.reg140_162_rcb_info[i].size = rkvdec_rcb_buf_size(ctx, i); -+ } -+ -+ if (sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED) { -+ /* Set scaling matrix */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); -+ regs->common_addr.reg132_scanlist_addr = priv_start_addr + offset; -+ } -+ -+ /* Set hw pps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); -+ regs->common_addr.reg131_gbl_base = priv_start_addr + offset; -+ regs->h26x_params.reg067_global_len = sizeof(struct rkvdec_hevc_sps_pps) / 16; -+ -+ /* Set hw rps address */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); -+ regs->common_addr.reg129_rps_base = priv_start_addr + offset; -+ -+ /* Set cabac table */ -+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); -+ regs->common_addr.reg130_cabactbl_base = priv_start_addr + offset; -+ -+ rkvdec_write_regs(ctx); -+} -+ -+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_priv_tbl *priv_tbl; -+ struct rkvdec_hevc_ctx *hevc_ctx; -+ struct v4l2_ctrl *ctrl; -+ int ret; -+ -+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, -+ V4L2_CID_STATELESS_HEVC_SPS); -+ if (!ctrl) -+ return -EINVAL; -+ -+ ret = rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); -+ if (ret) -+ return ret; -+ -+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); -+ if (!hevc_ctx) -+ return -ENOMEM; -+ -+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), -+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); -+ if (!priv_tbl) { -+ ret = -ENOMEM; -+ goto err_free_ctx; -+ } -+ -+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); -+ hevc_ctx->priv_tbl.cpu = priv_tbl; -+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, -+ sizeof(rkvdec_hevc_cabac_table)); -+ -+ ctx->priv = hevc_ctx; -+ return 0; -+ -+err_free_ctx: -+ kfree(hevc_ctx); -+ return ret; -+} -+ -+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ -+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, -+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); -+ kfree(hevc_ctx); -+} -+ -+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) -+{ -+ struct rkvdec_dev *rkvdec = ctx->dev; -+ struct rkvdec_hevc_run run; -+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; -+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; -+ u32 watchdog_time; -+ u64 timeout_threshold; -+ unsigned long axi_rate; -+ -+ rkvdec_hevc_run_preamble(ctx, &run); -+ -+ rkvdec_hevc_assemble_hw_scaling_list(rkvdec, &run, -+ &tbl->scaling_list, -+ &hevc_ctx->scaling_matrix_cache); -+ assemble_hw_pps(ctx, &run); -+ rkvdec_hevc_assemble_hw_rps(&run, &tbl->rps, &hevc_ctx->st_cache); -+ -+ config_registers(ctx, &run); -+ -+ rkvdec_run_postamble(ctx, &run.base); -+ -+ /* Set watchdog at 2 times the hardware timeout threshold */ -+ timeout_threshold = hevc_ctx->regs.common.reg013_core_timeout_threshold; -+ axi_rate = clk_get_rate(rkvdec->axi_clk); -+ -+ if (axi_rate) -+ watchdog_time = 2 * (1000 * timeout_threshold) / axi_rate; -+ else -+ watchdog_time = 2000; -+ schedule_delayed_work(&rkvdec->watchdog_work, -+ msecs_to_jiffies(watchdog_time)); -+ -+ /* Start decoding! */ -+ writel(timeout_threshold, rkvdec->link + VDPU383_LINK_TIMEOUT_THRESHOLD); -+ writel(VDPU383_IP_CRU_MODE, rkvdec->link + VDPU383_LINK_IP_ENABLE); -+ writel(VDPU383_DEC_E_BIT, rkvdec->link + VDPU383_LINK_DEC_ENABLE); -+ -+ return 0; -+} -+ -+const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_hevc_fmt_ops = { -+ .adjust_fmt = rkvdec_hevc_adjust_fmt, -+ .start = rkvdec_hevc_start, -+ .stop = rkvdec_hevc_stop, -+ .run = rkvdec_hevc_run, -+ .try_ctrl = rkvdec_hevc_try_ctrl, -+ .get_image_fmt = rkvdec_hevc_get_image_fmt, -+}; -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c -@@ -526,6 +526,22 @@ static const struct rkvdec_coded_fmt_desc vdpu383_coded_fmts[] = { - .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, - .capability = RKVDEC_CAPABILITY_H264, - }, -+ { -+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, -+ .frmsize = { -+ .min_width = 16, -+ .max_width = 65472, -+ .step_width = 16, -+ .min_height = 16, -+ .max_height = 65472, -+ .step_height = 16, -+ }, -+ .ctrls = &vdpu38x_hevc_ctrls, -+ .ops = &rkvdec_vdpu383_hevc_fmt_ops, -+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), -+ .decoded_fmts = rkvdec_hevc_decoded_fmts, -+ .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, -+ }, - }; - - static bool rkvdec_is_capable(struct rkvdec_ctx *ctx, unsigned int capability) -@@ -1458,6 +1474,78 @@ static irqreturn_t rkvdec_irq_handler(int irq, void *priv) - return cfg->irq_handler(ctx); - } - -+/* -+ * Flip one or more matrices along their main diagonal and flatten them -+ * before writing it to the memory. -+ * Convert: -+ * ABCD AEIM -+ * EFGH => BFJN => AEIMBFJNCGKODHLP -+ * IJKL CGKO -+ * MNOP DHLP -+ */ -+static void transpose_and_flatten_matrices(u8 *output, const u8 *input, -+ int matrices, int row_length) -+{ -+ int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value; -+ -+ matrix_size = row_length * row_length; -+ for (i = 0; i < matrices; i++) { -+ row = 0; -+ x_offset = 0; -+ matrix_offset = i * matrix_size; -+ for (j = 0; j < matrix_size; j++) { -+ y_offset = j - (row * row_length); -+ rot_index = y_offset * row_length + x_offset; -+ new_value = *(input + i * matrix_size + j); -+ output[matrix_offset + rot_index] = new_value; -+ if ((j + 1) % row_length == 0) { -+ row += 1; -+ x_offset += 1; -+ } -+ } -+ } -+} -+ -+/* -+ * VDPU383 needs a specific order: -+ * The 8x8 flatten matrix is based on 4x4 blocks. -+ * Each 4x4 block is written separately in order. -+ * -+ * Base data => Transposed VDPU383 transposed -+ * -+ * ABCDEFGH AIQYaiqy AIQYBJRZ -+ * IJKLMNOP BJRZbjrz CKS0DLT1 -+ * QRSTUVWX CKS0cks6 aiqybjrz -+ * YZ012345 => DLT1dlt7 cks6dlt7 -+ * abcdefgh EMU2emu8 EMU2FNV3 -+ * ijklmnop FNV3fnv9 GOW4HPX5 -+ * qrstuvwx GOW4gow# emu8fnv9 -+ * yz6789#$ HPX5hpx$ gow#hpx$ -+ * -+ * As the function reads block of 4x4 it can be used for both 4x4 and 8x8 matrices. -+ * -+ */ -+static void vdpu383_flatten_matrices(u8 *output, const u8 *input, int matrices, int row_length) -+{ -+ u8 block; -+ int i, j, matrix_offset, matrix_size, new_value, input_idx, line_offset, block_offset; -+ -+ matrix_size = row_length * row_length; -+ for (i = 0; i < matrices; i++) { -+ matrix_offset = i * matrix_size; -+ for (j = 0; j < matrix_size; j++) { -+ block = j / 16; -+ line_offset = (j % 16) / 4; -+ block_offset = (block & 1) * 32 + (block & 2) * 2; -+ input_idx = ((j % 4) * row_length) + line_offset + block_offset; -+ -+ new_value = *(input + i * matrix_size + input_idx); -+ -+ output[matrix_offset + j] = new_value; -+ } -+ } -+} -+ - static void rkvdec_watchdog_func(struct work_struct *work) - { - struct rkvdec_dev *rkvdec; -@@ -1521,6 +1609,7 @@ static const struct rkvdec_config config_rkvdec = { - .coded_fmts_num = ARRAY_SIZE(rkvdec_coded_fmts), - .irq_handler = rk3399_irq_handler, - .fill_pixfmt_mp = v4l2_fill_pixfmt_mp, -+ .flatten_matrices = transpose_and_flatten_matrices, - .colmv_size = rkvdec_colmv_size, - }; - -@@ -1545,6 +1634,7 @@ static const struct rkvdec_config config_vdpu381 = { - .irq_handler = vdpu381_irq_handler, - .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, - .colmv_size = rkvdec_colmv_size, -+ .flatten_matrices = transpose_and_flatten_matrices, - .named_regs = true, - }; - -@@ -1570,6 +1660,7 @@ const struct rkvdec_config config_vdpu383 = { - .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, - .colmv_size = rkvdec_vdpu383_colmv_size, - .fill_pixfmt_mp = vdpu38x_fill_pixfmt_mp, -+ .flatten_matrices = vdpu383_flatten_matrices, - .named_regs = true, - }; - -@@ -1601,7 +1692,8 @@ static const struct rkvdec_variant rk3588_vdpu381_variant = { - - static const struct rkvdec_variant rk3576_vdpu383_variant = { - .config = &config_vdpu383, -- .capabilities = RKVDEC_CAPABILITY_H264, -+ .capabilities = RKVDEC_CAPABILITY_H264 | -+ RKVDEC_CAPABILITY_HEVC, - }; - - static const struct of_device_id of_rkvdec_match[] = { -diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -index 111111111111..222222222222 100644 ---- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h -+++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h -@@ -124,6 +124,7 @@ struct rkvdec_config { - int (*fill_pixfmt_mp)(struct v4l2_pix_format_mplane *pix_mp, u32 pixelformat, - u32 width, u32 height); - u32 (*colmv_size)(u16 width, u16 height); -+ void (*flatten_matrices)(u8 *output, const u8 *input, int matrices, int row_length); - bool named_regs; - }; - -@@ -193,5 +194,6 @@ extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu381_hevc_fmt_ops; - - /* VDPU383 ops */ - extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_h264_fmt_ops; -+extern const struct rkvdec_coded_fmt_ops rkvdec_vdpu383_hevc_fmt_ops; - - #endif /* RKVDEC_H_ */ --- -Armbian - diff --git a/patch/kernel/archive/rockchip64-6.16/rk3576-0001-sige5-wifi.patch b/patch/kernel/archive/rockchip64-6.16/rk3576-0001-sige5-wifi.patch deleted file mode 100644 index 98cee21acdc5..000000000000 --- a/patch/kernel/archive/rockchip64-6.16/rk3576-0001-sige5-wifi.patch +++ /dev/null @@ -1,120 +0,0 @@ -From 358ccc1d8b242b8c659e5e177caef174624e8cb6 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Sat, 14 Jun 2025 22:14:35 +0400 -Subject: arm64: dts: rockchip: add version-independent WiFi/BT nodes on Sige5 - -ArmSoM Sige5 uses a soldered-on WiFi/BT module with WiFi on SDIO and BT -on UART. However, board v1.1 uses a Realtek based BL-M8852BS2, while -v1.2 uses a Broadcom based BW3752-50B1. They use the same pins and -controllers, but require different DT properties to enable. - -Thankfully, the WiFi part at least works without explicitly listing it in -the device tree, albeit without OOB interrupt functionality. - -Add required device tree nodes that do not depend on the board version so -that at least the WiFi module can appear on the SDIO bus. - -WiFi OOB interrupt and Bluetooth function support are not enabled here, as -they require module specific properties. - -Signed-off-by: Alexey Charkov -Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-3-3bb31b02623c@gmail.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3576-armsom-sige5.dts | 57 ++++++++++++++++++++++ - 1 file changed, 57 insertions(+) - -(limited to 'arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts') - -diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts -index 34e51cd71eac03..8f6d50febf830e 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts -@@ -205,6 +205,15 @@ vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_5v0_sys>; - }; -+ -+ sdio_pwrseq: sdio-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ clocks = <&hym8563>; -+ clock-names = "ext_clock"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wifi_reg_on>; -+ reset-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; -+ }; - }; - - &combphy0_ps { -@@ -736,6 +745,30 @@ pcie_reset: pcie-reset { - rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -+ -+ wireless-bluetooth { -+ bt_reg_on: bt-reg-on { -+ rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ host_wake_bt: host-wake-bt { -+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ -+ bt_wake_host: bt-wake-host { -+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ -+ wireless-wlan { -+ wifi_wake_host: wifi-wake-host { -+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ -+ wifi_reg_on: wifi-reg-on { -+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; - }; - - &sai1 { -@@ -763,6 +796,23 @@ &sdhci { - status = "okay"; - }; - -+&sdio { -+ bus-width = <4>; -+ cap-sdio-irq; -+ disable-wp; -+ keep-power-in-suspend; -+ mmc-pwrseq = <&sdio_pwrseq>; -+ no-sd; -+ no-mmc; -+ non-removable; -+ sd-uhs-sdr50; -+ sd-uhs-sdr104; -+ vmmc-supply = <&vcc_3v3_s3>; -+ vqmmc-supply = <&vcc_1v8_s3>; -+ wakeup-source; -+ status = "okay"; -+}; -+ - &sdmmc { - bus-width = <4>; - cap-mmc-highspeed; -@@ -782,6 +832,13 @@ &uart0 { - status = "okay"; - }; - -+/* Used by Bluetooth modules, enabled in a version specific overlay */ -+&uart4 { -+ pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn &uart4m1_rtsn>; -+ pinctrl-names = "default"; -+ uart-has-rtscts; -+}; -+ - &vop { - status = "okay"; - }; --- -cgit 1.2.3-korg - diff --git a/patch/kernel/archive/rockchip64-6.16/rk3576-0002-sige5-usb.patch b/patch/kernel/archive/rockchip64-6.16/rk3576-0002-sige5-usb.patch deleted file mode 100644 index f8fb70147c28..000000000000 --- a/patch/kernel/archive/rockchip64-6.16/rk3576-0002-sige5-usb.patch +++ /dev/null @@ -1,234 +0,0 @@ -From 64df8e2e207a2152201ef3515baacd8816c13282 Mon Sep 17 00:00:00 2001 -From: Nicolas Frattaroli -Date: Thu, 19 Jun 2025 20:36:37 +0200 -Subject: arm64: dts: rockchip: enable USB on Sige5 - -The ArmSoM Sige5 has several USB ports: a Type-A USB 3 port (USB2 lines -going through a hub), a Type-A USB 2.0 port (also going through a hub), -a Type-C DC input port that has absolutely no USB data connection and a -Type-C port with USB3.2 Gen1x1 that's also the maskrom programming port. - -Enable these ports, and set the device role to be host for the host -ports. - -The data capable Type-C USB port uses a fusb302 for data role switching. - -Signed-off-by: Nicolas Frattaroli -Link: https://lore.kernel.org/r/20250619-rk3576-sige5-usb-v5-2-9069a7e750e1@collabora.com -Signed-off-by: Heiko Stuebner ---- - .../boot/dts/rockchip/rk3576-armsom-sige5.dts | 161 +++++++++++++++++++++ - 1 file changed, 161 insertions(+) - -(limited to 'arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts') - -diff --git a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts -index 8f6d50febf830e..78add29f8a5c73 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts -+++ b/arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dts -@@ -196,6 +196,30 @@ vcc_5v0_device: regulator-vcc-5v0-device { - vin-supply = <&vcc_12v0_dcin>; - }; - -+ vcc_5v0_typec0: regulator-vcc-5v0-typec0 { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_otg0_pwren>; -+ regulator-name = "vcc_5v0_typec0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_5v0_device>; -+ }; -+ -+ vcc_5v0_usbhost: regulator-vcc-5v0-usbhost { -+ compatible = "regulator-fixed"; -+ enable-active-high; -+ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usb_host_pwren>; -+ regulator-name = "vcc_5v0_usbhost"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc_5v0_device>; -+ }; -+ - vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { - compatible = "regulator-fixed"; - regulator-name = "vcc_3v3_ufs_s0"; -@@ -216,6 +240,10 @@ sdio_pwrseq: sdio-pwrseq { - }; - }; - -+&combphy1_psu { -+ status = "okay"; -+}; -+ - &combphy0_ps { - status = "okay"; - }; -@@ -640,6 +668,58 @@ regulator-state-mem { - &i2c2 { - status = "okay"; - -+ usbc0: typec-portc@22 { -+ compatible = "fcs,fusb302"; -+ reg = <0x22>; -+ interrupt-parent = <&gpio0>; -+ interrupts = ; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usbc0_interrupt>; -+ vbus-supply = <&vcc_5v0_typec0>; -+ -+ connector { -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ data-role = "dual"; -+ /* fusb302 supports PD Rev 2.0 Ver 1.2 */ -+ pd-revision = /bits/ 8 <0x2 0x0 0x1 0x2>; -+ power-role = "source"; -+ source-pdos = ; -+ -+ altmodes { -+ displayport { -+ svid = /bits/ 16 <0xff01>; -+ vdo = <0xffffffff>; -+ }; -+ }; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usbc0_hs_ep: endpoint { -+ remote-endpoint = <&usb_drd0_hs_ep>; -+ }; -+ }; -+ port@1 { -+ reg = <1>; -+ usbc0_ss_ep: endpoint { -+ remote-endpoint = <&usb_drd0_ss_ep>; -+ }; -+ }; -+ port@2 { -+ reg = <2>; -+ usbc0_dp_ep: endpoint { -+ remote-endpoint = <&usbdp_phy_ep>; -+ }; -+ }; -+ }; -+ }; -+ }; -+ - hym8563: rtc@51 { - compatible = "haoyu,hym8563"; - reg = <0x51>; -@@ -746,6 +826,24 @@ pcie_reset: pcie-reset { - }; - }; - -+ usb { -+ usb_host_pwren: usb-host-pwren { -+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ usb_otg0_pwren: usb-otg0-pwren { -+ rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ usbc0_interrupt: usbc0-interrupt { -+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ usbc0_sbu1: usbc0-sbu1 { -+ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ usbc0_sbu2: usbc0-sbu2 { -+ rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; -+ }; -+ }; -+ - wireless-bluetooth { - bt_reg_on: bt-reg-on { - rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; -@@ -827,6 +925,23 @@ &sdmmc { - status = "okay"; - }; - -+&u2phy0 { -+ status = "okay"; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+}; -+ -+&u2phy1 { -+ status = "okay"; -+}; -+ -+&u2phy1_otg { -+ phy-supply = <&vcc_5v0_usbhost>; -+ status = "okay"; -+}; -+ - &uart0 { - pinctrl-0 = <&uart0m0_xfer>; - status = "okay"; -@@ -839,6 +954,52 @@ &uart4 { - uart-has-rtscts; - }; - -+&usb_drd0_dwc3 { -+ usb-role-switch; -+ dr_mode = "otg"; -+ status = "okay"; -+ -+ ports { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ port@0 { -+ reg = <0>; -+ usb_drd0_hs_ep: endpoint { -+ remote-endpoint = <&usbc0_hs_ep>; -+ }; -+ }; -+ -+ port@1 { -+ reg = <1>; -+ usb_drd0_ss_ep: endpoint { -+ remote-endpoint = <&usbc0_ss_ep>; -+ }; -+ }; -+ }; -+}; -+ -+&usb_drd1_dwc3 { -+ dr_mode = "host"; -+ status = "okay"; -+}; -+ -+&usbdp_phy { -+ mode-switch; -+ orientation-switch; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usbc0_sbu1 &usbc0_sbu2>; -+ sbu1-dc-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; -+ sbu2-dc-gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+ port { -+ usbdp_phy_ep: endpoint { -+ remote-endpoint = <&usbc0_dp_ep>; -+ }; -+ }; -+}; -+ - &vop { - status = "okay"; - }; --- -cgit 1.2.3-korg - diff --git a/patch/kernel/archive/rockchip64-6.16/rk3576-0003-rk3576-sdio.patch b/patch/kernel/archive/rockchip64-6.16/rk3576-0003-rk3576-sdio.patch deleted file mode 100644 index 3073644d7954..000000000000 --- a/patch/kernel/archive/rockchip64-6.16/rk3576-0003-rk3576-sdio.patch +++ /dev/null @@ -1,48 +0,0 @@ -From e490f854b46369b096f3d09c0c6a00f340425136 Mon Sep 17 00:00:00 2001 -From: Alexey Charkov -Date: Sat, 14 Jun 2025 22:14:34 +0400 -Subject: arm64: dts: rockchip: add SDIO controller on RK3576 - -RK3576 has one more SD/MMC controller than are currently listed in its -.dtsi, with the missing one intended as an SDIO controller. Add the -missing node (tested with the onboard WiFi module on ArmSoM Sige5 v1.2) - -Signed-off-by: Alexey Charkov -Link: https://lore.kernel.org/r/20250614-sige5-updates-v2-2-3bb31b02623c@gmail.com -Signed-off-by: Heiko Stuebner ---- - arch/arm64/boot/dts/rockchip/rk3576.dtsi | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - -(limited to 'arch/arm64/boot/dts/rockchip/rk3576.dtsi') - -diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi -index 1086482f047923..d3225d20baadd5 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi -@@ -1695,6 +1695,22 @@ sdmmc: mmc@2a310000 { - status = "disabled"; - }; - -+ sdio: mmc@2a320000 { -+ compatible = "rockchip,rk3576-dw-mshc"; -+ reg = <0x0 0x2a320000 0x0 0x4000>; -+ clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>; -+ clock-names = "biu", "ciu"; -+ fifo-depth = <0x100>; -+ interrupts = ; -+ max-frequency = <200000000>; -+ pinctrl-0 = <&sdmmc1m0_clk &sdmmc1m0_cmd &sdmmc1m0_bus4>; -+ pinctrl-names = "default"; -+ power-domains = <&power RK3576_PD_SDGMAC>; -+ resets = <&cru SRST_H_SDIO>; -+ reset-names = "reset"; -+ status = "disabled"; -+ }; -+ - sdhci: mmc@2a330000 { - compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; - reg = <0x0 0x2a330000 0x0 0x10000>; --- -cgit 1.2.3-korg - diff --git a/patch/kernel/archive/rockchip64-6.16/rk3576-thermal-support.patch b/patch/kernel/archive/rockchip64-6.16/rk3576-thermal-support.patch deleted file mode 100644 index bb4d0245f633..000000000000 --- a/patch/kernel/archive/rockchip64-6.16/rk3576-thermal-support.patch +++ /dev/null @@ -1,1041 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: SuperKali -Date: Thu, 11 Sep 2025 15:32:33 +0200 -Subject: rockchip: Add RK3576 thermal sensor support with OTP trim - -Add support for the RK3576's thermal sensor with six channels -providing measurements for package temperature, big cores, little -cores, GPU, NPU and DDR controller. - -This includes: -- Device tree binding updates for RK3576 TSADC -- Support for reading thermal trim values from OTP cells -- Thermal zones configuration with passive cooling -- Driver support for RK3576 hardware variant - -The trim functionality improves sensor accuracy by applying -per-sensor calibration offsets stored in factory-programmed -OTP memory. - -Based on patches from Nicolas Frattaroli and Ye Zhang. - -Signed-off-by: SuperKali -Link: https://lore.kernel.org/all/aHgGiojM3nnNg8Bk@mai.linaro.org/ ---- - Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 63 ++- - arch/arm64/boot/dts/rockchip/rk3576.dtsi | 214 ++++++++++ - drivers/thermal/rockchip_thermal.c | 273 ++++++++-- - 3 files changed, 504 insertions(+), 46 deletions(-) - -diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml -index 89baf5e6d..573f447cc 100644 ---- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml -+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml -@@ -15,15 +15,15 @@ properties: - compatible: - enum: - - rockchip,px30-tsadc - - rockchip,rk3228-tsadc - - rockchip,rk3288-tsadc -- - rockchip,rk3308-tsadc - - rockchip,rk3328-tsadc - - rockchip,rk3368-tsadc - - rockchip,rk3399-tsadc - - rockchip,rk3568-tsadc -+ - rockchip,rk3576-tsadc - - rockchip,rk3588-tsadc - - rockchip,rv1108-tsadc - - reg: - maxItems: 1 -@@ -38,10 +38,21 @@ properties: - clock-names: - items: - - const: tsadc - - const: apb_pclk - -+ nvmem-cells: -+ items: -+ - description: cell handle to where the trim's base temperature is stored -+ - description: -+ cell handle to where the trim's tenths of Celsius base value is stored -+ -+ nvmem-cell-names: -+ items: -+ - const: trim_base -+ - const: trim_base_frac -+ - resets: - minItems: 1 - maxItems: 3 - - reset-names: -@@ -49,10 +60,16 @@ properties: - items: - - const: tsadc-apb - - const: tsadc - - const: tsadc-phy - -+ "#address-cells": -+ const: 1 -+ -+ "#size-cells": -+ const: 0 -+ - "#thermal-sensor-cells": - const: 1 - - rockchip,grf: - description: The phandle of the syscon node for the general register file. -@@ -70,18 +87,62 @@ properties: - rockchip,hw-tshut-polarity: - description: The hardware-controlled active polarity 0:LOW 1:HIGH. - $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1] - -+patternProperties: -+ "@[0-9a-f]+$": -+ type: object -+ properties: -+ reg: -+ maxItems: 1 -+ description: sensor ID, a.k.a. channel number -+ -+ nvmem-cells: -+ items: -+ - description: handle of cell containing calibration data -+ -+ nvmem-cell-names: -+ items: -+ - const: trim -+ -+ required: -+ - reg -+ -+ unevaluatedProperties: false -+ - required: - - compatible - - reg - - interrupts - - clocks - - clock-names - - resets - -+allOf: -+ - if: -+ not: -+ properties: -+ compatible: -+ contains: -+ const: rockchip,rk3568-tsadc -+ then: -+ properties: -+ nvmem-cells: false -+ nvmem-cell-names: false -+ - if: -+ not: -+ properties: -+ compatible: -+ contains: -+ enum: -+ - rockchip,rk3568-tsadc -+ - rockchip,rk3576-tsadc -+ then: -+ patternProperties: -+ "@[0-9a-f]+$": false -+ - unevaluatedProperties: false - - examples: - - | - #include -diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi -index b99f4bd4c..8264feec6 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi -@@ -9,10 +9,11 @@ - #include - #include - #include - #include - #include -+#include - - / { - compatible = "rockchip,rk3576"; - - interrupt-parent = <&gic>; -@@ -124,10 +125,11 @@ cpu_l1: cpu@1 { - reg = <0x1>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&scmi_clk SCMI_ARMCLK_L>; - operating-points-v2 = <&cluster0_opp_table>; -+ #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - }; - - cpu_l2: cpu@2 { - device_type = "cpu"; -@@ -135,10 +137,11 @@ cpu_l2: cpu@2 { - reg = <0x2>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&scmi_clk SCMI_ARMCLK_L>; - operating-points-v2 = <&cluster0_opp_table>; -+ #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - }; - - cpu_l3: cpu@3 { - device_type = "cpu"; -@@ -146,10 +149,11 @@ cpu_l3: cpu@3 { - reg = <0x3>; - enable-method = "psci"; - capacity-dmips-mhz = <485>; - clocks = <&scmi_clk SCMI_ARMCLK_L>; - operating-points-v2 = <&cluster0_opp_table>; -+ #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - }; - - cpu_b0: cpu@100 { - device_type = "cpu"; -@@ -170,10 +174,11 @@ cpu_b1: cpu@101 { - reg = <0x101>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_ARMCLK_B>; - operating-points-v2 = <&cluster1_opp_table>; -+ #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - }; - - cpu_b2: cpu@102 { - device_type = "cpu"; -@@ -181,10 +186,11 @@ cpu_b2: cpu@102 { - reg = <0x102>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_ARMCLK_B>; - operating-points-v2 = <&cluster1_opp_table>; -+ #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - }; - - cpu_b3: cpu@103 { - device_type = "cpu"; -@@ -192,10 +198,11 @@ cpu_b3: cpu@103 { - reg = <0x103>; - enable-method = "psci"; - capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk SCMI_ARMCLK_B>; - operating-points-v2 = <&cluster1_opp_table>; -+ #cooling-cells = <2>; - cpu-idle-states = <&CPU_SLEEP>; - }; - - idle-states { - entry-method = "psci"; -@@ -518,10 +525,144 @@ pmu_a72: pmu-a72 { - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - -+ thermal_zones: thermal-zones { -+ package_thermal: package-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 0>; -+ -+ trips { -+ package_crit: package-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ bigcore_thermal: bigcore-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 1>; -+ -+ trips { -+ bigcore_alert: bigcore-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ bigcore_crit: bigcore-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&bigcore_alert>; -+ cooling-device = -+ <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ littlecore_thermal: littlecore-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 2>; -+ -+ trips { -+ littlecore_alert: littlecore-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ littlecore_crit: littlecore-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&littlecore_alert>; -+ cooling-device = -+ <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, -+ <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ gpu_thermal: gpu-thermal { -+ polling-delay-passive = <100>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 3>; -+ -+ trips { -+ gpu_alert: gpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ gpu_crit: gpu-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&gpu_alert>; -+ cooling-device = -+ <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ -+ npu_thermal: npu-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 4>; -+ -+ trips { -+ npu_crit: npu-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ ddr_thermal: ddr-thermal { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&tsadc 5>; -+ -+ trips { -+ ddr_crit: ddr-crit { -+ temperature = <115000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+ - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , -@@ -1823,10 +1964,34 @@ npu_leakage: npu-leakage@20 { - reg = <0x20 0x1>; - }; - gpu_leakage: gpu-leakage@21 { - reg = <0x21 0x1>; - }; -+ bigcore_tsadc_trim: bigcore-tsadc-trim@24 { -+ reg = <0x24 0x2>; -+ bits = <0 10>; -+ }; -+ litcore_tsadc_trim: litcore-tsadc-trim@26 { -+ reg = <0x26 0x2>; -+ bits = <0 10>; -+ }; -+ ddr_tsadc_trim: ddr-tsadc-trim@28 { -+ reg = <0x28 0x2>; -+ bits = <0 10>; -+ }; -+ npu_tsadc_trim: npu-tsadc-trim@2a { -+ reg = <0x2a 0x2>; -+ bits = <0 10>; -+ }; -+ gpu_tsadc_trim: gpu-tsadc-trim@2c { -+ reg = <0x2c 0x2>; -+ bits = <0 10>; -+ }; -+ soc_tsadc_trim: soc-tsadc-trim@64 { -+ reg = <0x64 0x2>; -+ bits = <0 10>; -+ }; - log_leakage: log-leakage@22 { - reg = <0x22 0x1>; - }; - }; - -@@ -2336,10 +2501,59 @@ saradc: adc@2ae00000 { - reset-names = "saradc-apb"; - #io-channel-cells = <1>; - status = "disabled"; - }; - -+ tsadc: tsadc@2ae70000 { -+ compatible = "rockchip,rk3576-tsadc"; -+ reg = <0x0 0x2ae70000 0x0 0x400>; -+ interrupts = ; -+ clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; -+ clock-names = "tsadc", "apb_pclk"; -+ assigned-clocks = <&cru CLK_TSADC>; -+ assigned-clock-rates = <2000000>; -+ resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>; -+ reset-names = "tsadc-apb", "tsadc"; -+ #thermal-sensor-cells = <1>; -+ rockchip,hw-tshut-temp = <120000>; -+ rockchip,hw-tshut-mode = <0>; -+ rockchip,hw-tshut-polarity = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ sensor@0 { -+ reg = <0>; -+ nvmem-cells = <&soc_tsadc_trim>; -+ nvmem-cell-names = "trim"; -+ }; -+ sensor@1 { -+ reg = <1>; -+ nvmem-cells = <&bigcore_tsadc_trim>; -+ nvmem-cell-names = "trim"; -+ }; -+ sensor@2 { -+ reg = <2>; -+ nvmem-cells = <&litcore_tsadc_trim>; -+ nvmem-cell-names = "trim"; -+ }; -+ sensor@3 { -+ reg = <3>; -+ nvmem-cells = <&ddr_tsadc_trim>; -+ nvmem-cell-names = "trim"; -+ }; -+ sensor@4 { -+ reg = <4>; -+ nvmem-cells = <&npu_tsadc_trim>; -+ nvmem-cell-names = "trim"; -+ }; -+ sensor@5 { -+ reg = <5>; -+ nvmem-cells = <&gpu_tsadc_trim>; -+ nvmem-cell-names = "trim"; -+ }; -+ }; -+ - i2c9: i2c@2ae80000 { - compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; - reg = <0x0 0x2ae80000 0x0 0x1000>; - clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; - clock-names = "i2c", "pclk"; -diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c -index 8a8c76bbe..3beff9b6f 100644 ---- a/drivers/thermal/rockchip_thermal.c -+++ b/drivers/thermal/rockchip_thermal.c -@@ -7,10 +7,11 @@ - #include - #include - #include - #include - #include -+#include - #include - #include - #include - #include - #include -@@ -67,27 +68,32 @@ struct chip_tsadc_table { - - /** - * struct rockchip_tsadc_chip - hold the private data of tsadc chip - * @chn_offset: the channel offset of the first channel - * @chn_num: the channel number of tsadc chip -- * @tshut_temp: the hardware-controlled shutdown temperature value -+ * @trim_slope: used to convert the trim code to a temperature in millicelsius -+ * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim - * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) - * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) - * @initialize: SoC special initialize tsadc controller method - * @irq_ack: clear the interrupt - * @control: enable/disable method for the tsadc controller -- * @get_temp: get the temperature -+ * @get_temp: get the raw temperature, unadjusted by trim - * @set_alarm_temp: set the high temperature interrupt - * @set_tshut_temp: set the hardware-controlled shutdown temperature - * @set_tshut_mode: set the hardware-controlled shutdown mode -+ * @get_trim_code: convert a hardware temperature code to one adjusted for by trim - * @table: the chip-specific conversion table - */ - struct rockchip_tsadc_chip { - /* The sensor id of chip correspond to the ADC channel */ - int chn_offset; - int chn_num; - -+ /* Used to convert trim code to trim temp */ -+ int trim_slope; -+ - /* The hardware-controlled tshut property */ - int tshut_temp; - enum tshut_mode tshut_mode; - enum tshut_polarity tshut_polarity; - -@@ -103,25 +109,31 @@ struct rockchip_tsadc_chip { - int (*set_alarm_temp)(const struct chip_tsadc_table *table, - int chn, void __iomem *reg, int temp); - int (*set_tshut_temp)(const struct chip_tsadc_table *table, - int chn, void __iomem *reg, int temp); - void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); -+ int (*get_trim_code)(const struct chip_tsadc_table *table, -+ int code, int trim_base, int trim_base_frac); - - /* Per-table methods */ - struct chip_tsadc_table table; - }; - - /** - * struct rockchip_thermal_sensor - hold the information of thermal sensor - * @thermal: pointer to the platform/configuration data - * @tzd: pointer to a thermal zone -+ * @of_node: pointer to the device_node representing this sensor, if any - * @id: identifier of the thermal sensor -+ * @trim_temp: per-sensor trim temperature value - */ - struct rockchip_thermal_sensor { - struct rockchip_thermal_data *thermal; - struct thermal_zone_device *tzd; -+ struct device_node *of_node; - int id; -+ int trim_temp; - }; - - /** - * struct rockchip_thermal_data - hold the private data of thermal driver - * @chip: pointer to the platform/configuration data -@@ -130,11 +142,15 @@ struct rockchip_thermal_sensor { - * @sensors: array of thermal sensors - * @clk: the controller clock is divided by the exteral 24MHz - * @pclk: the advanced peripherals bus clock - * @grf: the general register file will be used to do static set by software - * @regs: the base address of tsadc controller -- * @tshut_temp: the hardware-controlled shutdown temperature value -+ * @trim_base: major component of sensor trim value, in Celsius -+ * @trim_base_frac: minor component of sensor trim value, in Decicelsius -+ * @trim: fallback thermal trim value for each channel -+ * @tshut_temp: the hardware-controlled shutdown temperature value, with no trim -+ * @trim_temp: the fallback trim temperature for the whole sensor - * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) - * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) - */ - struct rockchip_thermal_data { - const struct rockchip_tsadc_chip *chip; -@@ -147,11 +163,16 @@ struct rockchip_thermal_data { - struct clk *pclk; - - struct regmap *grf; - void __iomem *regs; - -+ int trim_base; -+ int trim_base_frac; -+ int trim; -+ - int tshut_temp; -+ int trim_temp; - enum tshut_mode tshut_mode; - enum tshut_polarity tshut_polarity; - }; - - /* -@@ -247,10 +268,13 @@ struct rockchip_thermal_data { - #define GRF_TSADC_VCM_EN_L (0x10001 << 7) - #define GRF_TSADC_VCM_EN_H (0x10001 << 7) - - #define GRF_CON_TSADC_CH_INV (0x10001 << 1) - -+ -+#define RK_MAX_TEMP (180000) -+ - /** - * struct tsadc_table - code to temperature conversion table - * @code: the value of adc channel - * @temp: the temperature - * Note: -@@ -1043,11 +1067,11 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, - } - - writel_relaxed(val, regs + TSADCV2_INT_EN); - } - --static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, -+static void rk_tsadcv4_tshut_mode(int chn, void __iomem *regs, - enum tshut_mode mode) - { - u32 val_gpio, val_cru; - - if (mode == TSHUT_MODE_GPIO) { -@@ -1059,31 +1083,18 @@ static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs, - } - writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN); - writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN); - } - --static const struct rockchip_tsadc_chip rk3308_tsadc_data = { -- .chn_num = 2, /* 2 channels for tsadc */ -- -- .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ -- .tshut_temp = 95000, -- -- .initialize = rk_tsadcv4_initialize, -- .irq_ack = rk_tsadcv3_irq_ack, -- .control = rk_tsadcv3_control, -- .get_temp = rk_tsadcv2_get_temp, -- .set_alarm_temp = rk_tsadcv2_alarm_temp, -- .set_tshut_temp = rk_tsadcv2_tshut_temp, -- .set_tshut_mode = rk_tsadcv2_tshut_mode, -+static int rk_tsadcv2_get_trim_code(const struct chip_tsadc_table *table, -+ int code, int trim_base, int trim_base_frac) -+{ -+ int temp = trim_base * 1000 + trim_base_frac * 100; -+ u32 base_code = rk_tsadcv2_temp_to_code(table, temp); - -- .table = { -- .id = rk3328_code_table, -- .length = ARRAY_SIZE(rk3328_code_table), -- .data_mask = TSADCV2_DATA_MASK, -- .mode = ADC_INCREMENT, -- }, --}; -+ return code - base_code; -+} - - static const struct rockchip_tsadc_chip px30_tsadc_data = { - /* cpu, gpu */ - .chn_offset = 0, - .chn_num = 2, /* 2 channels for tsadc */ -@@ -1304,10 +1315,34 @@ static const struct rockchip_tsadc_chip rk3568_tsadc_data = { - .data_mask = TSADCV2_DATA_MASK, - .mode = ADC_INCREMENT, - }, - }; - -+static const struct rockchip_tsadc_chip rk3576_tsadc_data = { -+ /* top, big_core, little_core, ddr, npu, gpu */ -+ .chn_offset = 0, -+ .chn_num = 6, /* six channels for tsadc */ -+ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ -+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ -+ .tshut_temp = 95000, -+ .initialize = rk_tsadcv8_initialize, -+ .irq_ack = rk_tsadcv4_irq_ack, -+ .control = rk_tsadcv4_control, -+ .get_temp = rk_tsadcv4_get_temp, -+ .set_alarm_temp = rk_tsadcv3_alarm_temp, -+ .set_tshut_temp = rk_tsadcv3_tshut_temp, -+ .set_tshut_mode = rk_tsadcv4_tshut_mode, -+ .get_trim_code = rk_tsadcv2_get_trim_code, -+ .trim_slope = 923, -+ .table = { -+ .id = rk3588_code_table, -+ .length = ARRAY_SIZE(rk3588_code_table), -+ .data_mask = TSADCV4_DATA_MASK, -+ .mode = ADC_INCREMENT, -+ }, -+}; -+ - static const struct rockchip_tsadc_chip rk3588_tsadc_data = { - /* top, big_core0, big_core1, little_core, center, gpu, npu */ - .chn_offset = 0, - .chn_num = 7, /* seven channels for tsadc */ - .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ -@@ -1317,11 +1352,11 @@ static const struct rockchip_tsadc_chip rk3588_tsadc_data = { - .irq_ack = rk_tsadcv4_irq_ack, - .control = rk_tsadcv4_control, - .get_temp = rk_tsadcv4_get_temp, - .set_alarm_temp = rk_tsadcv3_alarm_temp, - .set_tshut_temp = rk_tsadcv3_tshut_temp, -- .set_tshut_mode = rk_tsadcv3_tshut_mode, -+ .set_tshut_mode = rk_tsadcv4_tshut_mode, - .table = { - .id = rk3588_code_table, - .length = ARRAY_SIZE(rk3588_code_table), - .data_mask = TSADCV4_DATA_MASK, - .mode = ADC_INCREMENT, -@@ -1342,14 +1377,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { - }, - { - .compatible = "rockchip,rk3288-tsadc", - .data = (void *)&rk3288_tsadc_data, - }, -- { -- .compatible = "rockchip,rk3308-tsadc", -- .data = (void *)&rk3308_tsadc_data, -- }, - { - .compatible = "rockchip,rk3328-tsadc", - .data = (void *)&rk3328_tsadc_data, - }, - { -@@ -1366,10 +1397,14 @@ static const struct of_device_id of_rockchip_thermal_match[] = { - }, - { - .compatible = "rockchip,rk3568-tsadc", - .data = (void *)&rk3568_tsadc_data, - }, -+ { -+ .compatible = "rockchip,rk3576-tsadc", -+ .data = (void *)&rk3576_tsadc_data, -+ }, - { - .compatible = "rockchip,rk3588-tsadc", - .data = (void *)&rk3588_tsadc_data, - }, - { /* end */ }, -@@ -1411,11 +1446,11 @@ static int rockchip_thermal_set_trips(struct thermal_zone_device *tz, int low, i - - dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n", - __func__, sensor->id, low, high); - - return tsadc->set_alarm_temp(&tsadc->table, -- sensor->id, thermal->regs, high); -+ sensor->id, thermal->regs, high + sensor->trim_temp); - } - - static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_temp) - { - struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz); -@@ -1423,18 +1458,118 @@ static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_te - const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; - int retval; - - retval = tsadc->get_temp(&tsadc->table, - sensor->id, thermal->regs, out_temp); -+ *out_temp -= sensor->trim_temp; -+ - return retval; - } - - static const struct thermal_zone_device_ops rockchip_of_thermal_ops = { - .get_temp = rockchip_thermal_get_temp, - .set_trips = rockchip_thermal_set_trips, - }; - -+/** -+ * rockchip_get_efuse_value - read an OTP cell from a device node -+ * @np: pointer to the device node with the nvmem-cells property -+ * @cell_name: name of cell that should be read -+ * @value: pointer to where the read value will be placed -+ * -+ * Return: Negative errno on failure, during which *value will not be touched, -+ * or 0 on success. -+ */ -+static int rockchip_get_efuse_value(struct device_node *np, const char *cell_name, -+ int *value) -+{ -+ struct nvmem_cell *cell; -+ int ret = 0; -+ size_t len; -+ u8 *buf; -+ int i; -+ -+ cell = of_nvmem_cell_get(np, cell_name); -+ if (IS_ERR(cell)) -+ return PTR_ERR(cell); -+ -+ buf = nvmem_cell_read(cell, &len); -+ -+ nvmem_cell_put(cell); -+ -+ if (IS_ERR(buf)) -+ return PTR_ERR(buf); -+ -+ if (len > sizeof(*value)) { -+ ret = -ERANGE; -+ goto exit; -+ } -+ -+ /* Copy with implicit endian conversion */ -+ *value = 0; -+ for (i = 0; i < len; i++) -+ *value |= (int) buf[i] << (8 * i); -+ -+exit: -+ kfree(buf); -+ return ret; -+} -+ -+static int rockchip_get_trim_configuration(struct device *dev, struct device_node *np, -+ struct rockchip_thermal_data *thermal) -+{ -+ const struct rockchip_tsadc_chip *tsadc = thermal->chip; -+ int trim_base = 0, trim_base_frac = 0, trim = 0; -+ int trim_code; -+ int ret; -+ -+ thermal->trim_base = 0; -+ thermal->trim_base_frac = 0; -+ thermal->trim = 0; -+ -+ if (!tsadc->get_trim_code) -+ return 0; -+ -+ ret = rockchip_get_efuse_value(np, "trim_base", &trim_base); -+ if (ret < 0) { -+ if (ret == -ENOENT) { -+ trim_base = 30; -+ dev_dbg(dev, "trim_base is absent, defaulting to 30\n"); -+ } else { -+ dev_err(dev, "failed reading nvmem value of trim_base: %pe\n", -+ ERR_PTR(ret)); -+ return ret; -+ } -+ } -+ ret = rockchip_get_efuse_value(np, "trim_base_frac", &trim_base_frac); -+ if (ret < 0) { -+ if (ret == -ENOENT) { -+ dev_dbg(dev, "trim_base_frac is absent, defaulting to 0\n"); -+ } else { -+ dev_err(dev, "failed reading nvmem value of trim_base_frac: %pe\n", -+ ERR_PTR(ret)); -+ return ret; -+ } -+ } -+ thermal->trim_base = trim_base; -+ thermal->trim_base_frac = trim_base_frac; -+ -+ /* -+ * If the tsadc node contains the trim property, then it is used in the -+ * absence of per-channel trim values -+ */ -+ if (!rockchip_get_efuse_value(np, "trim", &trim)) -+ thermal->trim = trim; -+ if (trim) { -+ trim_code = tsadc->get_trim_code(&tsadc->table, trim, -+ trim_base, trim_base_frac); -+ thermal->trim_temp = thermal->chip->trim_slope * trim_code; -+ } -+ -+ return 0; -+} -+ - static int rockchip_configure_from_dt(struct device *dev, - struct device_node *np, - struct rockchip_thermal_data *thermal) - { - u32 shut_temp, tshut_mode, tshut_polarity; -@@ -1491,37 +1626,66 @@ static int rockchip_configure_from_dt(struct device *dev, - */ - thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); - if (IS_ERR(thermal->grf)) - dev_warn(dev, "Missing rockchip,grf property\n"); - -+ rockchip_get_trim_configuration(dev, np, thermal); -+ - return 0; - } - - static int - rockchip_thermal_register_sensor(struct platform_device *pdev, - struct rockchip_thermal_data *thermal, - struct rockchip_thermal_sensor *sensor, - int id) - { - const struct rockchip_tsadc_chip *tsadc = thermal->chip; -+ struct device *dev = &pdev->dev; -+ int trim = thermal->trim; -+ int trim_code, tshut_temp; -+ int trim_temp = 0; - int error; - -+ if (thermal->trim_temp) -+ trim_temp = thermal->trim_temp; -+ -+ if (tsadc->get_trim_code && sensor->of_node) { -+ error = rockchip_get_efuse_value(sensor->of_node, "trim", &trim); -+ if (error < 0 && error != -ENOENT) { -+ dev_err(dev, "failed reading trim of sensor %d: %pe\n", -+ id, ERR_PTR(error)); -+ return error; -+ } -+ if (trim) { -+ trim_code = tsadc->get_trim_code(&tsadc->table, trim, -+ thermal->trim_base, -+ thermal->trim_base_frac); -+ trim_temp = thermal->chip->trim_slope * trim_code; -+ } -+ } -+ -+ sensor->trim_temp = trim_temp; -+ -+ dev_dbg(dev, "trim of sensor %d is %d\n", id, sensor->trim_temp); -+ -+ tshut_temp = min(thermal->tshut_temp + sensor->trim_temp, RK_MAX_TEMP); -+ - tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); - -- error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, -- thermal->tshut_temp); -+ error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, tshut_temp); - if (error) -- dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n", -- __func__, thermal->tshut_temp, error); -+ dev_err(dev, "%s: invalid tshut=%d, error=%d\n", -+ __func__, tshut_temp, error); - - sensor->thermal = thermal; - sensor->id = id; -- sensor->tzd = devm_thermal_of_zone_register(&pdev->dev, id, sensor, -+ sensor->tzd = devm_thermal_of_zone_register(dev, id, sensor, - &rockchip_of_thermal_ops); - if (IS_ERR(sensor->tzd)) { - error = PTR_ERR(sensor->tzd); -- dev_err(&pdev->dev, "failed to register sensor %d: %d\n", -+ dev_err(dev, "failed to register sensor %d: %d\n", - id, error); - return error; - } - - return 0; -@@ -1540,13 +1704,15 @@ static void rockchip_thermal_reset_controller(struct reset_control *reset) - - static int rockchip_thermal_probe(struct platform_device *pdev) - { - struct device_node *np = pdev->dev.of_node; - struct rockchip_thermal_data *thermal; -+ struct device_node *child; - int irq; - int i; - int error; -+ u32 chn; - - irq = platform_get_irq(pdev, 0); - if (irq < 0) - return -EINVAL; - -@@ -1593,10 +1759,22 @@ static int rockchip_thermal_probe(struct platform_device *pdev) - "failed to parse device tree data\n"); - - thermal->chip->initialize(thermal->grf, thermal->regs, - thermal->tshut_polarity); - -+ for_each_available_child_of_node(np, child) { -+ if (!of_property_read_u32(child, "reg", &chn)) { -+ if (chn < thermal->chip->chn_num) -+ thermal->sensors[chn].of_node = child; -+ else -+ dev_warn(&pdev->dev, -+ "sensor address (%d) too large, ignoring its trim\n", -+ chn); -+ } -+ -+ } -+ - for (i = 0; i < thermal->chip->chn_num; i++) { - error = rockchip_thermal_register_sensor(pdev, thermal, - &thermal->sensors[i], - thermal->chip->chn_offset + i); - if (error) -@@ -1662,12 +1840,15 @@ static int __maybe_unused rockchip_thermal_suspend(struct device *dev) - } - - static int __maybe_unused rockchip_thermal_resume(struct device *dev) - { - struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); -- int i; -+ const struct rockchip_tsadc_chip *tsadc = thermal->chip; -+ struct rockchip_thermal_sensor *sensor; -+ int tshut_temp; - int error; -+ int i; - - error = clk_enable(thermal->clk); - if (error) - return error; - -@@ -1677,25 +1858,27 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev) - return error; - } - - rockchip_thermal_reset_controller(thermal->reset); - -- thermal->chip->initialize(thermal->grf, thermal->regs, -- thermal->tshut_polarity); -+ tsadc->initialize(thermal->grf, thermal->regs, thermal->tshut_polarity); - - for (i = 0; i < thermal->chip->chn_num; i++) { -- int id = thermal->sensors[i].id; -+ sensor = &thermal->sensors[i]; -+ -+ tshut_temp = min(thermal->tshut_temp + sensor->trim_temp, -+ RK_MAX_TEMP); - -- thermal->chip->set_tshut_mode(id, thermal->regs, -+ tsadc->set_tshut_mode(sensor->id, thermal->regs, - thermal->tshut_mode); - -- error = thermal->chip->set_tshut_temp(&thermal->chip->table, -- id, thermal->regs, -- thermal->tshut_temp); -+ error = tsadc->set_tshut_temp(&thermal->chip->table, -+ sensor->id, thermal->regs, -+ tshut_temp); - if (error) - dev_err(dev, "%s: invalid tshut=%d, error=%d\n", -- __func__, thermal->tshut_temp, error); -+ __func__, tshut_temp, error); - } - - thermal->chip->control(thermal->regs, true); - - for (i = 0; i < thermal->chip->chn_num; i++) --- -Armbian - diff --git a/patch/kernel/archive/rockchip64-6.16/0000.patching_config.yaml b/patch/kernel/archive/rockchip64-6.17/0000.patching_config.yaml similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/0000.patching_config.yaml rename to patch/kernel/archive/rockchip64-6.17/0000.patching_config.yaml diff --git a/patch/kernel/archive/rockchip64-6.16/add-board-helios64.patch b/patch/kernel/archive/rockchip64-6.17/add-board-helios64.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/add-board-helios64.patch rename to patch/kernel/archive/rockchip64-6.17/add-board-helios64.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-firefly-rk3399-dts.patch b/patch/kernel/archive/rockchip64-6.17/board-firefly-rk3399-dts.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-firefly-rk3399-dts.patch rename to patch/kernel/archive/rockchip64-6.17/board-firefly-rk3399-dts.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-helios64-dts-fix-stability-issues.patch b/patch/kernel/archive/rockchip64-6.17/board-helios64-dts-fix-stability-issues.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-helios64-dts-fix-stability-issues.patch rename to patch/kernel/archive/rockchip64-6.17/board-helios64-dts-fix-stability-issues.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-helios64-remove-pcie-ep-gpios.patch b/patch/kernel/archive/rockchip64-6.17/board-helios64-remove-pcie-ep-gpios.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-helios64-remove-pcie-ep-gpios.patch rename to patch/kernel/archive/rockchip64-6.17/board-helios64-remove-pcie-ep-gpios.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-nanopc-t4-add-typec-dp.patch b/patch/kernel/archive/rockchip64-6.17/board-nanopc-t4-add-typec-dp.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-nanopc-t4-add-typec-dp.patch rename to patch/kernel/archive/rockchip64-6.17/board-nanopc-t4-add-typec-dp.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-nanopi-m4v2-dts-add-sound-card.patch b/patch/kernel/archive/rockchip64-6.17/board-nanopi-m4v2-dts-add-sound-card.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-nanopi-m4v2-dts-add-sound-card.patch rename to patch/kernel/archive/rockchip64-6.17/board-nanopi-m4v2-dts-add-sound-card.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-nanopi-r2c-plus.patch b/patch/kernel/archive/rockchip64-6.17/board-nanopi-r2c-plus.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-nanopi-r2c-plus.patch rename to patch/kernel/archive/rockchip64-6.17/board-nanopi-r2c-plus.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-nanopi-r2s.patch b/patch/kernel/archive/rockchip64-6.17/board-nanopi-r2s.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-nanopi-r2s.patch rename to patch/kernel/archive/rockchip64-6.17/board-nanopi-r2s.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-nanopi-r3s-fix-leds.patch b/patch/kernel/archive/rockchip64-6.17/board-nanopi-r3s-fix-leds.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-nanopi-r3s-fix-leds.patch rename to patch/kernel/archive/rockchip64-6.17/board-nanopi-r3s-fix-leds.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-nanopi-r4s-pwmfan.patch b/patch/kernel/archive/rockchip64-6.17/board-nanopi-r4s-pwmfan.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-nanopi-r4s-pwmfan.patch rename to patch/kernel/archive/rockchip64-6.17/board-nanopi-r4s-pwmfan.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-odroidm1-add-nodes-for-i2c-pwm-uart-spi.patch b/patch/kernel/archive/rockchip64-6.17/board-odroidm1-add-nodes-for-i2c-pwm-uart-spi.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-odroidm1-add-nodes-for-i2c-pwm-uart-spi.patch rename to patch/kernel/archive/rockchip64-6.17/board-odroidm1-add-nodes-for-i2c-pwm-uart-spi.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-odroidm2-fix-for-ethernet.patch b/patch/kernel/archive/rockchip64-6.17/board-odroidm2-fix-for-ethernet.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-odroidm2-fix-for-ethernet.patch rename to patch/kernel/archive/rockchip64-6.17/board-odroidm2-fix-for-ethernet.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-orangepi-r1-plus.patch b/patch/kernel/archive/rockchip64-6.17/board-orangepi-r1-plus.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-orangepi-r1-plus.patch rename to patch/kernel/archive/rockchip64-6.17/board-orangepi-r1-plus.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-orangepi-rk3399-pcie.patch b/patch/kernel/archive/rockchip64-6.17/board-orangepi-rk3399-pcie.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-orangepi-rk3399-pcie.patch rename to patch/kernel/archive/rockchip64-6.17/board-orangepi-rk3399-pcie.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-orangepi3b-add-uwe5622-wifi-bt-nodes.patch b/patch/kernel/archive/rockchip64-6.17/board-orangepi3b-add-uwe5622-wifi-bt-nodes.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-orangepi3b-add-uwe5622-wifi-bt-nodes.patch rename to patch/kernel/archive/rockchip64-6.17/board-orangepi3b-add-uwe5622-wifi-bt-nodes.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-pbp-add-dp-alt-mode.patch b/patch/kernel/archive/rockchip64-6.17/board-pbp-add-dp-alt-mode.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-pbp-add-dp-alt-mode.patch rename to patch/kernel/archive/rockchip64-6.17/board-pbp-add-dp-alt-mode.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-radxa-e25-sdmmc0-fix.patch b/patch/kernel/archive/rockchip64-6.17/board-radxa-e25-sdmmc0-fix.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-radxa-e25-sdmmc0-fix.patch rename to patch/kernel/archive/rockchip64-6.17/board-radxa-e25-sdmmc0-fix.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-radxa-e25-usb3-and-emmc-fix.patch b/patch/kernel/archive/rockchip64-6.17/board-radxa-e25-usb3-and-emmc-fix.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-radxa-e25-usb3-and-emmc-fix.patch rename to patch/kernel/archive/rockchip64-6.17/board-radxa-e25-usb3-and-emmc-fix.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rk3328-roc-cc-dts-enable-dmc.patch b/patch/kernel/archive/rockchip64-6.17/board-rk3328-roc-cc-dts-enable-dmc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rk3328-roc-cc-dts-enable-dmc.patch rename to patch/kernel/archive/rockchip64-6.17/board-rk3328-roc-cc-dts-enable-dmc.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rk3328-roc-cc-dts-ram-profile.patch b/patch/kernel/archive/rockchip64-6.17/board-rk3328-roc-cc-dts-ram-profile.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rk3328-roc-cc-dts-ram-profile.patch rename to patch/kernel/archive/rockchip64-6.17/board-rk3328-roc-cc-dts-ram-profile.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rk3328-roc-pc-dts-ram-profile.patch b/patch/kernel/archive/rockchip64-6.17/board-rk3328-roc-pc-dts-ram-profile.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rk3328-roc-pc-dts-ram-profile.patch rename to patch/kernel/archive/rockchip64-6.17/board-rk3328-roc-pc-dts-ram-profile.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rk3328-roc-pc.patch b/patch/kernel/archive/rockchip64-6.17/board-rk3328-roc-pc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rk3328-roc-pc.patch rename to patch/kernel/archive/rockchip64-6.17/board-rk3328-roc-pc.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rock3a-0001-emmc-sfc.patch b/patch/kernel/archive/rockchip64-6.17/board-rock3a-0001-emmc-sfc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rock3a-0001-emmc-sfc.patch rename to patch/kernel/archive/rockchip64-6.17/board-rock3a-0001-emmc-sfc.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rock3a-0002-usb3.patch b/patch/kernel/archive/rockchip64-6.17/board-rock3a-0002-usb3.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rock3a-0002-usb3.patch rename to patch/kernel/archive/rockchip64-6.17/board-rock3a-0002-usb3.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rock3a-0003-add-gpio-names.patch b/patch/kernel/archive/rockchip64-6.17/board-rock3a-0003-add-gpio-names.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rock3a-0003-add-gpio-names.patch rename to patch/kernel/archive/rockchip64-6.17/board-rock3a-0003-add-gpio-names.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rock5c-add-gpio-names.patch b/patch/kernel/archive/rockchip64-6.17/board-rock5c-add-gpio-names.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rock5c-add-gpio-names.patch rename to patch/kernel/archive/rockchip64-6.17/board-rock5c-add-gpio-names.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rock64-mail-supply.patch b/patch/kernel/archive/rockchip64-6.17/board-rock64-mail-supply.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rock64-mail-supply.patch rename to patch/kernel/archive/rockchip64-6.17/board-rock64-mail-supply.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rockpi3-enable-dmc.patch b/patch/kernel/archive/rockchip64-6.17/board-rockpi3-enable-dmc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rockpi3-enable-dmc.patch rename to patch/kernel/archive/rockchip64-6.17/board-rockpi3-enable-dmc.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rockpi4-0003-arm64-dts-pcie.patch b/patch/kernel/archive/rockchip64-6.17/board-rockpi4-0003-arm64-dts-pcie.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rockpi4-0003-arm64-dts-pcie.patch rename to patch/kernel/archive/rockchip64-6.17/board-rockpi4-0003-arm64-dts-pcie.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rockpis-dts-fixes.patch b/patch/kernel/archive/rockchip64-6.17/board-rockpis-dts-fixes.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rockpis-dts-fixes.patch rename to patch/kernel/archive/rockchip64-6.17/board-rockpis-dts-fixes.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch b/patch/kernel/archive/rockchip64-6.17/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch rename to patch/kernel/archive/rockchip64-6.17/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rockpro64-change-rx_delay-for-gmac.patch b/patch/kernel/archive/rockchip64-6.17/board-rockpro64-change-rx_delay-for-gmac.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rockpro64-change-rx_delay-for-gmac.patch rename to patch/kernel/archive/rockchip64-6.17/board-rockpro64-change-rx_delay-for-gmac.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rockpro64-fix-emmc.patch b/patch/kernel/archive/rockchip64-6.17/board-rockpro64-fix-emmc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rockpro64-fix-emmc.patch rename to patch/kernel/archive/rockchip64-6.17/board-rockpro64-fix-emmc.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rockpro64-fix-spi1-flash-speed.patch b/patch/kernel/archive/rockchip64-6.17/board-rockpro64-fix-spi1-flash-speed.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rockpro64-fix-spi1-flash-speed.patch rename to patch/kernel/archive/rockchip64-6.17/board-rockpro64-fix-spi1-flash-speed.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rockpro64-work-led-heartbeat.patch b/patch/kernel/archive/rockchip64-6.17/board-rockpro64-work-led-heartbeat.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rockpro64-work-led-heartbeat.patch rename to patch/kernel/archive/rockchip64-6.17/board-rockpro64-work-led-heartbeat.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-rocks0.patch b/patch/kernel/archive/rockchip64-6.17/board-rocks0.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-rocks0.patch rename to patch/kernel/archive/rockchip64-6.17/board-rocks0.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-station-m2.patch b/patch/kernel/archive/rockchip64-6.17/board-station-m2.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-station-m2.patch rename to patch/kernel/archive/rockchip64-6.17/board-station-m2.patch diff --git a/patch/kernel/archive/rockchip64-6.16/board-station-p2.patch b/patch/kernel/archive/rockchip64-6.17/board-station-p2.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/board-station-p2.patch rename to patch/kernel/archive/rockchip64-6.17/board-station-p2.patch diff --git a/patch/kernel/archive/rockchip64-6.16/drv-spi-spidev-remove-warnings.patch b/patch/kernel/archive/rockchip64-6.17/drv-spi-spidev-remove-warnings.patch similarity index 82% rename from patch/kernel/archive/rockchip64-6.16/drv-spi-spidev-remove-warnings.patch rename to patch/kernel/archive/rockchip64-6.17/drv-spi-spidev-remove-warnings.patch index d17cdadc1dd3..013ac0fce52a 100644 --- a/patch/kernel/archive/rockchip64-6.16/drv-spi-spidev-remove-warnings.patch +++ b/patch/kernel/archive/rockchip64-6.17/drv-spi-spidev-remove-warnings.patch @@ -9,7 +9,7 @@ Signed-off-by: John Doe 1 file changed, 2 insertions(+) diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c -index 111111111111..222222222222 100644 +index 5300c942a2a4..67e802d5419d 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -703,6 +703,7 @@ static const struct class spidev_class = { @@ -17,17 +17,17 @@ index 111111111111..222222222222 100644 */ static const struct spi_device_id spidev_spi_ids[] = { + { .name = "spi-dev" }, + { .name = /* abb */ "spi-sensor" }, { .name = /* cisco */ "spi-petra" }, { .name = /* dh */ "dhcom-board" }, - { .name = /* elgin */ "jg10309-01" }, -@@ -735,6 +736,7 @@ static int spidev_of_check(struct device *dev) +@@ -736,6 +737,7 @@ static int spidev_of_check(struct device *dev) } - + static const struct of_device_id spidev_dt_ids[] = { + { .compatible = "armbian,spi-dev", .data = &spidev_of_check }, + { .compatible = "abb,spi-sensor", .data = &spidev_of_check }, { .compatible = "cisco,spi-petra", .data = &spidev_of_check }, { .compatible = "dh,dhcom-board", .data = &spidev_of_check }, - { .compatible = "elgin,jg10309-01", .data = &spidev_of_check }, -- Armbian diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3308-sakurapi-rk3308b.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3308-sakurapi-rk3308b.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3308-sakurapi-rk3308b.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3308-sakurapi-rk3308b.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3318-box.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3318-box.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3318-box.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3318-box.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3328-heltec.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3328-heltec.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3328-heltec.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3328-heltec.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3328-mksklipad50.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3328-mksklipad50.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3328-mksklipad50.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3328-mksklipad50.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3328-mkspi.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3328-mkspi.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3328-mkspi.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3328-mkspi.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3328-nanopi-neo3-rev02.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3328-nanopi-neo3-rev02.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3328-nanopi-neo3-rev02.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3328-nanopi-neo3-rev02.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3328-nanopi-r2-rev00.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3328-nanopi-r2-rev00.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3328-nanopi-r2-rev00.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3328-nanopi-r2-rev00.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3328-nanopi-r2-rev06.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3328-nanopi-r2-rev06.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3328-nanopi-r2-rev06.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3328-nanopi-r2-rev06.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3328-nanopi-r2-rev20.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3328-nanopi-r2-rev20.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3328-nanopi-r2-rev20.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3328-nanopi-r2-rev20.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3328-nanopi-r2s-plus-rev00.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3328-nanopi-r2s-plus-rev00.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3328-nanopi-r2s-plus-rev00.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3328-nanopi-r2s-plus-rev00.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3328-z28pro.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3328-z28pro.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3328-z28pro.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3328-z28pro.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3399-am40.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3399-am40.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3399-am40.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3399-am40.dts diff --git a/patch/kernel/archive/rockchip64-6.16/dt/rk3399-fine3399.dts b/patch/kernel/archive/rockchip64-6.17/dt/rk3399-fine3399.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/dt/rk3399-fine3399.dts rename to patch/kernel/archive/rockchip64-6.17/dt/rk3399-fine3399.dts diff --git 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patch/kernel/archive/rockchip64-6.16/general-possibility-of-disabling-rk808-rtc.patch rename to patch/kernel/archive/rockchip64-6.17/general-possibility-of-disabling-rk808-rtc.patch diff --git a/patch/kernel/archive/rockchip64-6.16/general-rk3328-dtsi-trb-ent-quirk.patch b/patch/kernel/archive/rockchip64-6.17/general-rk3328-dtsi-trb-ent-quirk.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/general-rk3328-dtsi-trb-ent-quirk.patch rename to patch/kernel/archive/rockchip64-6.17/general-rk3328-dtsi-trb-ent-quirk.patch diff --git a/patch/kernel/archive/rockchip64-6.16/general-rk808-configurable-switch-voltage-steps.patch b/patch/kernel/archive/rockchip64-6.17/general-rk808-configurable-switch-voltage-steps.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/general-rk808-configurable-switch-voltage-steps.patch rename to patch/kernel/archive/rockchip64-6.17/general-rk808-configurable-switch-voltage-steps.patch diff --git a/patch/kernel/archive/rockchip64-6.16/general-rockchip-overlays.patch b/patch/kernel/archive/rockchip64-6.17/general-rockchip-overlays.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/general-rockchip-overlays.patch rename to patch/kernel/archive/rockchip64-6.17/general-rockchip-overlays.patch diff --git a/patch/kernel/archive/rockchip64-6.16/general-rt5651-add-mclk.patch b/patch/kernel/archive/rockchip64-6.17/general-rt5651-add-mclk.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/general-rt5651-add-mclk.patch rename to patch/kernel/archive/rockchip64-6.17/general-rt5651-add-mclk.patch diff --git a/patch/kernel/archive/rockchip64-6.16/general-st7796-driver.patch b/patch/kernel/archive/rockchip64-6.17/general-st7796-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/general-st7796-driver.patch rename to patch/kernel/archive/rockchip64-6.17/general-st7796-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.16/general-v4l2-iep-driver.patch b/patch/kernel/archive/rockchip64-6.17/general-v4l2-iep-driver.patch similarity index 99% rename from patch/kernel/archive/rockchip64-6.16/general-v4l2-iep-driver.patch rename to patch/kernel/archive/rockchip64-6.17/general-v4l2-iep-driver.patch index 53ff2d5090b1..4924c90b6e30 100644 --- a/patch/kernel/archive/rockchip64-6.16/general-v4l2-iep-driver.patch +++ b/patch/kernel/archive/rockchip64-6.17/general-v4l2-iep-driver.patch @@ -246,22 +246,22 @@ index 111111111111..222222222222 100644 status = "disabled"; }; diff --git a/drivers/media/platform/rockchip/Kconfig b/drivers/media/platform/rockchip/Kconfig -index 111111111111..222222222222 100644 +index 9bbeec4996aa..9fcf52f864b4 100644 --- a/drivers/media/platform/rockchip/Kconfig +++ b/drivers/media/platform/rockchip/Kconfig -@@ -4,3 +4,4 @@ comment "Rockchip media platform drivers" - +@@ -5,3 +5,4 @@ comment "Rockchip media platform drivers" source "drivers/media/platform/rockchip/rga/Kconfig" source "drivers/media/platform/rockchip/rkisp1/Kconfig" + source "drivers/media/platform/rockchip/rkvdec/Kconfig" +source "drivers/media/platform/rockchip/iep/Kconfig" diff --git a/drivers/media/platform/rockchip/Makefile b/drivers/media/platform/rockchip/Makefile -index 111111111111..222222222222 100644 +index 286dc5c53f7e..85293a5fec41 100644 --- a/drivers/media/platform/rockchip/Makefile +++ b/drivers/media/platform/rockchip/Makefile -@@ -1,3 +1,4 @@ - # SPDX-License-Identifier: GPL-2.0-only +@@ -2,3 +2,4 @@ obj-y += rga/ obj-y += rkisp1/ + obj-y += rkvdec/ +obj-y += iep/ diff --git a/drivers/media/platform/rockchip/iep/Kconfig b/drivers/media/platform/rockchip/iep/Kconfig new file mode 100644 diff --git a/patch/kernel/archive/rockchip64-6.16/general-workaround-broadcom-bt-serdev.patch b/patch/kernel/archive/rockchip64-6.17/general-workaround-broadcom-bt-serdev.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/general-workaround-broadcom-bt-serdev.patch rename to patch/kernel/archive/rockchip64-6.17/general-workaround-broadcom-bt-serdev.patch diff --git a/patch/kernel/archive/rockchip64-6.16/kernel-6.8-tools-cgroup-makefile.patch b/patch/kernel/archive/rockchip64-6.17/kernel-6.8-tools-cgroup-makefile.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/kernel-6.8-tools-cgroup-makefile.patch rename to patch/kernel/archive/rockchip64-6.17/kernel-6.8-tools-cgroup-makefile.patch diff --git a/patch/kernel/archive/rockchip64-6.16/media-0002-media-rkvdec-remove-vb2_is_busy-check-in-rkvdec_s_ct.patch b/patch/kernel/archive/rockchip64-6.17/media-0002-media-rkvdec-remove-vb2_is_busy-check-in-rkvdec_s_ct.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/media-0002-media-rkvdec-remove-vb2_is_busy-check-in-rkvdec_s_ct.patch rename to patch/kernel/archive/rockchip64-6.17/media-0002-media-rkvdec-remove-vb2_is_busy-check-in-rkvdec_s_ct.patch diff --git a/patch/kernel/archive/rockchip64-6.16/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch b/patch/kernel/archive/rockchip64-6.17/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch rename to patch/kernel/archive/rockchip64-6.17/media-0002-v4l2-core-Initialize-h264-frame_mbs_only_flag-.patch diff --git a/patch/kernel/archive/rockchip64-6.16/media-0003-rk3568-disable-hantro-h264.patch b/patch/kernel/archive/rockchip64-6.17/media-0003-rk3568-disable-hantro-h264.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/media-0003-rk3568-disable-hantro-h264.patch rename to patch/kernel/archive/rockchip64-6.17/media-0003-rk3568-disable-hantro-h264.patch diff --git a/patch/kernel/archive/rockchip64-6.17/media-rkvdec-from-kernel-mailing-lists.patch b/patch/kernel/archive/rockchip64-6.17/media-rkvdec-from-kernel-mailing-lists.patch new file mode 100644 index 000000000000..d580987c5642 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.17/media-rkvdec-from-kernel-mailing-lists.patch @@ -0,0 +1,3336 @@ +From 1e4384c38f0651af63b89609c5dedfba33e21e1b Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Fri, 5 Sep 2025 16:19:19 +0000 +Subject: [PATCH 044/108] FROMLIST(v3): media: rkvdec: Add HEVC backend + +The Rockchip VDEC supports the HEVC codec with the Main and Main10 +Profile up to Level 5.1 High tier: 4096x2304@60 fps. + +Add the backend for HEVC format to the decoder. + +Signed-off-by: Alex Bee +Signed-off-by: Nicolas Dufresne +Signed-off-by: Sebastian Fricke +Tested-by: Nicolas Dufresne +Reviewed-by: Nicolas Dufresne +Signed-off-by: Jonas Karlman +--- + .../media/platform/rockchip/rkvdec/Makefile | 2 +- + .../rockchip/rkvdec/rkvdec-hevc-data.c | 1848 +++++++++++++++++ + .../platform/rockchip/rkvdec/rkvdec-hevc.c | 817 ++++++++ + .../platform/rockchip/rkvdec/rkvdec-regs.h | 2 + + .../media/platform/rockchip/rkvdec/rkvdec.c | 76 + + .../media/platform/rockchip/rkvdec/rkvdec.h | 1 + + 6 files changed, 2745 insertions(+), 1 deletion(-) + create mode 100644 drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c + create mode 100644 drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c + +diff --git a/drivers/media/platform/rockchip/rkvdec/Makefile b/drivers/media/platform/rockchip/rkvdec/Makefile +index cb86b429cfaa..a77122641d14 100644 +--- a/drivers/media/platform/rockchip/rkvdec/Makefile ++++ b/drivers/media/platform/rockchip/rkvdec/Makefile +@@ -1,3 +1,3 @@ + obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o + +-rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o ++rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c +new file mode 100644 +index 000000000000..eac4ea604949 +--- /dev/null ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-data.c +@@ -0,0 +1,1848 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Rockchip Video Decoder driver ++ * ++ * Copyright (C) 2023 Collabora, Ltd. ++ * Sebastian Fricke ++ */ ++ ++#include ++ ++#define RKV_CABAC_TABLE_SIZE 27456 ++ ++/* ++ * This file is #include from rkvdec-hevc.c and not compiled. ++ */ ++static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = { ++ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, ++ 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40, ++ 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60, ++ 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50, ++ 0x48, 0x68, 0x60, 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, ++ 0x68, 0x68, 0x50, 0x48, 0x68, 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60, ++ 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, ++ 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07, ++ 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40, ++ 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37, ++ 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x47, 0x57, ++ 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, 0x47, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, 0x57, 0x5e, ++ 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, 0x4f, ++ 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f, ++ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, ++ 0x66, 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47, ++ 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, ++ 0x07, 0x57, 0x4f, 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10, ++ 0x47, 0x67, 0x40, 0x40, 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27, ++ 0x4e, 0x47, 0x47, 0x00, 0x0f, 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07, ++ 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64, 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x66, 0x57, 0x5d, 0x00, 0x1e, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5e, 0x5e, 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, ++ 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x5e, 0x5e, 0x4e, 0x56, 0x4f, 0x07, ++ 0x56, 0x66, 0x4f, 0x56, 0x66, 0x67, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x64, 0x45, 0x48, 0x20, ++ 0x57, 0x66, 0x66, 0x56, 0x5e, 0x5e, 0x5d, 0x4e, 0x4e, 0x4e, 0x46, 0x56, 0x57, 0x36, 0x07, ++ 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x46, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f, 0x47, ++ 0x1e, 0x1e, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x66, 0x10, 0x47, 0x66, 0x40, 0x40, ++ 0x4f, 0x4d, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x03, 0x27, 0x4d, 0x47, 0x46, 0x01, ++ 0x0f, 0x4f, 0x36, 0x1f, 0x1e, 0x4f, 0x34, 0x01, 0x26, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x0d, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0e, 0x40, ++ 0x40, 0x40, 0x0e, 0x62, 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x07, 0x00, 0x00, 0x65, 0x57, 0x5c, 0x00, 0x1e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x47, 0x47, 0x5d, 0x5d, 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, 0x65, 0x67, 0x66, ++ 0x65, 0x63, 0x4d, 0x46, 0x62, 0x5d, 0x5d, 0x4e, 0x56, 0x4f, 0x07, 0x56, 0x66, 0x4f, 0x55, ++ 0x65, 0x67, 0x66, 0x65, 0x63, 0x4d, 0x46, 0x62, 0x44, 0x48, 0x20, 0x57, 0x65, 0x65, 0x56, ++ 0x5d, 0x5d, 0x5c, 0x4e, 0x4d, 0x4e, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, ++ 0x36, 0x07, 0x56, 0x45, 0x56, 0x57, 0x36, 0x07, 0x56, 0x4f, 0x47, 0x1e, 0x1e, 0x0f, 0x10, ++ 0x0f, 0x10, 0x07, 0x10, 0x47, 0x65, 0x10, 0x47, 0x65, 0x40, 0x40, 0x4f, 0x4c, 0x08, 0x00, ++ 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x04, 0x27, 0x4c, 0x47, 0x45, 0x01, 0x0f, 0x4f, 0x36, 0x1f, ++ 0x1e, 0x4f, 0x33, 0x01, 0x25, 0x00, 0x07, 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x0c, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0d, 0x40, 0x40, 0x40, 0x0d, 0x60, ++ 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, ++ 0x64, 0x56, 0x5b, 0x01, 0x1d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5c, 0x5c, ++ 0x4d, 0x55, 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, 0x61, 0x4c, 0x45, ++ 0x60, 0x5c, 0x5c, 0x4d, 0x55, 0x4e, 0x07, 0x55, 0x65, 0x4e, 0x54, 0x64, 0x66, 0x65, 0x64, ++ 0x61, 0x4c, 0x45, 0x60, 0x43, 0x49, 0x21, 0x56, 0x64, 0x64, 0x55, 0x5c, 0x5c, 0x5b, 0x4d, ++ 0x4c, 0x4d, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x44, 0x55, 0x56, 0x35, 0x07, 0x55, 0x44, ++ 0x55, 0x56, 0x35, 0x07, 0x55, 0x4e, 0x46, 0x1d, 0x1d, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, ++ 0x46, 0x64, 0x11, 0x46, 0x64, 0x40, 0x40, 0x4e, 0x4b, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, ++ 0x07, 0x06, 0x27, 0x4b, 0x46, 0x44, 0x02, 0x0f, 0x4e, 0x35, 0x1e, 0x1d, 0x4e, 0x31, 0x02, ++ 0x24, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0b, 0x46, 0x56, 0x58, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5e, 0x46, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x63, 0x56, 0x59, 0x01, ++ 0x1c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x46, 0x46, 0x5b, 0x5b, 0x4c, 0x54, 0x4e, 0x07, ++ 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e, 0x5b, 0x5b, 0x4c, ++ 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x53, 0x63, 0x66, 0x64, 0x63, 0x60, 0x4b, 0x44, 0x5e, ++ 0x41, 0x49, 0x21, 0x56, 0x63, 0x63, 0x54, 0x5b, 0x5b, 0x59, 0x4c, 0x4b, 0x4c, 0x43, 0x54, ++ 0x56, 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, 0x54, 0x43, 0x54, 0x56, 0x34, 0x07, ++ 0x54, 0x4e, 0x46, 0x1c, 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x63, 0x11, 0x46, ++ 0x63, 0x40, 0x40, 0x4e, 0x49, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x07, 0x27, 0x49, ++ 0x46, 0x43, 0x03, 0x0f, 0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x30, 0x03, 0x23, 0x01, 0x07, 0x11, ++ 0x16, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0a, 0x46, 0x56, 0x58, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x0c, 0x40, 0x40, 0x40, 0x0c, 0x5c, 0x46, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x07, 0x01, 0x01, 0x62, 0x56, 0x58, 0x01, 0x1c, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x46, 0x46, 0x5a, 0x5a, 0x4c, 0x54, 0x4e, 0x07, 0x54, 0x64, 0x4e, 0x52, ++ 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c, 0x5a, 0x5a, 0x4c, 0x54, 0x4e, 0x07, 0x54, ++ 0x64, 0x4e, 0x52, 0x62, 0x66, 0x64, 0x62, 0x5e, 0x4a, 0x44, 0x5c, 0x40, 0x49, 0x21, 0x56, ++ 0x62, 0x62, 0x54, 0x5a, 0x5a, 0x58, 0x4c, 0x4a, 0x4c, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, ++ 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x42, 0x54, 0x56, 0x34, 0x07, 0x54, 0x4e, 0x46, 0x1c, ++ 0x1c, 0x0f, 0x11, 0x0f, 0x11, 0x07, 0x11, 0x46, 0x62, 0x11, 0x46, 0x62, 0x40, 0x40, 0x4e, ++ 0x48, 0x09, 0x01, 0x4e, 0x0f, 0x01, 0x46, 0x07, 0x09, 0x27, 0x48, 0x46, 0x42, 0x03, 0x0f, ++ 0x4e, 0x34, 0x1e, 0x1c, 0x4e, 0x2e, 0x03, 0x22, 0x01, 0x07, 0x11, 0x16, 0x0f, 0x0f, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x07, 0x09, 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0b, 0x40, 0x40, ++ 0x40, 0x0b, 0x5a, 0x45, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x07, 0x02, 0x02, 0x61, 0x55, 0x57, 0x02, 0x1b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, ++ 0x45, 0x59, 0x59, 0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x51, 0x61, 0x65, 0x63, 0x61, ++ 0x5d, 0x49, 0x43, 0x5a, 0x59, 0x59, 0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x51, 0x61, ++ 0x65, 0x63, 0x61, 0x5d, 0x49, 0x43, 0x5a, 0x00, 0x4a, 0x22, 0x55, 0x61, 0x61, 0x53, 0x59, ++ 0x59, 0x57, 0x4b, 0x49, 0x4b, 0x41, 0x53, 0x55, 0x33, 0x07, 0x53, 0x41, 0x53, 0x55, 0x33, ++ 0x07, 0x53, 0x41, 0x53, 0x55, 0x33, 0x07, 0x53, 0x4d, 0x45, 0x1b, 0x1b, 0x0f, 0x12, 0x0f, ++ 0x12, 0x07, 0x12, 0x45, 0x61, 0x12, 0x45, 0x61, 0x40, 0x40, 0x4d, 0x47, 0x0a, 0x02, 0x4d, ++ 0x0f, 0x02, 0x45, 0x07, 0x0a, 0x27, 0x47, 0x45, 0x41, 0x04, 0x0f, 0x4d, 0x33, 0x1d, 0x1b, ++ 0x4d, 0x2d, 0x04, 0x21, 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x08, ++ 0x45, 0x55, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, 0x40, 0x40, 0x40, 0x0a, 0x59, 0x45, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x60, ++ 0x55, 0x56, 0x02, 0x1a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x58, 0x58, 0x4b, ++ 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x50, 0x60, 0x65, 0x63, 0x60, 0x5b, 0x48, 0x43, 0x59, ++ 0x58, 0x58, 0x4b, 0x53, 0x4d, 0x07, 0x53, 0x63, 0x4d, 0x50, 0x60, 0x65, 0x63, 0x60, 0x5b, ++ 0x48, 0x43, 0x59, 0x01, 0x4a, 0x22, 0x55, 0x60, 0x60, 0x53, 0x58, 0x58, 0x56, 0x4b, 0x48, ++ 0x4b, 0x40, 0x53, 0x55, 0x32, 0x07, 0x53, 0x40, 0x53, 0x55, 0x32, 0x07, 0x53, 0x40, 0x53, ++ 0x55, 0x32, 0x07, 0x53, 0x4d, 0x45, 0x1a, 0x1a, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, ++ 0x60, 0x12, 0x45, 0x60, 0x40, 0x40, 0x4d, 0x46, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, ++ 0x0c, 0x27, 0x46, 0x45, 0x40, 0x04, 0x0f, 0x4d, 0x32, 0x1d, 0x1a, 0x4d, 0x2b, 0x04, 0x20, ++ 0x02, 0x07, 0x12, 0x15, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x07, 0x45, 0x55, 0x58, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x0a, 0x40, 0x40, 0x40, 0x0a, 0x57, 0x45, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x02, 0x02, 0x5f, 0x55, 0x54, 0x02, 0x1a, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x45, 0x57, 0x57, 0x4a, 0x52, 0x4d, 0x07, 0x52, ++ 0x62, 0x4d, 0x4f, 0x5f, 0x65, 0x62, 0x5f, 0x59, 0x47, 0x42, 0x57, 0x57, 0x57, 0x4a, 0x52, ++ 0x4d, 0x07, 0x52, 0x62, 0x4d, 0x4f, 0x5f, 0x65, 0x62, 0x5f, 0x59, 0x47, 0x42, 0x57, 0x03, ++ 0x4a, 0x22, 0x55, 0x5f, 0x5f, 0x52, 0x57, 0x57, 0x54, 0x4a, 0x47, 0x4a, 0x00, 0x52, 0x55, ++ 0x32, 0x07, 0x52, 0x00, 0x52, 0x55, 0x32, 0x07, 0x52, 0x00, 0x52, 0x55, 0x32, 0x07, 0x52, ++ 0x4d, 0x45, 0x1a, 0x1a, 0x0f, 0x12, 0x0f, 0x12, 0x07, 0x12, 0x45, 0x5f, 0x12, 0x45, 0x5f, ++ 0x40, 0x40, 0x4d, 0x44, 0x0a, 0x02, 0x4d, 0x0f, 0x02, 0x45, 0x07, 0x0e, 0x27, 0x44, 0x45, ++ 0x00, 0x05, 0x0f, 0x4d, 0x32, 0x1d, 0x1a, 0x4d, 0x29, 0x05, 0x1f, 0x02, 0x07, 0x12, 0x15, ++ 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x06, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x09, 0x40, 0x40, 0x40, 0x09, 0x55, 0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5e, 0x54, 0x53, 0x03, 0x19, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x44, 0x44, 0x56, 0x56, 0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4e, 0x5e, ++ 0x64, 0x61, 0x5e, 0x58, 0x46, 0x41, 0x55, 0x56, 0x56, 0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, ++ 0x4c, 0x4e, 0x5e, 0x64, 0x61, 0x5e, 0x58, 0x46, 0x41, 0x55, 0x04, 0x4b, 0x23, 0x54, 0x5e, ++ 0x5e, 0x51, 0x56, 0x56, 0x53, 0x49, 0x46, 0x49, 0x01, 0x51, 0x54, 0x31, 0x07, 0x51, 0x01, ++ 0x51, 0x54, 0x31, 0x07, 0x51, 0x01, 0x51, 0x54, 0x31, 0x07, 0x51, 0x4c, 0x44, 0x19, 0x19, ++ 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5e, 0x13, 0x44, 0x5e, 0x40, 0x40, 0x4c, 0x43, ++ 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x0f, 0x27, 0x43, 0x44, 0x01, 0x06, 0x0f, 0x4c, ++ 0x31, 0x1c, 0x19, 0x4c, 0x28, 0x06, 0x1e, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x07, 0x05, 0x44, 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x09, 0x40, 0x40, 0x40, ++ 0x09, 0x53, 0x44, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, ++ 0x03, 0x03, 0x5d, 0x54, 0x52, 0x03, 0x19, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, ++ 0x55, 0x55, 0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4d, 0x5d, 0x64, 0x61, 0x5d, 0x56, ++ 0x45, 0x41, 0x53, 0x55, 0x55, 0x49, 0x51, 0x4c, 0x07, 0x51, 0x61, 0x4c, 0x4d, 0x5d, 0x64, ++ 0x61, 0x5d, 0x56, 0x45, 0x41, 0x53, 0x05, 0x4b, 0x23, 0x54, 0x5d, 0x5d, 0x51, 0x55, 0x55, ++ 0x52, 0x49, 0x45, 0x49, 0x02, 0x51, 0x54, 0x31, 0x07, 0x51, 0x02, 0x51, 0x54, 0x31, 0x07, ++ 0x51, 0x02, 0x51, 0x54, 0x31, 0x07, 0x51, 0x4c, 0x44, 0x19, 0x19, 0x0f, 0x13, 0x0f, 0x13, ++ 0x07, 0x13, 0x44, 0x5d, 0x13, 0x44, 0x5d, 0x40, 0x40, 0x4c, 0x42, 0x0b, 0x03, 0x4c, 0x0f, ++ 0x03, 0x44, 0x07, 0x11, 0x27, 0x42, 0x44, 0x02, 0x06, 0x0f, 0x4c, 0x31, 0x1c, 0x19, 0x4c, ++ 0x26, 0x06, 0x1d, 0x03, 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x04, 0x44, ++ 0x54, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x08, 0x40, 0x40, 0x40, 0x08, 0x51, 0x44, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x03, 0x03, 0x5c, 0x54, ++ 0x51, 0x03, 0x18, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x44, 0x54, 0x54, 0x48, 0x50, ++ 0x4c, 0x07, 0x50, 0x60, 0x4c, 0x4c, 0x5c, 0x64, 0x60, 0x5c, 0x55, 0x44, 0x40, 0x51, 0x54, ++ 0x54, 0x48, 0x50, 0x4c, 0x07, 0x50, 0x60, 0x4c, 0x4c, 0x5c, 0x64, 0x60, 0x5c, 0x55, 0x44, ++ 0x40, 0x51, 0x06, 0x4b, 0x23, 0x54, 0x5c, 0x5c, 0x50, 0x54, 0x54, 0x51, 0x48, 0x44, 0x48, ++ 0x03, 0x50, 0x54, 0x30, 0x07, 0x50, 0x03, 0x50, 0x54, 0x30, 0x07, 0x50, 0x03, 0x50, 0x54, ++ 0x30, 0x07, 0x50, 0x4c, 0x44, 0x18, 0x18, 0x0f, 0x13, 0x0f, 0x13, 0x07, 0x13, 0x44, 0x5c, ++ 0x13, 0x44, 0x5c, 0x40, 0x40, 0x4c, 0x41, 0x0b, 0x03, 0x4c, 0x0f, 0x03, 0x44, 0x07, 0x12, ++ 0x27, 0x41, 0x44, 0x03, 0x07, 0x0f, 0x4c, 0x30, 0x1c, 0x18, 0x4c, 0x25, 0x07, 0x1c, 0x03, ++ 0x07, 0x13, 0x14, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x03, 0x43, 0x53, 0x58, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, 0x07, 0x4f, 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x5b, 0x53, 0x4f, 0x04, 0x17, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x53, 0x53, 0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, ++ 0x4b, 0x4b, 0x5b, 0x63, 0x5f, 0x5b, 0x53, 0x43, 0x00, 0x4f, 0x53, 0x53, 0x47, 0x4f, 0x4b, ++ 0x07, 0x4f, 0x5f, 0x4b, 0x4b, 0x5b, 0x63, 0x5f, 0x5b, 0x53, 0x43, 0x00, 0x4f, 0x08, 0x4c, ++ 0x24, 0x53, 0x5b, 0x5b, 0x4f, 0x53, 0x53, 0x4f, 0x47, 0x43, 0x47, 0x04, 0x4f, 0x53, 0x2f, ++ 0x07, 0x4f, 0x04, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x04, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x4b, ++ 0x43, 0x17, 0x17, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x5b, 0x14, 0x43, 0x5b, 0x40, ++ 0x40, 0x4b, 0x00, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x14, 0x27, 0x00, 0x43, 0x04, ++ 0x08, 0x0f, 0x4b, 0x2f, 0x1b, 0x17, 0x4b, 0x23, 0x08, 0x1b, 0x04, 0x07, 0x14, 0x13, 0x0f, ++ 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x07, 0x02, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, ++ 0x40, 0x40, 0x40, 0x07, 0x4d, 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x07, 0x04, 0x04, 0x5a, 0x53, 0x4e, 0x04, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x43, 0x43, 0x52, 0x52, 0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, 0x4b, 0x4a, 0x5a, 0x63, ++ 0x5f, 0x5a, 0x52, 0x42, 0x00, 0x4d, 0x52, 0x52, 0x47, 0x4f, 0x4b, 0x07, 0x4f, 0x5f, 0x4b, ++ 0x4a, 0x5a, 0x63, 0x5f, 0x5a, 0x52, 0x42, 0x00, 0x4d, 0x09, 0x4c, 0x24, 0x53, 0x5a, 0x5a, ++ 0x4f, 0x52, 0x52, 0x4e, 0x47, 0x42, 0x47, 0x05, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x05, 0x4f, ++ 0x53, 0x2f, 0x07, 0x4f, 0x05, 0x4f, 0x53, 0x2f, 0x07, 0x4f, 0x4b, 0x43, 0x17, 0x17, 0x0f, ++ 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x5a, 0x14, 0x43, 0x5a, 0x40, 0x40, 0x4b, 0x01, 0x0c, ++ 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x15, 0x27, 0x01, 0x43, 0x05, 0x08, 0x0f, 0x4b, 0x2f, ++ 0x1b, 0x17, 0x4b, 0x22, 0x08, 0x1a, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x01, 0x43, 0x53, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x40, 0x40, 0x40, 0x06, ++ 0x4b, 0x43, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, ++ 0x04, 0x59, 0x53, 0x4d, 0x04, 0x16, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x51, ++ 0x51, 0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x50, 0x41, ++ 0x01, 0x4b, 0x51, 0x51, 0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, ++ 0x59, 0x50, 0x41, 0x01, 0x4b, 0x0a, 0x4c, 0x24, 0x53, 0x59, 0x59, 0x4e, 0x51, 0x51, 0x4d, ++ 0x46, 0x41, 0x46, 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, ++ 0x06, 0x4e, 0x53, 0x2e, 0x07, 0x4e, 0x4b, 0x43, 0x16, 0x16, 0x0f, 0x14, 0x0f, 0x14, 0x07, ++ 0x14, 0x43, 0x59, 0x14, 0x43, 0x59, 0x40, 0x40, 0x4b, 0x02, 0x0c, 0x04, 0x4b, 0x0f, 0x04, ++ 0x43, 0x07, 0x17, 0x27, 0x02, 0x43, 0x06, 0x09, 0x0f, 0x4b, 0x2e, 0x1b, 0x16, 0x4b, 0x20, ++ 0x09, 0x19, 0x04, 0x07, 0x14, 0x13, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x43, 0x53, ++ 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x05, 0x4a, 0x43, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x04, 0x04, 0x59, 0x53, 0x4c, ++ 0x04, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x43, 0x51, 0x51, 0x46, 0x4e, 0x4b, ++ 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x4f, 0x41, 0x01, 0x4a, 0x51, 0x51, ++ 0x46, 0x4e, 0x4b, 0x07, 0x4e, 0x5e, 0x4b, 0x49, 0x59, 0x63, 0x5e, 0x59, 0x4f, 0x41, 0x01, ++ 0x4a, 0x0b, 0x4d, 0x24, 0x53, 0x59, 0x59, 0x4e, 0x51, 0x51, 0x4c, 0x46, 0x41, 0x46, 0x06, ++ 0x4e, 0x53, 0x2d, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2d, 0x07, 0x4e, 0x06, 0x4e, 0x53, 0x2d, ++ 0x07, 0x4e, 0x4b, 0x43, 0x15, 0x15, 0x0f, 0x14, 0x0f, 0x14, 0x07, 0x14, 0x43, 0x59, 0x14, ++ 0x43, 0x59, 0x40, 0x40, 0x4b, 0x03, 0x0c, 0x04, 0x4b, 0x0f, 0x04, 0x43, 0x07, 0x18, 0x27, ++ 0x03, 0x43, 0x06, 0x09, 0x0f, 0x4b, 0x2d, 0x1a, 0x15, 0x4b, 0x1e, 0x09, 0x18, 0x04, 0x07, ++ 0x14, 0x12, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x05, 0x48, 0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, 0x58, 0x52, 0x4a, 0x05, 0x15, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x50, 0x50, 0x45, 0x4d, 0x4a, 0x07, 0x4d, 0x5d, 0x4a, ++ 0x48, 0x58, 0x62, 0x5d, 0x58, 0x4d, 0x40, 0x02, 0x48, 0x50, 0x50, 0x45, 0x4d, 0x4a, 0x07, ++ 0x4d, 0x5d, 0x4a, 0x48, 0x58, 0x62, 0x5d, 0x58, 0x4d, 0x40, 0x02, 0x48, 0x0d, 0x4d, 0x25, ++ 0x52, 0x58, 0x58, 0x4d, 0x50, 0x50, 0x4a, 0x45, 0x40, 0x45, 0x07, 0x4d, 0x52, 0x2d, 0x07, ++ 0x4d, 0x07, 0x4d, 0x52, 0x2d, 0x07, 0x4d, 0x07, 0x4d, 0x52, 0x2d, 0x07, 0x4d, 0x4a, 0x42, ++ 0x15, 0x15, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, 0x42, 0x58, 0x15, 0x42, 0x58, 0x40, 0x40, ++ 0x4a, 0x05, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1a, 0x27, 0x05, 0x42, 0x07, 0x0a, ++ 0x0f, 0x4a, 0x2d, 0x1a, 0x15, 0x4a, 0x1d, 0x0a, 0x18, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x40, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x40, ++ 0x40, 0x40, 0x04, 0x46, 0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x07, 0x05, 0x05, 0x57, 0x52, 0x49, 0x05, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x42, 0x42, 0x4f, 0x4f, 0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x47, 0x57, 0x62, 0x5c, ++ 0x57, 0x4b, 0x00, 0x03, 0x46, 0x4f, 0x4f, 0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x47, ++ 0x57, 0x62, 0x5c, 0x57, 0x4b, 0x00, 0x03, 0x46, 0x0e, 0x4d, 0x25, 0x52, 0x57, 0x57, 0x4c, ++ 0x4f, 0x4f, 0x49, 0x44, 0x00, 0x44, 0x08, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x08, 0x4c, 0x52, ++ 0x2c, 0x07, 0x4c, 0x08, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x4a, 0x42, 0x14, 0x14, 0x0f, 0x15, ++ 0x0f, 0x15, 0x07, 0x15, 0x42, 0x57, 0x15, 0x42, 0x57, 0x40, 0x40, 0x4a, 0x06, 0x0d, 0x05, ++ 0x4a, 0x0f, 0x05, 0x42, 0x07, 0x1c, 0x27, 0x06, 0x42, 0x08, 0x0b, 0x0f, 0x4a, 0x2c, 0x1a, ++ 0x14, 0x4a, 0x1b, 0x0b, 0x17, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x41, 0x42, 0x52, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x40, 0x40, 0x40, 0x04, 0x44, ++ 0x42, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x05, 0x05, ++ 0x56, 0x52, 0x48, 0x05, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4e, 0x4e, ++ 0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x46, 0x56, 0x62, 0x5c, 0x56, 0x4a, 0x01, 0x03, ++ 0x44, 0x4e, 0x4e, 0x44, 0x4c, 0x4a, 0x07, 0x4c, 0x5c, 0x4a, 0x46, 0x56, 0x62, 0x5c, 0x56, ++ 0x4a, 0x01, 0x03, 0x44, 0x0f, 0x4d, 0x25, 0x52, 0x56, 0x56, 0x4c, 0x4e, 0x4e, 0x48, 0x44, ++ 0x01, 0x44, 0x09, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x09, 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x09, ++ 0x4c, 0x52, 0x2c, 0x07, 0x4c, 0x4a, 0x42, 0x14, 0x14, 0x0f, 0x15, 0x0f, 0x15, 0x07, 0x15, ++ 0x42, 0x56, 0x15, 0x42, 0x56, 0x40, 0x40, 0x4a, 0x07, 0x0d, 0x05, 0x4a, 0x0f, 0x05, 0x42, ++ 0x07, 0x1d, 0x27, 0x07, 0x42, 0x09, 0x0b, 0x0f, 0x4a, 0x2c, 0x1a, 0x14, 0x4a, 0x1a, 0x0b, ++ 0x16, 0x05, 0x07, 0x15, 0x12, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x42, 0x41, 0x51, 0x58, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x40, 0x40, 0x40, 0x03, 0x42, 0x41, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x55, 0x51, 0x47, 0x06, ++ 0x13, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4d, 0x4d, 0x43, 0x4b, 0x49, 0x07, ++ 0x4b, 0x5b, 0x49, 0x45, 0x55, 0x61, 0x5b, 0x55, 0x48, 0x02, 0x04, 0x42, 0x4d, 0x4d, 0x43, ++ 0x4b, 0x49, 0x07, 0x4b, 0x5b, 0x49, 0x45, 0x55, 0x61, 0x5b, 0x55, 0x48, 0x02, 0x04, 0x42, ++ 0x10, 0x4e, 0x26, 0x51, 0x55, 0x55, 0x4b, 0x4d, 0x4d, 0x47, 0x43, 0x02, 0x43, 0x0a, 0x4b, ++ 0x51, 0x2b, 0x07, 0x4b, 0x0a, 0x4b, 0x51, 0x2b, 0x07, 0x4b, 0x0a, 0x4b, 0x51, 0x2b, 0x07, ++ 0x4b, 0x49, 0x41, 0x13, 0x13, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x55, 0x16, 0x41, ++ 0x55, 0x40, 0x40, 0x49, 0x08, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x1f, 0x27, 0x08, ++ 0x41, 0x0a, 0x0c, 0x0f, 0x49, 0x2b, 0x19, 0x13, 0x49, 0x18, 0x0c, 0x15, 0x06, 0x07, 0x16, ++ 0x11, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x43, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x02, 0x40, 0x40, 0x40, 0x02, 0x40, 0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x07, 0x06, 0x06, 0x54, 0x51, 0x45, 0x06, 0x12, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x41, 0x41, 0x4c, 0x4c, 0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x44, ++ 0x54, 0x61, 0x5a, 0x54, 0x47, 0x03, 0x05, 0x40, 0x4c, 0x4c, 0x42, 0x4a, 0x49, 0x07, 0x4a, ++ 0x5a, 0x49, 0x44, 0x54, 0x61, 0x5a, 0x54, 0x47, 0x03, 0x05, 0x40, 0x12, 0x4e, 0x26, 0x51, ++ 0x54, 0x54, 0x4a, 0x4c, 0x4c, 0x45, 0x42, 0x03, 0x42, 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, ++ 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x0b, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x49, 0x41, 0x12, ++ 0x12, 0x0f, 0x16, 0x0f, 0x16, 0x07, 0x16, 0x41, 0x54, 0x16, 0x41, 0x54, 0x40, 0x40, 0x49, ++ 0x0a, 0x0e, 0x06, 0x49, 0x0f, 0x06, 0x41, 0x07, 0x20, 0x27, 0x0a, 0x41, 0x0b, 0x0d, 0x0f, ++ 0x49, 0x2a, 0x19, 0x12, 0x49, 0x17, 0x0d, 0x14, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x07, 0x44, 0x41, 0x51, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x40, 0x40, ++ 0x40, 0x02, 0x01, 0x41, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x07, 0x06, 0x06, 0x53, 0x51, 0x44, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x41, ++ 0x41, 0x4b, 0x4b, 0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x43, 0x53, 0x61, 0x5a, 0x53, ++ 0x45, 0x04, 0x05, 0x01, 0x4b, 0x4b, 0x42, 0x4a, 0x49, 0x07, 0x4a, 0x5a, 0x49, 0x43, 0x53, ++ 0x61, 0x5a, 0x53, 0x45, 0x04, 0x05, 0x01, 0x13, 0x4e, 0x26, 0x51, 0x53, 0x53, 0x4a, 0x4b, ++ 0x4b, 0x44, 0x42, 0x04, 0x42, 0x0c, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x0c, 0x4a, 0x51, 0x2a, ++ 0x07, 0x4a, 0x0c, 0x4a, 0x51, 0x2a, 0x07, 0x4a, 0x49, 0x41, 0x12, 0x12, 0x0f, 0x16, 0x0f, ++ 0x16, 0x07, 0x16, 0x41, 0x53, 0x16, 0x41, 0x53, 0x40, 0x40, 0x49, 0x0b, 0x0e, 0x06, 0x49, ++ 0x0f, 0x06, 0x41, 0x07, 0x22, 0x27, 0x0b, 0x41, 0x0c, 0x0d, 0x0f, 0x49, 0x2a, 0x19, 0x12, ++ 0x49, 0x15, 0x0d, 0x13, 0x06, 0x07, 0x16, 0x11, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x45, ++ 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x40, 0x40, 0x40, 0x01, 0x03, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x52, ++ 0x50, 0x43, 0x07, 0x11, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x4a, 0x41, ++ 0x49, 0x48, 0x07, 0x49, 0x59, 0x48, 0x42, 0x52, 0x60, 0x59, 0x52, 0x44, 0x05, 0x06, 0x03, ++ 0x4a, 0x4a, 0x41, 0x49, 0x48, 0x07, 0x49, 0x59, 0x48, 0x42, 0x52, 0x60, 0x59, 0x52, 0x44, ++ 0x05, 0x06, 0x03, 0x14, 0x4f, 0x27, 0x50, 0x52, 0x52, 0x49, 0x4a, 0x4a, 0x43, 0x41, 0x05, ++ 0x41, 0x0d, 0x49, 0x50, 0x29, 0x07, 0x49, 0x0d, 0x49, 0x50, 0x29, 0x07, 0x49, 0x0d, 0x49, ++ 0x50, 0x29, 0x07, 0x49, 0x48, 0x40, 0x11, 0x11, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, ++ 0x52, 0x17, 0x40, 0x52, 0x40, 0x40, 0x48, 0x0c, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, ++ 0x23, 0x27, 0x0c, 0x40, 0x0d, 0x0e, 0x0f, 0x48, 0x29, 0x18, 0x11, 0x48, 0x14, 0x0e, 0x12, ++ 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x46, 0x40, 0x50, 0x58, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x40, 0x40, 0x40, 0x00, 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x51, 0x50, 0x42, 0x07, 0x10, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x41, 0x49, 0x48, 0x07, 0x49, ++ 0x59, 0x48, 0x41, 0x51, 0x60, 0x59, 0x51, 0x42, 0x06, 0x06, 0x04, 0x49, 0x49, 0x41, 0x49, ++ 0x48, 0x07, 0x49, 0x59, 0x48, 0x41, 0x51, 0x60, 0x59, 0x51, 0x42, 0x06, 0x06, 0x04, 0x15, ++ 0x4f, 0x27, 0x50, 0x51, 0x51, 0x49, 0x49, 0x49, 0x42, 0x41, 0x06, 0x41, 0x0e, 0x49, 0x50, ++ 0x28, 0x07, 0x49, 0x0e, 0x49, 0x50, 0x28, 0x07, 0x49, 0x0e, 0x49, 0x50, 0x28, 0x07, 0x49, ++ 0x48, 0x40, 0x10, 0x10, 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x51, 0x17, 0x40, 0x51, ++ 0x40, 0x40, 0x48, 0x0d, 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x25, 0x27, 0x0d, 0x40, ++ 0x0e, 0x0e, 0x0f, 0x48, 0x28, 0x18, 0x10, 0x48, 0x12, 0x0e, 0x11, 0x07, 0x07, 0x17, 0x10, ++ 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x47, 0x40, 0x50, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x40, 0x40, 0x40, 0x00, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x50, 0x50, 0x40, 0x07, 0x10, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48, 0x48, 0x07, 0x48, 0x58, 0x48, 0x40, 0x50, ++ 0x60, 0x58, 0x50, 0x40, 0x07, 0x07, 0x06, 0x48, 0x48, 0x40, 0x48, 0x48, 0x07, 0x48, 0x58, ++ 0x48, 0x40, 0x50, 0x60, 0x58, 0x50, 0x40, 0x07, 0x07, 0x06, 0x17, 0x4f, 0x27, 0x50, 0x50, ++ 0x50, 0x48, 0x48, 0x48, 0x40, 0x40, 0x07, 0x40, 0x0f, 0x48, 0x50, 0x28, 0x07, 0x48, 0x0f, ++ 0x48, 0x50, 0x28, 0x07, 0x48, 0x0f, 0x48, 0x50, 0x28, 0x07, 0x48, 0x48, 0x40, 0x10, 0x10, ++ 0x0f, 0x17, 0x0f, 0x17, 0x07, 0x17, 0x40, 0x50, 0x17, 0x40, 0x50, 0x40, 0x40, 0x48, 0x0f, ++ 0x0f, 0x07, 0x48, 0x0f, 0x07, 0x40, 0x07, 0x27, 0x27, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x48, ++ 0x28, 0x18, 0x10, 0x48, 0x10, 0x0f, 0x10, 0x07, 0x07, 0x17, 0x10, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x07, 0x48, 0x00, 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x08, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, ++ 0x08, 0x08, 0x4f, 0x4f, 0x00, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x47, 0x47, 0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x00, 0x4f, 0x5f, 0x57, 0x4f, 0x00, ++ 0x08, 0x08, 0x08, 0x47, 0x47, 0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x00, 0x4f, 0x5f, ++ 0x57, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x18, 0x50, 0x28, 0x4f, 0x4f, 0x4f, 0x47, 0x47, 0x47, ++ 0x00, 0x00, 0x08, 0x00, 0x10, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x10, 0x47, 0x4f, 0x27, 0x07, ++ 0x47, 0x10, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x47, 0x00, 0x0f, 0x0f, 0x0f, 0x18, 0x0f, 0x18, ++ 0x07, 0x18, 0x00, 0x4f, 0x18, 0x00, 0x4f, 0x40, 0x40, 0x47, 0x10, 0x10, 0x08, 0x47, 0x0f, ++ 0x08, 0x00, 0x07, 0x28, 0x27, 0x10, 0x00, 0x10, 0x10, 0x0f, 0x47, 0x27, 0x17, 0x0f, 0x47, ++ 0x0f, 0x10, 0x0f, 0x08, 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x49, 0x00, ++ 0x4f, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0a, 0x00, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4e, 0x4f, ++ 0x01, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x46, 0x00, 0x47, ++ 0x47, 0x07, 0x47, 0x57, 0x47, 0x01, 0x4e, 0x5f, 0x57, 0x4e, 0x02, 0x09, 0x08, 0x0a, 0x46, ++ 0x46, 0x00, 0x47, 0x47, 0x07, 0x47, 0x57, 0x47, 0x01, 0x4e, 0x5f, 0x57, 0x4e, 0x02, 0x09, ++ 0x08, 0x0a, 0x19, 0x50, 0x28, 0x4f, 0x4e, 0x4e, 0x47, 0x46, 0x46, 0x01, 0x00, 0x09, 0x00, ++ 0x11, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x11, 0x47, 0x4f, 0x27, 0x07, 0x47, 0x11, 0x47, 0x4f, ++ 0x27, 0x07, 0x47, 0x47, 0x00, 0x0f, 0x0f, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4e, ++ 0x18, 0x00, 0x4e, 0x40, 0x40, 0x47, 0x11, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x2a, ++ 0x27, 0x11, 0x00, 0x11, 0x10, 0x0f, 0x47, 0x27, 0x17, 0x0f, 0x47, 0x0d, 0x10, 0x0e, 0x08, ++ 0x07, 0x18, 0x0f, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x4a, 0x00, 0x4f, 0x58, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x41, 0x40, 0x40, 0x40, 0x41, 0x0c, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x08, 0x08, 0x4d, 0x4f, 0x02, 0x08, 0x0e, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x45, 0x45, 0x01, 0x46, 0x47, 0x07, 0x46, 0x56, ++ 0x47, 0x02, 0x4d, 0x5f, 0x56, 0x4d, 0x03, 0x0a, 0x09, 0x0c, 0x45, 0x45, 0x01, 0x46, 0x47, ++ 0x07, 0x46, 0x56, 0x47, 0x02, 0x4d, 0x5f, 0x56, 0x4d, 0x03, 0x0a, 0x09, 0x0c, 0x1a, 0x50, ++ 0x28, 0x4f, 0x4d, 0x4d, 0x46, 0x45, 0x45, 0x02, 0x01, 0x0a, 0x01, 0x12, 0x46, 0x4f, 0x26, ++ 0x07, 0x46, 0x12, 0x46, 0x4f, 0x26, 0x07, 0x46, 0x12, 0x46, 0x4f, 0x26, 0x07, 0x46, 0x47, ++ 0x00, 0x0e, 0x0e, 0x0f, 0x18, 0x0f, 0x18, 0x07, 0x18, 0x00, 0x4d, 0x18, 0x00, 0x4d, 0x40, ++ 0x40, 0x47, 0x12, 0x10, 0x08, 0x47, 0x0f, 0x08, 0x00, 0x07, 0x2b, 0x27, 0x12, 0x00, 0x12, ++ 0x11, 0x0f, 0x47, 0x26, 0x17, 0x0e, 0x47, 0x0c, 0x11, 0x0d, 0x08, 0x07, 0x18, 0x0f, 0x0f, ++ 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x07, 0x4b, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, ++ 0x40, 0x40, 0x40, 0x42, 0x0e, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x07, 0x09, 0x09, 0x4c, 0x4e, 0x04, 0x09, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x01, 0x01, 0x44, 0x44, 0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x03, 0x4c, 0x5e, ++ 0x55, 0x4c, 0x05, 0x0b, 0x0a, 0x0e, 0x44, 0x44, 0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, ++ 0x03, 0x4c, 0x5e, 0x55, 0x4c, 0x05, 0x0b, 0x0a, 0x0e, 0x1c, 0x51, 0x29, 0x4e, 0x4c, 0x4c, ++ 0x45, 0x44, 0x44, 0x04, 0x02, 0x0b, 0x02, 0x13, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x13, 0x45, ++ 0x4e, 0x25, 0x07, 0x45, 0x13, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x46, 0x01, 0x0d, 0x0d, 0x0f, ++ 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4c, 0x19, 0x01, 0x4c, 0x40, 0x40, 0x46, 0x14, 0x11, ++ 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x2d, 0x27, 0x14, 0x01, 0x13, 0x12, 0x0f, 0x46, 0x25, ++ 0x16, 0x0d, 0x46, 0x0a, 0x12, 0x0c, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4c, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x42, 0x40, 0x40, 0x40, 0x42, ++ 0x10, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, ++ 0x09, 0x4b, 0x4e, 0x05, 0x09, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x43, ++ 0x43, 0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x04, 0x4b, 0x5e, 0x55, 0x4b, 0x06, 0x0c, ++ 0x0a, 0x10, 0x43, 0x43, 0x02, 0x45, 0x46, 0x07, 0x45, 0x55, 0x46, 0x04, 0x4b, 0x5e, 0x55, ++ 0x4b, 0x06, 0x0c, 0x0a, 0x10, 0x1d, 0x51, 0x29, 0x4e, 0x4b, 0x4b, 0x45, 0x43, 0x43, 0x05, ++ 0x02, 0x0c, 0x02, 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, ++ 0x14, 0x45, 0x4e, 0x25, 0x07, 0x45, 0x46, 0x01, 0x0d, 0x0d, 0x0f, 0x19, 0x0f, 0x19, 0x07, ++ 0x19, 0x01, 0x4b, 0x19, 0x01, 0x4b, 0x40, 0x40, 0x46, 0x15, 0x11, 0x09, 0x46, 0x0f, 0x09, ++ 0x01, 0x07, 0x2e, 0x27, 0x15, 0x01, 0x14, 0x12, 0x0f, 0x46, 0x25, 0x16, 0x0d, 0x46, 0x09, ++ 0x12, 0x0b, 0x09, 0x07, 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x4d, 0x01, 0x4e, ++ 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x43, 0x40, 0x40, 0x40, 0x43, 0x12, 0x01, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4a, 0x4e, 0x06, ++ 0x09, 0x0c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x42, 0x42, 0x03, 0x44, 0x46, ++ 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x08, 0x0d, 0x0b, 0x12, 0x42, 0x42, ++ 0x03, 0x44, 0x46, 0x07, 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x08, 0x0d, 0x0b, ++ 0x12, 0x1e, 0x51, 0x29, 0x4e, 0x4a, 0x4a, 0x44, 0x42, 0x42, 0x06, 0x03, 0x0d, 0x03, 0x15, ++ 0x44, 0x4e, 0x24, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x24, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x24, ++ 0x07, 0x44, 0x46, 0x01, 0x0c, 0x0c, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4a, 0x19, ++ 0x01, 0x4a, 0x40, 0x40, 0x46, 0x16, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x30, 0x27, ++ 0x16, 0x01, 0x15, 0x13, 0x0f, 0x46, 0x24, 0x16, 0x0c, 0x46, 0x07, 0x13, 0x0a, 0x09, 0x07, ++ 0x19, 0x0e, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x4e, 0x01, 0x4e, 0x58, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x44, 0x40, 0x40, 0x40, 0x44, 0x13, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x09, 0x09, 0x4a, 0x4e, 0x07, 0x09, 0x0b, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x42, 0x42, 0x03, 0x44, 0x46, 0x07, 0x44, 0x54, 0x46, ++ 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x09, 0x0d, 0x0b, 0x13, 0x42, 0x42, 0x03, 0x44, 0x46, 0x07, ++ 0x44, 0x54, 0x46, 0x05, 0x4a, 0x5e, 0x54, 0x4a, 0x09, 0x0d, 0x0b, 0x13, 0x1f, 0x52, 0x29, ++ 0x4e, 0x4a, 0x4a, 0x44, 0x42, 0x42, 0x07, 0x03, 0x0d, 0x03, 0x15, 0x44, 0x4e, 0x23, 0x07, ++ 0x44, 0x15, 0x44, 0x4e, 0x23, 0x07, 0x44, 0x15, 0x44, 0x4e, 0x23, 0x07, 0x44, 0x46, 0x01, ++ 0x0b, 0x0b, 0x0f, 0x19, 0x0f, 0x19, 0x07, 0x19, 0x01, 0x4a, 0x19, 0x01, 0x4a, 0x40, 0x40, ++ 0x46, 0x17, 0x11, 0x09, 0x46, 0x0f, 0x09, 0x01, 0x07, 0x31, 0x27, 0x17, 0x01, 0x15, 0x13, ++ 0x0f, 0x46, 0x23, 0x15, 0x0b, 0x46, 0x05, 0x13, 0x09, 0x09, 0x07, 0x19, 0x0d, 0x0f, 0x0f, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x4e, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x44, 0x40, ++ 0x40, 0x40, 0x44, 0x15, 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x07, 0x0a, 0x0a, 0x49, 0x4d, 0x09, 0x0a, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x02, 0x02, 0x41, 0x41, 0x04, 0x43, 0x45, 0x07, 0x43, 0x53, 0x45, 0x06, 0x49, 0x5d, 0x53, ++ 0x49, 0x0b, 0x0e, 0x0c, 0x15, 0x41, 0x41, 0x04, 0x43, 0x45, 0x07, 0x43, 0x53, 0x45, 0x06, ++ 0x49, 0x5d, 0x53, 0x49, 0x0b, 0x0e, 0x0c, 0x15, 0x21, 0x52, 0x2a, 0x4d, 0x49, 0x49, 0x43, ++ 0x41, 0x41, 0x09, 0x04, 0x0e, 0x04, 0x16, 0x43, 0x4d, 0x23, 0x07, 0x43, 0x16, 0x43, 0x4d, ++ 0x23, 0x07, 0x43, 0x16, 0x43, 0x4d, 0x23, 0x07, 0x43, 0x45, 0x02, 0x0b, 0x0b, 0x0f, 0x1a, ++ 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x49, 0x1a, 0x02, 0x49, 0x40, 0x40, 0x45, 0x19, 0x12, 0x0a, ++ 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x33, 0x27, 0x19, 0x02, 0x16, 0x14, 0x0f, 0x45, 0x23, 0x15, ++ 0x0b, 0x45, 0x04, 0x14, 0x09, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x4f, 0x02, 0x4d, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x40, 0x40, 0x40, 0x45, 0x17, ++ 0x02, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, ++ 0x48, 0x4d, 0x0a, 0x0a, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x40, 0x40, ++ 0x05, 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x07, 0x48, 0x5d, 0x52, 0x48, 0x0d, 0x0f, 0x0d, ++ 0x17, 0x40, 0x40, 0x05, 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x07, 0x48, 0x5d, 0x52, 0x48, ++ 0x0d, 0x0f, 0x0d, 0x17, 0x22, 0x52, 0x2a, 0x4d, 0x48, 0x48, 0x42, 0x40, 0x40, 0x0a, 0x05, ++ 0x0f, 0x05, 0x17, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x17, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x17, ++ 0x42, 0x4d, 0x22, 0x07, 0x42, 0x45, 0x02, 0x0a, 0x0a, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, ++ 0x02, 0x48, 0x1a, 0x02, 0x48, 0x40, 0x40, 0x45, 0x1a, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, ++ 0x07, 0x35, 0x27, 0x1a, 0x02, 0x17, 0x15, 0x0f, 0x45, 0x22, 0x15, 0x0a, 0x45, 0x02, 0x15, ++ 0x08, 0x0a, 0x07, 0x1a, 0x0d, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x50, 0x02, 0x4d, 0x58, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x45, 0x40, 0x40, 0x40, 0x45, 0x19, 0x02, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x47, 0x4d, 0x0b, 0x0a, ++ 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x00, 0x00, 0x05, 0x42, 0x45, 0x07, ++ 0x42, 0x52, 0x45, 0x08, 0x47, 0x5d, 0x52, 0x47, 0x0e, 0x10, 0x0d, 0x19, 0x00, 0x00, 0x05, ++ 0x42, 0x45, 0x07, 0x42, 0x52, 0x45, 0x08, 0x47, 0x5d, 0x52, 0x47, 0x0e, 0x10, 0x0d, 0x19, ++ 0x23, 0x52, 0x2a, 0x4d, 0x47, 0x47, 0x42, 0x00, 0x00, 0x0b, 0x05, 0x10, 0x05, 0x18, 0x42, ++ 0x4d, 0x22, 0x07, 0x42, 0x18, 0x42, 0x4d, 0x22, 0x07, 0x42, 0x18, 0x42, 0x4d, 0x22, 0x07, ++ 0x42, 0x45, 0x02, 0x0a, 0x0a, 0x0f, 0x1a, 0x0f, 0x1a, 0x07, 0x1a, 0x02, 0x47, 0x1a, 0x02, ++ 0x47, 0x40, 0x40, 0x45, 0x1b, 0x12, 0x0a, 0x45, 0x0f, 0x0a, 0x02, 0x07, 0x36, 0x27, 0x1b, ++ 0x02, 0x18, 0x15, 0x0f, 0x45, 0x22, 0x15, 0x0a, 0x45, 0x01, 0x15, 0x07, 0x0a, 0x07, 0x1a, ++ 0x0d, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x51, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x46, 0x40, 0x40, 0x40, 0x46, 0x1b, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x46, 0x4c, 0x0c, 0x0b, 0x09, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x03, 0x03, 0x01, 0x01, 0x06, 0x41, 0x44, 0x07, 0x41, 0x51, 0x44, 0x09, ++ 0x46, 0x5c, 0x51, 0x46, 0x10, 0x11, 0x0e, 0x1b, 0x01, 0x01, 0x06, 0x41, 0x44, 0x07, 0x41, ++ 0x51, 0x44, 0x09, 0x46, 0x5c, 0x51, 0x46, 0x10, 0x11, 0x0e, 0x1b, 0x24, 0x53, 0x2b, 0x4c, ++ 0x46, 0x46, 0x41, 0x01, 0x01, 0x0c, 0x06, 0x11, 0x06, 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, ++ 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, 0x19, 0x41, 0x4c, 0x21, 0x07, 0x41, 0x44, 0x03, 0x09, ++ 0x09, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, 0x46, 0x1b, 0x03, 0x46, 0x40, 0x40, 0x44, ++ 0x1c, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, 0x38, 0x27, 0x1c, 0x03, 0x19, 0x16, 0x0f, ++ 0x44, 0x21, 0x14, 0x09, 0x44, 0x40, 0x16, 0x06, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x07, 0x52, 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x40, 0x40, ++ 0x40, 0x47, 0x1d, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x07, 0x0b, 0x0b, 0x45, 0x4c, 0x0e, 0x0b, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, ++ 0x03, 0x02, 0x02, 0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0a, 0x45, 0x5c, 0x50, 0x45, ++ 0x11, 0x12, 0x0f, 0x1d, 0x02, 0x02, 0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0a, 0x45, ++ 0x5c, 0x50, 0x45, 0x11, 0x12, 0x0f, 0x1d, 0x26, 0x53, 0x2b, 0x4c, 0x45, 0x45, 0x40, 0x02, ++ 0x02, 0x0e, 0x07, 0x12, 0x07, 0x1a, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1a, 0x40, 0x4c, 0x20, ++ 0x07, 0x40, 0x1a, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x44, 0x03, 0x08, 0x08, 0x0f, 0x1b, 0x0f, ++ 0x1b, 0x07, 0x1b, 0x03, 0x45, 0x1b, 0x03, 0x45, 0x40, 0x40, 0x44, 0x1e, 0x13, 0x0b, 0x44, ++ 0x0f, 0x0b, 0x03, 0x07, 0x39, 0x27, 0x1e, 0x03, 0x1a, 0x17, 0x0f, 0x44, 0x20, 0x14, 0x08, ++ 0x44, 0x41, 0x17, 0x05, 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x53, ++ 0x03, 0x4c, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x40, 0x40, 0x40, 0x47, 0x1f, 0x03, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0b, 0x0b, 0x44, ++ 0x4c, 0x0f, 0x0b, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x03, 0x03, 0x03, 0x03, 0x07, ++ 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0b, 0x44, 0x5c, 0x50, 0x44, 0x13, 0x13, 0x0f, 0x1f, ++ 0x03, 0x03, 0x07, 0x40, 0x44, 0x07, 0x40, 0x50, 0x44, 0x0b, 0x44, 0x5c, 0x50, 0x44, 0x13, ++ 0x13, 0x0f, 0x1f, 0x27, 0x53, 0x2b, 0x4c, 0x44, 0x44, 0x40, 0x03, 0x03, 0x0f, 0x07, 0x13, ++ 0x07, 0x1b, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1b, 0x40, 0x4c, 0x20, 0x07, 0x40, 0x1b, 0x40, ++ 0x4c, 0x20, 0x07, 0x40, 0x44, 0x03, 0x08, 0x08, 0x0f, 0x1b, 0x0f, 0x1b, 0x07, 0x1b, 0x03, ++ 0x44, 0x1b, 0x03, 0x44, 0x40, 0x40, 0x44, 0x1f, 0x13, 0x0b, 0x44, 0x0f, 0x0b, 0x03, 0x07, ++ 0x3b, 0x27, 0x1f, 0x03, 0x1b, 0x17, 0x0f, 0x44, 0x20, 0x14, 0x08, 0x44, 0x43, 0x17, 0x04, ++ 0x0b, 0x07, 0x1b, 0x0c, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x54, 0x04, 0x4b, 0x58, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x48, 0x40, 0x40, 0x40, 0x48, 0x21, 0x04, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x43, 0x4b, 0x10, 0x0c, 0x07, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, 0x04, 0x04, 0x08, 0x00, 0x43, 0x07, 0x00, ++ 0x4f, 0x43, 0x0c, 0x43, 0x5b, 0x4f, 0x43, 0x14, 0x14, 0x10, 0x21, 0x04, 0x04, 0x08, 0x00, ++ 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0c, 0x43, 0x5b, 0x4f, 0x43, 0x14, 0x14, 0x10, 0x21, 0x28, ++ 0x54, 0x2c, 0x4b, 0x43, 0x43, 0x00, 0x04, 0x04, 0x10, 0x08, 0x14, 0x08, 0x1c, 0x00, 0x4b, ++ 0x1f, 0x07, 0x00, 0x1c, 0x00, 0x4b, 0x1f, 0x07, 0x00, 0x1c, 0x00, 0x4b, 0x1f, 0x07, 0x00, ++ 0x43, 0x04, 0x07, 0x07, 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x43, 0x1c, 0x04, 0x43, ++ 0x40, 0x40, 0x43, 0x20, 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3c, 0x27, 0x20, 0x04, ++ 0x1c, 0x18, 0x0f, 0x43, 0x1f, 0x13, 0x07, 0x43, 0x44, 0x18, 0x03, 0x0c, 0x07, 0x1c, 0x0b, ++ 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x55, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x49, 0x40, 0x40, 0x40, 0x49, 0x22, 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x07, 0x0c, 0x0c, 0x42, 0x4b, 0x11, 0x0c, 0x06, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x04, 0x04, 0x05, 0x05, 0x08, 0x00, 0x43, 0x07, 0x00, 0x4f, 0x43, 0x0d, 0x42, ++ 0x5b, 0x4f, 0x42, 0x16, 0x15, 0x10, 0x22, 0x05, 0x05, 0x08, 0x00, 0x43, 0x07, 0x00, 0x4f, ++ 0x43, 0x0d, 0x42, 0x5b, 0x4f, 0x42, 0x16, 0x15, 0x10, 0x22, 0x29, 0x54, 0x2c, 0x4b, 0x42, ++ 0x42, 0x00, 0x05, 0x05, 0x11, 0x08, 0x15, 0x08, 0x1d, 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x1d, ++ 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x1d, 0x00, 0x4b, 0x1e, 0x07, 0x00, 0x43, 0x04, 0x06, 0x06, ++ 0x0f, 0x1c, 0x0f, 0x1c, 0x07, 0x1c, 0x04, 0x42, 0x1c, 0x04, 0x42, 0x40, 0x40, 0x43, 0x21, ++ 0x14, 0x0c, 0x43, 0x0f, 0x0c, 0x04, 0x07, 0x3e, 0x27, 0x21, 0x04, 0x1d, 0x18, 0x0f, 0x43, ++ 0x1e, 0x13, 0x06, 0x43, 0x46, 0x18, 0x02, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x07, 0x56, 0x04, 0x4b, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x40, 0x40, 0x40, ++ 0x49, 0x24, 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, ++ 0x0c, 0x0c, 0x41, 0x4b, 0x13, 0x0c, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x04, 0x04, ++ 0x06, 0x06, 0x09, 0x01, 0x43, 0x07, 0x01, 0x4e, 0x43, 0x0e, 0x41, 0x5b, 0x4e, 0x41, 0x18, ++ 0x16, 0x11, 0x24, 0x06, 0x06, 0x09, 0x01, 0x43, 0x07, 0x01, 0x4e, 0x43, 0x0e, 0x41, 0x5b, ++ 0x4e, 0x41, 0x18, 0x16, 0x11, 0x24, 0x2b, 0x54, 0x2c, 0x4b, 0x41, 0x41, 0x01, 0x06, 0x06, ++ 0x13, 0x09, 0x16, 0x09, 0x1e, 0x01, 0x4b, 0x1e, 0x07, 0x01, 0x1e, 0x01, 0x4b, 0x1e, 0x07, ++ 0x01, 0x1e, 0x01, 0x4b, 0x1e, 0x07, 0x01, 0x43, 0x04, 0x06, 0x06, 0x0f, 0x1c, 0x0f, 0x1c, ++ 0x07, 0x1c, 0x04, 0x41, 0x1c, 0x04, 0x41, 0x40, 0x40, 0x43, 0x23, 0x14, 0x0c, 0x43, 0x0f, ++ 0x0c, 0x04, 0x07, 0x3e, 0x27, 0x23, 0x04, 0x1e, 0x19, 0x0f, 0x43, 0x1e, 0x13, 0x06, 0x43, ++ 0x48, 0x19, 0x01, 0x0c, 0x07, 0x1c, 0x0b, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x57, 0x05, ++ 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4a, 0x40, 0x40, 0x40, 0x4a, 0x26, 0x05, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x40, 0x4a, ++ 0x14, 0x0d, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x07, 0x07, 0x0a, 0x02, ++ 0x42, 0x07, 0x02, 0x4d, 0x42, 0x0f, 0x40, 0x5a, 0x4d, 0x40, 0x19, 0x17, 0x12, 0x26, 0x07, ++ 0x07, 0x0a, 0x02, 0x42, 0x07, 0x02, 0x4d, 0x42, 0x0f, 0x40, 0x5a, 0x4d, 0x40, 0x19, 0x17, ++ 0x12, 0x26, 0x2c, 0x55, 0x2d, 0x4a, 0x40, 0x40, 0x02, 0x07, 0x07, 0x14, 0x0a, 0x17, 0x0a, ++ 0x1f, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x1f, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x1f, 0x02, 0x4a, ++ 0x1d, 0x07, 0x02, 0x42, 0x05, 0x05, 0x05, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x40, ++ 0x1d, 0x05, 0x40, 0x40, 0x40, 0x42, 0x24, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, ++ 0x27, 0x24, 0x05, 0x1f, 0x1a, 0x0f, 0x42, 0x1d, 0x12, 0x05, 0x42, 0x49, 0x1a, 0x00, 0x0d, ++ 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x58, 0x05, 0x4a, 0x58, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x4a, 0x40, 0x40, 0x40, 0x4a, 0x28, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x00, 0x4a, 0x15, 0x0d, 0x05, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x05, 0x05, 0x08, 0x08, 0x0a, 0x02, 0x42, 0x07, 0x02, 0x4d, ++ 0x42, 0x10, 0x00, 0x5a, 0x4d, 0x00, 0x1b, 0x18, 0x12, 0x28, 0x08, 0x08, 0x0a, 0x02, 0x42, ++ 0x07, 0x02, 0x4d, 0x42, 0x10, 0x00, 0x5a, 0x4d, 0x00, 0x1b, 0x18, 0x12, 0x28, 0x2d, 0x55, ++ 0x2d, 0x4a, 0x00, 0x00, 0x02, 0x08, 0x08, 0x15, 0x0a, 0x18, 0x0a, 0x20, 0x02, 0x4a, 0x1d, ++ 0x07, 0x02, 0x20, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x20, 0x02, 0x4a, 0x1d, 0x07, 0x02, 0x42, ++ 0x05, 0x05, 0x05, 0x0f, 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x00, 0x1d, 0x05, 0x00, 0x40, ++ 0x40, 0x42, 0x25, 0x15, 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x25, 0x05, 0x20, ++ 0x1a, 0x0f, 0x42, 0x1d, 0x12, 0x05, 0x42, 0x4b, 0x1a, 0x40, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, ++ 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x07, 0x59, 0x05, 0x4a, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4b, ++ 0x40, 0x40, 0x40, 0x4b, 0x2a, 0x05, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x07, 0x0d, 0x0d, 0x01, 0x4a, 0x16, 0x0d, 0x04, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x05, 0x05, 0x09, 0x09, 0x0b, 0x03, 0x42, 0x07, 0x03, 0x4c, 0x42, 0x11, 0x01, 0x5a, ++ 0x4c, 0x01, 0x1c, 0x19, 0x13, 0x2a, 0x09, 0x09, 0x0b, 0x03, 0x42, 0x07, 0x03, 0x4c, 0x42, ++ 0x11, 0x01, 0x5a, 0x4c, 0x01, 0x1c, 0x19, 0x13, 0x2a, 0x2e, 0x55, 0x2d, 0x4a, 0x01, 0x01, ++ 0x03, 0x09, 0x09, 0x16, 0x0b, 0x19, 0x0b, 0x21, 0x03, 0x4a, 0x1c, 0x07, 0x03, 0x21, 0x03, ++ 0x4a, 0x1c, 0x07, 0x03, 0x21, 0x03, 0x4a, 0x1c, 0x07, 0x03, 0x42, 0x05, 0x04, 0x04, 0x0f, ++ 0x1d, 0x0f, 0x1d, 0x07, 0x1d, 0x05, 0x01, 0x1d, 0x05, 0x01, 0x40, 0x40, 0x42, 0x26, 0x15, ++ 0x0d, 0x42, 0x0f, 0x0d, 0x05, 0x07, 0x3e, 0x27, 0x26, 0x05, 0x21, 0x1b, 0x0f, 0x42, 0x1c, ++ 0x12, 0x04, 0x42, 0x4c, 0x1b, 0x41, 0x0d, 0x07, 0x1d, 0x0a, 0x0f, 0x0f, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x5a, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4c, 0x40, 0x40, 0x40, 0x4c, ++ 0x2c, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, ++ 0x0e, 0x02, 0x49, 0x18, 0x0e, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0a, ++ 0x0a, 0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x12, 0x02, 0x59, 0x4b, 0x02, 0x1e, 0x1a, ++ 0x14, 0x2c, 0x0a, 0x0a, 0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x12, 0x02, 0x59, 0x4b, ++ 0x02, 0x1e, 0x1a, 0x14, 0x2c, 0x30, 0x56, 0x2e, 0x49, 0x02, 0x02, 0x04, 0x0a, 0x0a, 0x18, ++ 0x0c, 0x1a, 0x0c, 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, ++ 0x22, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x41, 0x06, 0x03, 0x03, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, ++ 0x1e, 0x06, 0x02, 0x1e, 0x06, 0x02, 0x40, 0x40, 0x41, 0x28, 0x16, 0x0e, 0x41, 0x0f, 0x0e, ++ 0x06, 0x07, 0x3e, 0x27, 0x28, 0x06, 0x22, 0x1c, 0x0f, 0x41, 0x1b, 0x11, 0x03, 0x41, 0x4e, ++ 0x1c, 0x42, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x5b, 0x06, 0x49, ++ 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4c, 0x40, 0x40, 0x40, 0x4c, 0x2e, 0x06, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x03, 0x49, 0x19, ++ 0x0e, 0x03, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0b, 0x0b, 0x0c, 0x04, 0x41, ++ 0x07, 0x04, 0x4b, 0x41, 0x13, 0x03, 0x59, 0x4b, 0x03, 0x1f, 0x1b, 0x14, 0x2e, 0x0b, 0x0b, ++ 0x0c, 0x04, 0x41, 0x07, 0x04, 0x4b, 0x41, 0x13, 0x03, 0x59, 0x4b, 0x03, 0x1f, 0x1b, 0x14, ++ 0x2e, 0x31, 0x56, 0x2e, 0x49, 0x03, 0x03, 0x04, 0x0b, 0x0b, 0x19, 0x0c, 0x1b, 0x0c, 0x23, ++ 0x04, 0x49, 0x1b, 0x07, 0x04, 0x23, 0x04, 0x49, 0x1b, 0x07, 0x04, 0x23, 0x04, 0x49, 0x1b, ++ 0x07, 0x04, 0x41, 0x06, 0x03, 0x03, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x03, 0x1e, ++ 0x06, 0x03, 0x40, 0x40, 0x41, 0x29, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, ++ 0x29, 0x06, 0x23, 0x1c, 0x0f, 0x41, 0x1b, 0x11, 0x03, 0x41, 0x4f, 0x1c, 0x43, 0x0e, 0x07, ++ 0x1e, 0x09, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x5c, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x4d, 0x40, 0x40, 0x40, 0x4d, 0x30, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0e, 0x0e, 0x04, 0x49, 0x1a, 0x0e, 0x02, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x06, 0x06, 0x0c, 0x0c, 0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, ++ 0x14, 0x04, 0x59, 0x4a, 0x04, 0x21, 0x1c, 0x15, 0x30, 0x0c, 0x0c, 0x0d, 0x05, 0x41, 0x07, ++ 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, 0x04, 0x21, 0x1c, 0x15, 0x30, 0x32, 0x56, 0x2e, ++ 0x49, 0x04, 0x04, 0x05, 0x0c, 0x0c, 0x1a, 0x0d, 0x1c, 0x0d, 0x24, 0x05, 0x49, 0x1a, 0x07, ++ 0x05, 0x24, 0x05, 0x49, 0x1a, 0x07, 0x05, 0x24, 0x05, 0x49, 0x1a, 0x07, 0x05, 0x41, 0x06, ++ 0x02, 0x02, 0x0f, 0x1e, 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x04, 0x1e, 0x06, 0x04, 0x40, 0x40, ++ 0x41, 0x2a, 0x16, 0x0e, 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x2a, 0x06, 0x24, 0x1d, ++ 0x0f, 0x41, 0x1a, 0x11, 0x02, 0x41, 0x51, 0x1d, 0x44, 0x0e, 0x07, 0x1e, 0x09, 0x0f, 0x0f, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x5d, 0x06, 0x49, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4e, 0x40, ++ 0x40, 0x40, 0x4e, 0x31, 0x06, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x07, 0x0e, 0x0e, 0x04, 0x49, 0x1b, 0x0e, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x06, 0x06, 0x0c, 0x0c, 0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, 0x04, 0x59, 0x4a, ++ 0x04, 0x22, 0x1c, 0x15, 0x31, 0x0c, 0x0c, 0x0d, 0x05, 0x41, 0x07, 0x05, 0x4a, 0x41, 0x14, ++ 0x04, 0x59, 0x4a, 0x04, 0x22, 0x1c, 0x15, 0x31, 0x33, 0x57, 0x2e, 0x49, 0x04, 0x04, 0x05, ++ 0x0c, 0x0c, 0x1b, 0x0d, 0x1c, 0x0d, 0x24, 0x05, 0x49, 0x19, 0x07, 0x05, 0x24, 0x05, 0x49, ++ 0x19, 0x07, 0x05, 0x24, 0x05, 0x49, 0x19, 0x07, 0x05, 0x41, 0x06, 0x01, 0x01, 0x0f, 0x1e, ++ 0x0f, 0x1e, 0x07, 0x1e, 0x06, 0x04, 0x1e, 0x06, 0x04, 0x40, 0x40, 0x41, 0x2b, 0x16, 0x0e, ++ 0x41, 0x0f, 0x0e, 0x06, 0x07, 0x3e, 0x27, 0x2b, 0x06, 0x24, 0x1d, 0x0f, 0x41, 0x19, 0x10, ++ 0x01, 0x41, 0x53, 0x1d, 0x45, 0x0e, 0x07, 0x1e, 0x08, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x5d, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x4e, 0x33, ++ 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, ++ 0x05, 0x48, 0x1d, 0x0f, 0x01, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0d, 0x0d, ++ 0x0e, 0x06, 0x40, 0x07, 0x06, 0x49, 0x40, 0x15, 0x05, 0x58, 0x49, 0x05, 0x24, 0x1d, 0x16, ++ 0x33, 0x0d, 0x0d, 0x0e, 0x06, 0x40, 0x07, 0x06, 0x49, 0x40, 0x15, 0x05, 0x58, 0x49, 0x05, ++ 0x24, 0x1d, 0x16, 0x33, 0x35, 0x57, 0x2f, 0x48, 0x05, 0x05, 0x06, 0x0d, 0x0d, 0x1d, 0x0e, ++ 0x1d, 0x0e, 0x25, 0x06, 0x48, 0x19, 0x07, 0x06, 0x25, 0x06, 0x48, 0x19, 0x07, 0x06, 0x25, ++ 0x06, 0x48, 0x19, 0x07, 0x06, 0x40, 0x07, 0x01, 0x01, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, ++ 0x07, 0x05, 0x1f, 0x07, 0x05, 0x40, 0x40, 0x40, 0x2d, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, ++ 0x07, 0x3e, 0x27, 0x2d, 0x07, 0x25, 0x1e, 0x0f, 0x40, 0x19, 0x10, 0x01, 0x40, 0x54, 0x1e, ++ 0x45, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x5e, 0x07, 0x48, 0x58, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x4f, 0x40, 0x40, 0x40, 0x4f, 0x35, 0x07, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x06, 0x48, 0x1e, 0x0f, ++ 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0e, 0x0e, 0x0f, 0x07, 0x40, 0x07, ++ 0x07, 0x48, 0x40, 0x16, 0x06, 0x58, 0x48, 0x06, 0x26, 0x1e, 0x17, 0x35, 0x0e, 0x0e, 0x0f, ++ 0x07, 0x40, 0x07, 0x07, 0x48, 0x40, 0x16, 0x06, 0x58, 0x48, 0x06, 0x26, 0x1e, 0x17, 0x35, ++ 0x36, 0x57, 0x2f, 0x48, 0x06, 0x06, 0x07, 0x0e, 0x0e, 0x1e, 0x0f, 0x1e, 0x0f, 0x26, 0x07, ++ 0x48, 0x18, 0x07, 0x07, 0x26, 0x07, 0x48, 0x18, 0x07, 0x07, 0x26, 0x07, 0x48, 0x18, 0x07, ++ 0x07, 0x40, 0x07, 0x00, 0x00, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x06, 0x1f, 0x07, ++ 0x06, 0x40, 0x40, 0x40, 0x2e, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2e, ++ 0x07, 0x26, 0x1f, 0x0f, 0x40, 0x18, 0x10, 0x00, 0x40, 0x56, 0x1f, 0x46, 0x0f, 0x07, 0x1f, ++ 0x08, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x5f, 0x07, 0x48, 0x58, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x4f, 0x40, 0x40, 0x40, 0x4f, 0x37, 0x07, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x07, 0x0f, 0x0f, 0x07, 0x48, 0x1f, 0x0f, 0x00, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x07, 0x40, 0x07, 0x07, 0x48, 0x40, 0x17, ++ 0x07, 0x58, 0x48, 0x07, 0x27, 0x1f, 0x17, 0x37, 0x0f, 0x0f, 0x0f, 0x07, 0x40, 0x07, 0x07, ++ 0x48, 0x40, 0x17, 0x07, 0x58, 0x48, 0x07, 0x27, 0x1f, 0x17, 0x37, 0x37, 0x57, 0x2f, 0x48, ++ 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x1f, 0x0f, 0x1f, 0x0f, 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, ++ 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, 0x27, 0x07, 0x48, 0x18, 0x07, 0x07, 0x40, 0x07, 0x00, ++ 0x00, 0x0f, 0x1f, 0x0f, 0x1f, 0x07, 0x1f, 0x07, 0x07, 0x1f, 0x07, 0x07, 0x40, 0x40, 0x40, ++ 0x2f, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x07, 0x07, 0x3e, 0x27, 0x2f, 0x07, 0x27, 0x1f, 0x0f, ++ 0x40, 0x18, 0x10, 0x00, 0x40, 0x57, 0x1f, 0x47, 0x0f, 0x07, 0x1f, 0x08, 0x0f, 0x0f, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x07, 0x07, 0x48, 0x48, 0x60, 0x40, 0x27, 0x07, 0x07, 0x27, 0x40, 0x48, 0x40, ++ 0x40, 0x40, 0x0f, 0x48, 0x68, 0x60, 0x40, 0x68, 0x68, 0x68, 0x68, 0x68, 0x07, 0x07, 0x0f, ++ 0x50, 0x40, 0x60, 0x07, 0x68, 0x27, 0x48, 0x17, 0x40, 0x50, 0x1f, 0x40, 0x40, 0x40, 0x48, ++ 0x48, 0x58, 0x60, 0x60, 0x60, 0x68, 0x68, 0x58, 0x68, 0x60, 0x60, 0x60, 0x68, 0x68, 0x68, ++ 0x60, 0x50, 0x48, 0x50, 0x58, 0x60, 0x60, 0x60, 0x68, 0x68, 0x58, 0x68, 0x60, 0x60, 0x60, ++ 0x68, 0x68, 0x68, 0x60, 0x50, 0x48, 0x50, 0x07, 0x50, 0x58, 0x40, 0x48, 0x40, 0x48, 0x07, ++ 0x48, 0x48, 0x48, 0x68, 0x07, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, ++ 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x40, 0x07, 0x48, 0x48, 0x48, 0x07, 0x48, ++ 0x07, 0x17, 0x17, 0x17, 0x50, 0x17, 0x17, 0x50, 0x40, 0x40, 0x40, 0x2f, 0x2f, 0x17, 0x40, ++ 0x0f, 0x17, 0x1f, 0x1f, 0x1f, 0x27, 0x0f, 0x07, 0x07, 0x0f, 0x07, 0x07, 0x3e, 0x1f, 0x17, ++ 0x40, 0x17, 0x07, 0x1f, 0x48, 0x17, 0x48, 0x40, 0x48, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x07, ++ 0x47, 0x47, 0x5f, 0x40, 0x27, 0x07, 0x07, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f, 0x47, ++ 0x66, 0x5f, 0x00, 0x66, 0x66, 0x66, 0x65, 0x65, 0x07, 0x07, 0x0f, 0x4f, 0x00, 0x5e, 0x07, ++ 0x67, 0x27, 0x47, 0x17, 0x40, 0x4f, 0x1f, 0x40, 0x40, 0x40, 0x47, 0x47, 0x57, 0x5f, 0x5e, ++ 0x5f, 0x66, 0x66, 0x57, 0x67, 0x5f, 0x5e, 0x5f, 0x67, 0x67, 0x66, 0x5e, 0x4f, 0x47, 0x4f, ++ 0x57, 0x5f, 0x5e, 0x5f, 0x66, 0x66, 0x57, 0x67, 0x5f, 0x5e, 0x5f, 0x67, 0x67, 0x66, 0x5e, ++ 0x4f, 0x47, 0x4f, 0x08, 0x4f, 0x56, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x47, 0x47, 0x66, ++ 0x07, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, ++ 0x4f, 0x10, 0x07, 0x40, 0x40, 0x07, 0x47, 0x47, 0x47, 0x08, 0x47, 0x08, 0x17, 0x17, 0x17, ++ 0x4f, 0x17, 0x17, 0x4f, 0x40, 0x40, 0x40, 0x2f, 0x2f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, ++ 0x20, 0x27, 0x10, 0x07, 0x08, 0x10, 0x08, 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1f, ++ 0x47, 0x17, 0x46, 0x00, 0x47, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x06, 0x46, 0x47, 0x5e, 0x40, ++ 0x26, 0x06, 0x06, 0x27, 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f, 0x47, 0x64, 0x5e, 0x01, 0x65, ++ 0x64, 0x64, 0x63, 0x63, 0x07, 0x07, 0x0f, 0x4e, 0x00, 0x5d, 0x07, 0x66, 0x27, 0x46, 0x17, ++ 0x40, 0x4f, 0x1e, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5e, 0x5d, 0x5e, 0x65, 0x64, 0x56, ++ 0x66, 0x5e, 0x5c, 0x5e, 0x66, 0x66, 0x65, 0x5d, 0x4e, 0x46, 0x4e, 0x56, 0x5e, 0x5d, 0x5e, ++ 0x65, 0x64, 0x56, 0x66, 0x5e, 0x5c, 0x5e, 0x66, 0x66, 0x65, 0x5d, 0x4e, 0x46, 0x4e, 0x09, ++ 0x4f, 0x54, 0x40, 0x48, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x64, 0x07, 0x1f, 0x16, 0x4f, ++ 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, ++ 0x40, 0x07, 0x46, 0x46, 0x46, 0x09, 0x46, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, ++ 0x40, 0x40, 0x40, 0x2e, 0x2e, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, ++ 0x09, 0x10, 0x08, 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1e, 0x46, 0x17, 0x45, 0x01, ++ 0x46, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x06, 0x45, 0x47, 0x5e, 0x40, 0x25, 0x06, 0x05, 0x27, ++ 0x40, 0x47, 0x40, 0x40, 0x40, 0x0f, 0x47, 0x63, 0x5d, 0x01, 0x64, 0x63, 0x62, 0x60, 0x60, ++ 0x07, 0x07, 0x0f, 0x4e, 0x00, 0x5c, 0x07, 0x65, 0x27, 0x45, 0x17, 0x40, 0x4f, 0x1d, 0x40, ++ 0x40, 0x40, 0x47, 0x47, 0x56, 0x5d, 0x5c, 0x5d, 0x64, 0x63, 0x56, 0x65, 0x5d, 0x5b, 0x5d, ++ 0x65, 0x65, 0x64, 0x5c, 0x4d, 0x46, 0x4d, 0x56, 0x5d, 0x5c, 0x5d, 0x64, 0x63, 0x56, 0x65, ++ 0x5d, 0x5b, 0x5d, 0x65, 0x65, 0x64, 0x5c, 0x4d, 0x46, 0x4d, 0x09, 0x4f, 0x52, 0x40, 0x48, ++ 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x62, 0x07, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, ++ 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40, 0x07, 0x46, 0x46, ++ 0x45, 0x09, 0x45, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40, 0x40, 0x2d, ++ 0x2d, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, 0x08, 0x07, ++ 0x3d, 0x1f, 0x17, 0x40, 0x17, 0x08, 0x1e, 0x45, 0x17, 0x44, 0x01, 0x45, 0x17, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x07, 0x05, 0x44, 0x46, 0x5d, 0x40, 0x24, 0x05, 0x04, 0x27, 0x40, 0x46, 0x40, 0x40, ++ 0x40, 0x0f, 0x46, 0x61, 0x5c, 0x02, 0x63, 0x61, 0x60, 0x5e, 0x5e, 0x07, 0x07, 0x0e, 0x4d, ++ 0x01, 0x5b, 0x07, 0x64, 0x27, 0x44, 0x16, 0x40, 0x4e, 0x1c, 0x40, 0x40, 0x40, 0x46, 0x46, ++ 0x55, 0x5c, 0x5b, 0x5c, 0x63, 0x61, 0x55, 0x64, 0x5c, 0x59, 0x5c, 0x64, 0x64, 0x63, 0x5b, ++ 0x4c, 0x45, 0x4c, 0x55, 0x5c, 0x5b, 0x5c, 0x63, 0x61, 0x55, 0x64, 0x5c, 0x59, 0x5c, 0x64, ++ 0x64, 0x63, 0x5b, 0x4c, 0x45, 0x4c, 0x0a, 0x4e, 0x50, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, ++ 0x45, 0x45, 0x60, 0x07, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, ++ 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x41, 0x07, 0x45, 0x45, 0x44, 0x0a, 0x44, 0x0a, ++ 0x16, 0x17, 0x15, 0x4e, 0x17, 0x15, 0x4e, 0x40, 0x40, 0x40, 0x2c, 0x2c, 0x16, 0x40, 0x0f, ++ 0x16, 0x1d, 0x1d, 0x21, 0x27, 0x11, 0x07, 0x0a, 0x11, 0x09, 0x06, 0x3c, 0x1e, 0x16, 0x40, ++ 0x16, 0x09, 0x1d, 0x44, 0x16, 0x43, 0x02, 0x44, 0x16, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x04, 0x43, ++ 0x46, 0x5c, 0x40, 0x23, 0x04, 0x03, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f, 0x46, 0x60, ++ 0x5b, 0x03, 0x61, 0x60, 0x5e, 0x5b, 0x5b, 0x07, 0x07, 0x0e, 0x4c, 0x01, 0x59, 0x07, 0x63, ++ 0x27, 0x43, 0x16, 0x40, 0x4e, 0x1b, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5b, 0x59, 0x5b, ++ 0x61, 0x60, 0x54, 0x63, 0x5b, 0x58, 0x5b, 0x63, 0x63, 0x61, 0x59, 0x4b, 0x44, 0x4b, 0x54, ++ 0x5b, 0x59, 0x5b, 0x61, 0x60, 0x54, 0x63, 0x5b, 0x58, 0x5b, 0x63, 0x63, 0x61, 0x59, 0x4b, ++ 0x44, 0x4b, 0x0b, 0x4e, 0x4e, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5e, 0x07, ++ 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, ++ 0x11, 0x07, 0x40, 0x41, 0x07, 0x44, 0x44, 0x43, 0x0b, 0x43, 0x0b, 0x16, 0x17, 0x14, 0x4e, ++ 0x17, 0x14, 0x4e, 0x40, 0x40, 0x40, 0x2b, 0x2b, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, ++ 0x27, 0x11, 0x07, 0x0b, 0x11, 0x09, 0x06, 0x3b, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1c, 0x43, ++ 0x16, 0x41, 0x03, 0x43, 0x16, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x04, 0x42, 0x46, 0x5c, 0x40, 0x22, ++ 0x04, 0x02, 0x27, 0x40, 0x46, 0x40, 0x40, 0x40, 0x0f, 0x46, 0x5e, 0x5a, 0x03, 0x60, 0x5e, ++ 0x5c, 0x59, 0x59, 0x07, 0x07, 0x0e, 0x4c, 0x01, 0x58, 0x07, 0x62, 0x27, 0x42, 0x16, 0x40, ++ 0x4e, 0x1a, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5a, 0x58, 0x5a, 0x60, 0x5e, 0x54, 0x62, ++ 0x5a, 0x56, 0x5a, 0x62, 0x62, 0x60, 0x58, 0x4a, 0x44, 0x4a, 0x54, 0x5a, 0x58, 0x5a, 0x60, ++ 0x5e, 0x54, 0x62, 0x5a, 0x56, 0x5a, 0x62, 0x62, 0x60, 0x58, 0x4a, 0x44, 0x4a, 0x0b, 0x4e, ++ 0x4c, 0x40, 0x48, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5c, 0x07, 0x1e, 0x14, 0x4e, 0x11, ++ 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41, ++ 0x07, 0x44, 0x44, 0x42, 0x0b, 0x42, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, ++ 0x40, 0x40, 0x2a, 0x2a, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, ++ 0x11, 0x09, 0x06, 0x3a, 0x1e, 0x16, 0x40, 0x16, 0x09, 0x1c, 0x42, 0x16, 0x40, 0x03, 0x42, ++ 0x16, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x07, 0x03, 0x41, 0x45, 0x5b, 0x40, 0x21, 0x03, 0x01, 0x27, 0x40, ++ 0x45, 0x40, 0x40, 0x40, 0x0f, 0x45, 0x5d, 0x59, 0x04, 0x5f, 0x5d, 0x5a, 0x56, 0x56, 0x07, ++ 0x07, 0x0d, 0x4b, 0x02, 0x57, 0x07, 0x61, 0x27, 0x41, 0x15, 0x40, 0x4d, 0x19, 0x40, 0x40, ++ 0x40, 0x45, 0x45, 0x53, 0x59, 0x57, 0x59, 0x5f, 0x5d, 0x53, 0x61, 0x59, 0x55, 0x59, 0x61, ++ 0x61, 0x5f, 0x57, 0x49, 0x43, 0x49, 0x53, 0x59, 0x57, 0x59, 0x5f, 0x5d, 0x53, 0x61, 0x59, ++ 0x55, 0x59, 0x61, 0x61, 0x5f, 0x57, 0x49, 0x43, 0x49, 0x0c, 0x4d, 0x4a, 0x40, 0x48, 0x40, ++ 0x45, 0x07, 0x45, 0x43, 0x43, 0x5a, 0x07, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, ++ 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x42, 0x07, 0x43, 0x43, 0x41, ++ 0x0c, 0x41, 0x0c, 0x15, 0x17, 0x13, 0x4d, 0x17, 0x13, 0x4d, 0x40, 0x40, 0x40, 0x29, 0x29, ++ 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x1b, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x0a, 0x05, 0x39, ++ 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1b, 0x41, 0x15, 0x00, 0x04, 0x41, 0x15, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x02, 0x40, 0x45, 0x5b, 0x40, 0x20, 0x02, 0x00, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, ++ 0x0f, 0x45, 0x5b, 0x58, 0x04, 0x5e, 0x5b, 0x59, 0x54, 0x54, 0x07, 0x07, 0x0d, 0x4b, 0x02, ++ 0x56, 0x07, 0x60, 0x27, 0x40, 0x15, 0x40, 0x4d, 0x18, 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, ++ 0x58, 0x56, 0x58, 0x5e, 0x5b, 0x53, 0x60, 0x58, 0x53, 0x58, 0x60, 0x60, 0x5e, 0x56, 0x48, ++ 0x43, 0x48, 0x53, 0x58, 0x56, 0x58, 0x5e, 0x5b, 0x53, 0x60, 0x58, 0x53, 0x58, 0x60, 0x60, ++ 0x5e, 0x56, 0x48, 0x43, 0x48, 0x0c, 0x4d, 0x49, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x43, ++ 0x43, 0x59, 0x07, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, ++ 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42, 0x07, 0x43, 0x43, 0x40, 0x0c, 0x40, 0x0c, 0x15, ++ 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, 0x40, 0x28, 0x28, 0x15, 0x40, 0x0f, 0x15, ++ 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x0a, 0x05, 0x38, 0x1d, 0x15, 0x40, 0x15, ++ 0x0a, 0x1a, 0x40, 0x15, 0x01, 0x04, 0x40, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x02, 0x00, 0x45, ++ 0x5a, 0x40, 0x1f, 0x02, 0x40, 0x27, 0x40, 0x45, 0x40, 0x40, 0x40, 0x0f, 0x45, 0x59, 0x57, ++ 0x05, 0x5c, 0x59, 0x57, 0x51, 0x51, 0x07, 0x07, 0x0d, 0x4a, 0x02, 0x54, 0x07, 0x5f, 0x27, ++ 0x00, 0x15, 0x40, 0x4d, 0x17, 0x40, 0x40, 0x40, 0x45, 0x45, 0x52, 0x57, 0x54, 0x57, 0x5c, ++ 0x59, 0x52, 0x5f, 0x57, 0x51, 0x57, 0x5f, 0x5f, 0x5c, 0x54, 0x47, 0x42, 0x47, 0x52, 0x57, ++ 0x54, 0x57, 0x5c, 0x59, 0x52, 0x5f, 0x57, 0x51, 0x57, 0x5f, 0x5f, 0x5c, 0x54, 0x47, 0x42, ++ 0x47, 0x0d, 0x4d, 0x47, 0x40, 0x48, 0x40, 0x45, 0x07, 0x45, 0x42, 0x42, 0x57, 0x07, 0x1d, ++ 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, ++ 0x07, 0x40, 0x42, 0x07, 0x42, 0x42, 0x00, 0x0d, 0x00, 0x0d, 0x15, 0x17, 0x12, 0x4d, 0x17, ++ 0x12, 0x4d, 0x40, 0x40, 0x40, 0x27, 0x27, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, ++ 0x12, 0x07, 0x0d, 0x12, 0x0a, 0x05, 0x37, 0x1d, 0x15, 0x40, 0x15, 0x0a, 0x1a, 0x00, 0x15, ++ 0x03, 0x05, 0x00, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x01, 0x01, 0x44, 0x59, 0x40, 0x1e, 0x01, ++ 0x41, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f, 0x44, 0x58, 0x56, 0x06, 0x5b, 0x58, 0x55, ++ 0x4f, 0x4f, 0x07, 0x07, 0x0c, 0x49, 0x03, 0x53, 0x07, 0x5e, 0x27, 0x01, 0x14, 0x40, 0x4c, ++ 0x16, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x56, 0x53, 0x56, 0x5b, 0x58, 0x51, 0x5e, 0x56, ++ 0x50, 0x56, 0x5e, 0x5e, 0x5b, 0x53, 0x46, 0x41, 0x46, 0x51, 0x56, 0x53, 0x56, 0x5b, 0x58, ++ 0x51, 0x5e, 0x56, 0x50, 0x56, 0x5e, 0x5e, 0x5b, 0x53, 0x46, 0x41, 0x46, 0x0e, 0x4c, 0x45, ++ 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x55, 0x07, 0x1c, 0x11, 0x4c, 0x13, 0x07, ++ 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, 0x07, ++ 0x41, 0x41, 0x01, 0x0e, 0x01, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, ++ 0x40, 0x26, 0x26, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, ++ 0x0b, 0x04, 0x36, 0x1c, 0x14, 0x40, 0x14, 0x0b, 0x19, 0x01, 0x14, 0x04, 0x06, 0x01, 0x14, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x01, 0x02, 0x44, 0x59, 0x40, 0x1d, 0x01, 0x42, 0x27, 0x40, 0x44, ++ 0x40, 0x40, 0x40, 0x0f, 0x44, 0x56, 0x55, 0x06, 0x5a, 0x56, 0x53, 0x4c, 0x4c, 0x07, 0x07, ++ 0x0c, 0x49, 0x03, 0x52, 0x07, 0x5d, 0x27, 0x02, 0x14, 0x40, 0x4c, 0x15, 0x40, 0x40, 0x40, ++ 0x44, 0x44, 0x51, 0x55, 0x52, 0x55, 0x5a, 0x56, 0x51, 0x5d, 0x55, 0x4e, 0x55, 0x5d, 0x5d, ++ 0x5a, 0x52, 0x45, 0x41, 0x45, 0x51, 0x55, 0x52, 0x55, 0x5a, 0x56, 0x51, 0x5d, 0x55, 0x4e, ++ 0x55, 0x5d, 0x5d, 0x5a, 0x52, 0x45, 0x41, 0x45, 0x0e, 0x4c, 0x43, 0x40, 0x48, 0x40, 0x44, ++ 0x07, 0x44, 0x41, 0x41, 0x53, 0x07, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, ++ 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, 0x07, 0x41, 0x41, 0x02, 0x0e, ++ 0x02, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, 0x40, 0x25, 0x25, 0x14, ++ 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x0b, 0x04, 0x35, 0x1c, ++ 0x14, 0x40, 0x14, 0x0b, 0x19, 0x02, 0x14, 0x05, 0x06, 0x02, 0x14, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x00, 0x03, 0x44, 0x58, 0x40, 0x1c, 0x00, 0x43, 0x27, 0x40, 0x44, 0x40, 0x40, 0x40, 0x0f, ++ 0x44, 0x55, 0x54, 0x07, 0x59, 0x55, 0x51, 0x4a, 0x4a, 0x07, 0x07, 0x0c, 0x48, 0x03, 0x51, ++ 0x07, 0x5c, 0x27, 0x03, 0x14, 0x40, 0x4c, 0x14, 0x40, 0x40, 0x40, 0x44, 0x44, 0x50, 0x54, ++ 0x51, 0x54, 0x59, 0x55, 0x50, 0x5c, 0x54, 0x4d, 0x54, 0x5c, 0x5c, 0x59, 0x51, 0x44, 0x40, ++ 0x44, 0x50, 0x54, 0x51, 0x54, 0x59, 0x55, 0x50, 0x5c, 0x54, 0x4d, 0x54, 0x5c, 0x5c, 0x59, ++ 0x51, 0x44, 0x40, 0x44, 0x0f, 0x4c, 0x41, 0x40, 0x48, 0x40, 0x44, 0x07, 0x44, 0x40, 0x40, ++ 0x51, 0x07, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, ++ 0x10, 0x4c, 0x13, 0x07, 0x40, 0x43, 0x07, 0x40, 0x40, 0x03, 0x0f, 0x03, 0x0f, 0x14, 0x17, ++ 0x10, 0x4c, 0x17, 0x10, 0x4c, 0x40, 0x40, 0x40, 0x24, 0x24, 0x14, 0x40, 0x0f, 0x14, 0x18, ++ 0x18, 0x23, 0x27, 0x13, 0x07, 0x0f, 0x13, 0x0b, 0x04, 0x34, 0x1c, 0x14, 0x40, 0x14, 0x0b, ++ 0x18, 0x03, 0x14, 0x06, 0x07, 0x03, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x40, 0x04, 0x43, 0x57, ++ 0x40, 0x1b, 0x40, 0x44, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, 0x43, 0x53, 0x53, 0x08, ++ 0x57, 0x53, 0x4f, 0x47, 0x47, 0x07, 0x07, 0x0b, 0x47, 0x04, 0x4f, 0x07, 0x5b, 0x27, 0x04, ++ 0x13, 0x40, 0x4b, 0x13, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x53, 0x4f, 0x53, 0x57, 0x53, ++ 0x4f, 0x5b, 0x53, 0x4b, 0x53, 0x5b, 0x5b, 0x57, 0x4f, 0x43, 0x00, 0x43, 0x4f, 0x53, 0x4f, ++ 0x53, 0x57, 0x53, 0x4f, 0x5b, 0x53, 0x4b, 0x53, 0x5b, 0x5b, 0x57, 0x4f, 0x43, 0x00, 0x43, ++ 0x10, 0x4b, 0x00, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4f, 0x07, 0x1b, 0x0f, ++ 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, ++ 0x40, 0x44, 0x07, 0x00, 0x00, 0x04, 0x10, 0x04, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, ++ 0x4b, 0x40, 0x40, 0x40, 0x23, 0x23, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, ++ 0x07, 0x10, 0x14, 0x0c, 0x03, 0x33, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x17, 0x04, 0x13, 0x08, ++ 0x08, 0x04, 0x13, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x40, 0x05, 0x43, 0x57, 0x40, 0x1a, 0x40, 0x45, ++ 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, 0x43, 0x52, 0x52, 0x08, 0x56, 0x52, 0x4d, 0x45, ++ 0x45, 0x07, 0x07, 0x0b, 0x47, 0x04, 0x4e, 0x07, 0x5a, 0x27, 0x05, 0x13, 0x40, 0x4b, 0x12, ++ 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x52, 0x4e, 0x52, 0x56, 0x52, 0x4f, 0x5a, 0x52, 0x4a, ++ 0x52, 0x5a, 0x5a, 0x56, 0x4e, 0x42, 0x00, 0x42, 0x4f, 0x52, 0x4e, 0x52, 0x56, 0x52, 0x4f, ++ 0x5a, 0x52, 0x4a, 0x52, 0x5a, 0x5a, 0x56, 0x4e, 0x42, 0x00, 0x42, 0x10, 0x4b, 0x02, 0x40, ++ 0x48, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4d, 0x07, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, ++ 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44, 0x07, 0x00, ++ 0x00, 0x05, 0x10, 0x05, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, 0x40, 0x40, ++ 0x22, 0x22, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, 0x14, 0x0c, ++ 0x03, 0x32, 0x1b, 0x13, 0x40, 0x13, 0x0c, 0x17, 0x05, 0x13, 0x09, 0x08, 0x05, 0x13, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x07, 0x41, 0x06, 0x43, 0x56, 0x40, 0x19, 0x41, 0x46, 0x27, 0x40, 0x43, 0x40, ++ 0x40, 0x40, 0x0f, 0x43, 0x50, 0x51, 0x09, 0x55, 0x50, 0x4b, 0x42, 0x42, 0x07, 0x07, 0x0b, ++ 0x46, 0x04, 0x4d, 0x07, 0x59, 0x27, 0x06, 0x13, 0x40, 0x4b, 0x11, 0x40, 0x40, 0x40, 0x43, ++ 0x43, 0x4e, 0x51, 0x4d, 0x51, 0x55, 0x50, 0x4e, 0x59, 0x51, 0x48, 0x51, 0x59, 0x59, 0x55, ++ 0x4d, 0x41, 0x01, 0x41, 0x4e, 0x51, 0x4d, 0x51, 0x55, 0x50, 0x4e, 0x59, 0x51, 0x48, 0x51, ++ 0x59, 0x59, 0x55, 0x4d, 0x41, 0x01, 0x41, 0x11, 0x4b, 0x04, 0x40, 0x48, 0x40, 0x43, 0x07, ++ 0x43, 0x01, 0x01, 0x4b, 0x07, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, ++ 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x44, 0x07, 0x01, 0x01, 0x06, 0x11, 0x06, ++ 0x11, 0x13, 0x17, 0x0e, 0x4b, 0x17, 0x0e, 0x4b, 0x40, 0x40, 0x40, 0x21, 0x21, 0x13, 0x40, ++ 0x0f, 0x13, 0x16, 0x16, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x0c, 0x03, 0x31, 0x1b, 0x13, ++ 0x40, 0x13, 0x0c, 0x16, 0x06, 0x13, 0x0a, 0x09, 0x06, 0x13, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x42, ++ 0x06, 0x43, 0x56, 0x40, 0x18, 0x42, 0x47, 0x27, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0f, 0x43, ++ 0x4f, 0x51, 0x09, 0x54, 0x4f, 0x4a, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x46, 0x04, 0x4c, 0x07, ++ 0x59, 0x27, 0x06, 0x12, 0x40, 0x4b, 0x10, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, 0x51, 0x4c, ++ 0x51, 0x54, 0x4f, 0x4e, 0x59, 0x51, 0x47, 0x51, 0x59, 0x59, 0x54, 0x4c, 0x41, 0x01, 0x41, ++ 0x4e, 0x51, 0x4c, 0x51, 0x54, 0x4f, 0x4e, 0x59, 0x51, 0x47, 0x51, 0x59, 0x59, 0x54, 0x4c, ++ 0x41, 0x01, 0x41, 0x11, 0x4b, 0x05, 0x40, 0x48, 0x40, 0x43, 0x07, 0x43, 0x01, 0x01, 0x4a, ++ 0x07, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, ++ 0x4b, 0x14, 0x07, 0x40, 0x45, 0x07, 0x01, 0x01, 0x06, 0x11, 0x06, 0x11, 0x12, 0x17, 0x0d, ++ 0x4b, 0x17, 0x0d, 0x4b, 0x40, 0x40, 0x40, 0x20, 0x20, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, ++ 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x0c, 0x02, 0x30, 0x1a, 0x12, 0x40, 0x12, 0x0c, 0x15, ++ 0x06, 0x12, 0x0b, 0x09, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x42, 0x07, 0x42, 0x55, 0x40, ++ 0x18, 0x42, 0x47, 0x27, 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f, 0x42, 0x4d, 0x50, 0x0a, 0x52, ++ 0x4d, 0x48, 0x02, 0x02, 0x07, 0x07, 0x0a, 0x45, 0x05, 0x4a, 0x07, 0x58, 0x27, 0x07, 0x12, ++ 0x40, 0x4a, 0x10, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4d, 0x50, 0x4a, 0x50, 0x52, 0x4d, 0x4d, ++ 0x58, 0x50, 0x45, 0x50, 0x58, 0x58, 0x52, 0x4a, 0x40, 0x02, 0x40, 0x4d, 0x50, 0x4a, 0x50, ++ 0x52, 0x4d, 0x4d, 0x58, 0x50, 0x45, 0x50, 0x58, 0x58, 0x52, 0x4a, 0x40, 0x02, 0x40, 0x12, ++ 0x4a, 0x07, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, 0x02, 0x02, 0x48, 0x07, 0x1a, 0x0d, 0x4a, ++ 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, ++ 0x45, 0x07, 0x02, 0x02, 0x07, 0x12, 0x07, 0x12, 0x12, 0x17, 0x0d, 0x4a, 0x17, 0x0d, 0x4a, ++ 0x40, 0x40, 0x40, 0x20, 0x20, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x25, 0x27, 0x15, 0x07, ++ 0x12, 0x15, 0x0d, 0x02, 0x30, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x15, 0x07, 0x12, 0x0d, 0x0a, ++ 0x07, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x43, 0x08, 0x42, 0x54, 0x40, 0x17, 0x43, 0x48, 0x27, ++ 0x40, 0x42, 0x40, 0x40, 0x40, 0x0f, 0x42, 0x4b, 0x4f, 0x0b, 0x51, 0x4b, 0x46, 0x04, 0x04, ++ 0x07, 0x07, 0x0a, 0x44, 0x05, 0x49, 0x07, 0x57, 0x27, 0x08, 0x12, 0x40, 0x4a, 0x0f, 0x40, ++ 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4f, 0x49, 0x4f, 0x51, 0x4b, 0x4c, 0x57, 0x4f, 0x43, 0x4f, ++ 0x57, 0x57, 0x51, 0x49, 0x00, 0x03, 0x00, 0x4c, 0x4f, 0x49, 0x4f, 0x51, 0x4b, 0x4c, 0x57, ++ 0x4f, 0x43, 0x4f, 0x57, 0x57, 0x51, 0x49, 0x00, 0x03, 0x00, 0x13, 0x4a, 0x09, 0x40, 0x48, ++ 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x46, 0x07, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, ++ 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, 0x07, 0x03, 0x03, ++ 0x08, 0x13, 0x08, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, 0x40, 0x1f, ++ 0x1f, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0d, 0x02, ++ 0x2f, 0x1a, 0x12, 0x40, 0x12, 0x0d, 0x14, 0x08, 0x12, 0x0e, 0x0b, 0x08, 0x12, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x07, 0x43, 0x09, 0x42, 0x54, 0x40, 0x16, 0x43, 0x49, 0x27, 0x40, 0x42, 0x40, 0x40, ++ 0x40, 0x0f, 0x42, 0x4a, 0x4e, 0x0b, 0x50, 0x4a, 0x44, 0x07, 0x07, 0x07, 0x07, 0x0a, 0x44, ++ 0x05, 0x48, 0x07, 0x56, 0x27, 0x09, 0x12, 0x40, 0x4a, 0x0e, 0x40, 0x40, 0x40, 0x42, 0x42, ++ 0x4c, 0x4e, 0x48, 0x4e, 0x50, 0x4a, 0x4c, 0x56, 0x4e, 0x42, 0x4e, 0x56, 0x56, 0x50, 0x48, ++ 0x01, 0x03, 0x01, 0x4c, 0x4e, 0x48, 0x4e, 0x50, 0x4a, 0x4c, 0x56, 0x4e, 0x42, 0x4e, 0x56, ++ 0x56, 0x50, 0x48, 0x01, 0x03, 0x01, 0x13, 0x4a, 0x0b, 0x40, 0x48, 0x40, 0x42, 0x07, 0x42, ++ 0x03, 0x03, 0x44, 0x07, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, ++ 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, 0x07, 0x03, 0x03, 0x09, 0x13, 0x09, 0x13, ++ 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, 0x40, 0x1e, 0x1e, 0x12, 0x40, 0x0f, ++ 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0d, 0x02, 0x2e, 0x1a, 0x12, 0x40, ++ 0x12, 0x0d, 0x14, 0x09, 0x12, 0x0f, 0x0b, 0x09, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x44, 0x0a, ++ 0x41, 0x53, 0x40, 0x15, 0x44, 0x4a, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f, 0x41, 0x48, ++ 0x4d, 0x0c, 0x4f, 0x48, 0x42, 0x09, 0x09, 0x07, 0x07, 0x09, 0x43, 0x06, 0x47, 0x07, 0x55, ++ 0x27, 0x0a, 0x11, 0x40, 0x49, 0x0d, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4d, 0x47, 0x4d, ++ 0x4f, 0x48, 0x4b, 0x55, 0x4d, 0x40, 0x4d, 0x55, 0x55, 0x4f, 0x47, 0x02, 0x04, 0x02, 0x4b, ++ 0x4d, 0x47, 0x4d, 0x4f, 0x48, 0x4b, 0x55, 0x4d, 0x40, 0x4d, 0x55, 0x55, 0x4f, 0x47, 0x02, ++ 0x04, 0x02, 0x14, 0x49, 0x0d, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x04, 0x04, 0x42, 0x07, ++ 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, ++ 0x16, 0x07, 0x40, 0x46, 0x07, 0x04, 0x04, 0x0a, 0x14, 0x0a, 0x14, 0x11, 0x17, 0x0b, 0x49, ++ 0x17, 0x0b, 0x49, 0x40, 0x40, 0x40, 0x1d, 0x1d, 0x11, 0x40, 0x0f, 0x11, 0x13, 0x13, 0x26, ++ 0x27, 0x16, 0x07, 0x14, 0x16, 0x0e, 0x01, 0x2d, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x13, 0x0a, ++ 0x11, 0x10, 0x0c, 0x0a, 0x11, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x45, 0x0b, 0x41, 0x52, 0x40, 0x14, ++ 0x45, 0x4b, 0x27, 0x40, 0x41, 0x40, 0x40, 0x40, 0x0f, 0x41, 0x47, 0x4c, 0x0d, 0x4d, 0x47, ++ 0x40, 0x0c, 0x0c, 0x07, 0x07, 0x09, 0x42, 0x06, 0x45, 0x07, 0x54, 0x27, 0x0b, 0x11, 0x40, ++ 0x49, 0x0c, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4c, 0x45, 0x4c, 0x4d, 0x47, 0x4a, 0x54, ++ 0x4c, 0x00, 0x4c, 0x54, 0x54, 0x4d, 0x45, 0x03, 0x05, 0x03, 0x4a, 0x4c, 0x45, 0x4c, 0x4d, ++ 0x47, 0x4a, 0x54, 0x4c, 0x00, 0x4c, 0x54, 0x54, 0x4d, 0x45, 0x03, 0x05, 0x03, 0x15, 0x49, ++ 0x0f, 0x40, 0x48, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x40, 0x07, 0x19, 0x0a, 0x49, 0x16, ++ 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, ++ 0x07, 0x05, 0x05, 0x0b, 0x15, 0x0b, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, ++ 0x40, 0x40, 0x1c, 0x1c, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, ++ 0x16, 0x0e, 0x01, 0x2c, 0x19, 0x11, 0x40, 0x11, 0x0e, 0x12, 0x0b, 0x11, 0x12, 0x0d, 0x0b, ++ 0x11, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x07, 0x45, 0x0c, 0x41, 0x52, 0x40, 0x13, 0x45, 0x4c, 0x27, 0x40, ++ 0x41, 0x40, 0x40, 0x40, 0x0f, 0x41, 0x45, 0x4b, 0x0d, 0x4c, 0x45, 0x01, 0x0e, 0x0e, 0x07, ++ 0x07, 0x09, 0x42, 0x06, 0x44, 0x07, 0x53, 0x27, 0x0c, 0x11, 0x40, 0x49, 0x0b, 0x40, 0x40, ++ 0x40, 0x41, 0x41, 0x4a, 0x4b, 0x44, 0x4b, 0x4c, 0x45, 0x4a, 0x53, 0x4b, 0x02, 0x4b, 0x53, ++ 0x53, 0x4c, 0x44, 0x04, 0x05, 0x04, 0x4a, 0x4b, 0x44, 0x4b, 0x4c, 0x45, 0x4a, 0x53, 0x4b, ++ 0x02, 0x4b, 0x53, 0x53, 0x4c, 0x44, 0x04, 0x05, 0x04, 0x15, 0x49, 0x11, 0x40, 0x48, 0x40, ++ 0x41, 0x07, 0x41, 0x05, 0x05, 0x01, 0x07, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, ++ 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, 0x07, 0x05, 0x05, 0x0c, ++ 0x15, 0x0c, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40, 0x40, 0x1b, 0x1b, ++ 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0e, 0x01, 0x2b, ++ 0x19, 0x11, 0x40, 0x11, 0x0e, 0x12, 0x0c, 0x11, 0x13, 0x0d, 0x0c, 0x11, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x46, 0x0d, 0x40, 0x51, 0x40, 0x12, 0x46, 0x4d, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x0f, 0x40, 0x44, 0x4a, 0x0e, 0x4b, 0x44, 0x03, 0x11, 0x11, 0x07, 0x07, 0x08, 0x41, 0x07, ++ 0x43, 0x07, 0x52, 0x27, 0x0d, 0x10, 0x40, 0x48, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, ++ 0x4a, 0x43, 0x4a, 0x4b, 0x44, 0x49, 0x52, 0x4a, 0x03, 0x4a, 0x52, 0x52, 0x4b, 0x43, 0x05, ++ 0x06, 0x05, 0x49, 0x4a, 0x43, 0x4a, 0x4b, 0x44, 0x49, 0x52, 0x4a, 0x03, 0x4a, 0x52, 0x52, ++ 0x4b, 0x43, 0x05, 0x06, 0x05, 0x16, 0x48, 0x13, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x06, ++ 0x06, 0x03, 0x07, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, ++ 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x47, 0x07, 0x06, 0x06, 0x0d, 0x16, 0x0d, 0x16, 0x10, ++ 0x17, 0x09, 0x48, 0x17, 0x09, 0x48, 0x40, 0x40, 0x40, 0x1a, 0x1a, 0x10, 0x40, 0x0f, 0x10, ++ 0x11, 0x11, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0f, 0x00, 0x2a, 0x18, 0x10, 0x40, 0x10, ++ 0x0f, 0x11, 0x0d, 0x10, 0x14, 0x0e, 0x0d, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x47, 0x0e, 0x40, ++ 0x51, 0x40, 0x11, 0x47, 0x4e, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x42, 0x49, ++ 0x0e, 0x4a, 0x42, 0x04, 0x13, 0x13, 0x07, 0x07, 0x08, 0x41, 0x07, 0x42, 0x07, 0x51, 0x27, ++ 0x0e, 0x10, 0x40, 0x48, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x42, 0x49, 0x4a, ++ 0x42, 0x49, 0x51, 0x49, 0x05, 0x49, 0x51, 0x51, 0x4a, 0x42, 0x06, 0x06, 0x06, 0x49, 0x49, ++ 0x42, 0x49, 0x4a, 0x42, 0x49, 0x51, 0x49, 0x05, 0x49, 0x51, 0x51, 0x4a, 0x42, 0x06, 0x06, ++ 0x06, 0x16, 0x48, 0x14, 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x04, 0x07, 0x18, ++ 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, ++ 0x07, 0x40, 0x47, 0x07, 0x06, 0x06, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x08, 0x48, 0x17, ++ 0x08, 0x48, 0x40, 0x40, 0x40, 0x19, 0x19, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, ++ 0x17, 0x07, 0x16, 0x17, 0x0f, 0x00, 0x29, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x10, 0x0e, 0x10, ++ 0x15, 0x0e, 0x0e, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x47, 0x0f, 0x40, 0x50, 0x40, 0x10, 0x47, ++ 0x4f, 0x27, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x48, 0x0f, 0x48, 0x40, 0x06, ++ 0x16, 0x16, 0x07, 0x07, 0x08, 0x40, 0x07, 0x40, 0x07, 0x50, 0x27, 0x0f, 0x10, 0x40, 0x48, ++ 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48, 0x48, 0x40, 0x48, 0x50, 0x48, ++ 0x07, 0x48, 0x50, 0x50, 0x48, 0x40, 0x07, 0x07, 0x07, 0x48, 0x48, 0x40, 0x48, 0x48, 0x40, ++ 0x48, 0x50, 0x48, 0x07, 0x48, 0x50, 0x50, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x48, 0x16, ++ 0x40, 0x48, 0x40, 0x40, 0x07, 0x40, 0x07, 0x07, 0x06, 0x07, 0x18, 0x08, 0x48, 0x17, 0x07, ++ 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x47, 0x07, ++ 0x07, 0x07, 0x0f, 0x17, 0x0f, 0x17, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, 0x40, 0x40, ++ 0x40, 0x18, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, 0x17, 0x17, ++ 0x0f, 0x00, 0x28, 0x18, 0x10, 0x40, 0x10, 0x0f, 0x10, 0x0f, 0x10, 0x17, 0x0f, 0x0f, 0x10, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x48, 0x10, 0x00, 0x4f, 0x40, 0x0f, 0x48, 0x50, 0x27, 0x40, 0x00, ++ 0x40, 0x40, 0x40, 0x0f, 0x00, 0x00, 0x47, 0x10, 0x47, 0x00, 0x08, 0x18, 0x18, 0x07, 0x07, ++ 0x07, 0x00, 0x08, 0x00, 0x07, 0x4f, 0x27, 0x10, 0x0f, 0x40, 0x47, 0x07, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x47, 0x47, 0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x47, 0x08, 0x47, 0x4f, 0x4f, ++ 0x47, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47, 0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x47, 0x08, ++ 0x47, 0x4f, 0x4f, 0x47, 0x00, 0x08, 0x08, 0x08, 0x18, 0x47, 0x18, 0x40, 0x48, 0x40, 0x00, ++ 0x07, 0x00, 0x08, 0x08, 0x08, 0x07, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, ++ 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, 0x07, 0x08, 0x08, 0x10, 0x18, ++ 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, 0x40, 0x17, 0x17, 0x0f, ++ 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, 0x40, 0x27, 0x17, ++ 0x0f, 0x40, 0x0f, 0x10, 0x0f, 0x10, 0x0f, 0x18, 0x10, 0x10, 0x0f, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x48, 0x11, 0x00, 0x4f, 0x40, 0x0e, 0x48, 0x51, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f, ++ 0x00, 0x02, 0x46, 0x10, 0x46, 0x02, 0x0a, 0x1b, 0x1b, 0x07, 0x07, 0x07, 0x00, 0x08, 0x01, ++ 0x07, 0x4e, 0x27, 0x11, 0x0f, 0x40, 0x47, 0x06, 0x40, 0x40, 0x40, 0x00, 0x00, 0x47, 0x46, ++ 0x01, 0x46, 0x46, 0x02, 0x47, 0x4e, 0x46, 0x0a, 0x46, 0x4e, 0x4e, 0x46, 0x01, 0x09, 0x08, ++ 0x09, 0x47, 0x46, 0x01, 0x46, 0x46, 0x02, 0x47, 0x4e, 0x46, 0x0a, 0x46, 0x4e, 0x4e, 0x46, ++ 0x01, 0x09, 0x08, 0x09, 0x18, 0x47, 0x1a, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, ++ 0x0a, 0x07, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, ++ 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, 0x07, 0x08, 0x08, 0x11, 0x18, 0x11, 0x18, 0x0f, 0x17, ++ 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, 0x40, 0x16, 0x16, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, ++ 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, 0x40, 0x26, 0x17, 0x0f, 0x40, 0x0f, 0x10, ++ 0x0f, 0x11, 0x0f, 0x19, 0x10, 0x11, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x49, 0x12, 0x00, 0x4e, ++ 0x40, 0x0d, 0x49, 0x52, 0x27, 0x40, 0x00, 0x40, 0x40, 0x40, 0x0f, 0x00, 0x03, 0x45, 0x11, ++ 0x45, 0x03, 0x0c, 0x1d, 0x1d, 0x07, 0x07, 0x07, 0x01, 0x08, 0x02, 0x07, 0x4d, 0x27, 0x12, ++ 0x0f, 0x40, 0x47, 0x05, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x45, 0x02, 0x45, 0x45, 0x03, ++ 0x46, 0x4d, 0x45, 0x0b, 0x45, 0x4d, 0x4d, 0x45, 0x02, 0x0a, 0x09, 0x0a, 0x46, 0x45, 0x02, ++ 0x45, 0x45, 0x03, 0x46, 0x4d, 0x45, 0x0b, 0x45, 0x4d, 0x4d, 0x45, 0x02, 0x0a, 0x09, 0x0a, ++ 0x19, 0x47, 0x1c, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x09, 0x09, 0x0c, 0x07, 0x17, 0x06, ++ 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, ++ 0x40, 0x48, 0x07, 0x09, 0x09, 0x12, 0x19, 0x12, 0x19, 0x0f, 0x17, 0x06, 0x47, 0x17, 0x06, ++ 0x47, 0x40, 0x40, 0x40, 0x15, 0x15, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x0e, 0x28, 0x27, 0x18, ++ 0x07, 0x19, 0x18, 0x10, 0x40, 0x25, 0x17, 0x0f, 0x40, 0x0f, 0x10, 0x0e, 0x12, 0x0f, 0x1a, ++ 0x11, 0x12, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x4a, 0x13, 0x01, 0x4d, 0x40, 0x0c, 0x4a, 0x53, ++ 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, 0x01, 0x05, 0x44, 0x12, 0x43, 0x05, 0x0e, 0x20, ++ 0x20, 0x07, 0x07, 0x06, 0x02, 0x09, 0x04, 0x07, 0x4c, 0x27, 0x13, 0x0e, 0x40, 0x46, 0x04, ++ 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x44, 0x04, 0x44, 0x43, 0x05, 0x45, 0x4c, 0x44, 0x0d, ++ 0x44, 0x4c, 0x4c, 0x43, 0x04, 0x0b, 0x0a, 0x0b, 0x45, 0x44, 0x04, 0x44, 0x43, 0x05, 0x45, ++ 0x4c, 0x44, 0x0d, 0x44, 0x4c, 0x4c, 0x43, 0x04, 0x0b, 0x0a, 0x0b, 0x1a, 0x46, 0x1e, 0x40, ++ 0x48, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x0e, 0x07, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, ++ 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, 0x07, 0x0a, ++ 0x0a, 0x13, 0x1a, 0x13, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, 0x40, ++ 0x14, 0x14, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x11, ++ 0x41, 0x24, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0d, 0x13, 0x0e, 0x1c, 0x12, 0x13, 0x0e, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x07, 0x4a, 0x14, 0x01, 0x4d, 0x40, 0x0b, 0x4a, 0x54, 0x27, 0x40, 0x01, 0x40, ++ 0x40, 0x40, 0x0f, 0x01, 0x06, 0x43, 0x12, 0x42, 0x06, 0x10, 0x22, 0x22, 0x07, 0x07, 0x06, ++ 0x02, 0x09, 0x05, 0x07, 0x4b, 0x27, 0x14, 0x0e, 0x40, 0x46, 0x03, 0x40, 0x40, 0x40, 0x01, ++ 0x01, 0x45, 0x43, 0x05, 0x43, 0x42, 0x06, 0x45, 0x4b, 0x43, 0x0e, 0x43, 0x4b, 0x4b, 0x42, ++ 0x05, 0x0c, 0x0a, 0x0c, 0x45, 0x43, 0x05, 0x43, 0x42, 0x06, 0x45, 0x4b, 0x43, 0x0e, 0x43, ++ 0x4b, 0x4b, 0x42, 0x05, 0x0c, 0x0a, 0x0c, 0x1a, 0x46, 0x20, 0x40, 0x48, 0x40, 0x01, 0x07, ++ 0x01, 0x0a, 0x0a, 0x10, 0x07, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, ++ 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, 0x07, 0x0a, 0x0a, 0x14, 0x1a, 0x14, ++ 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, 0x40, 0x13, 0x13, 0x0e, 0x40, ++ 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x11, 0x41, 0x23, 0x16, 0x0e, ++ 0x40, 0x0e, 0x11, 0x0d, 0x14, 0x0e, 0x1d, 0x12, 0x14, 0x0e, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x4b, ++ 0x15, 0x01, 0x4c, 0x40, 0x0a, 0x4b, 0x55, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, 0x01, ++ 0x08, 0x42, 0x13, 0x41, 0x08, 0x12, 0x25, 0x25, 0x07, 0x07, 0x06, 0x03, 0x09, 0x06, 0x07, ++ 0x4a, 0x27, 0x15, 0x0e, 0x40, 0x46, 0x02, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x06, ++ 0x42, 0x41, 0x08, 0x44, 0x4a, 0x42, 0x10, 0x42, 0x4a, 0x4a, 0x41, 0x06, 0x0d, 0x0b, 0x0d, ++ 0x44, 0x42, 0x06, 0x42, 0x41, 0x08, 0x44, 0x4a, 0x42, 0x10, 0x42, 0x4a, 0x4a, 0x41, 0x06, ++ 0x0d, 0x0b, 0x0d, 0x1b, 0x46, 0x22, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x12, ++ 0x07, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, ++ 0x46, 0x19, 0x07, 0x40, 0x49, 0x07, 0x0b, 0x0b, 0x15, 0x1b, 0x15, 0x1b, 0x0e, 0x17, 0x04, ++ 0x46, 0x17, 0x04, 0x46, 0x40, 0x40, 0x40, 0x12, 0x12, 0x0e, 0x40, 0x0f, 0x0e, 0x0c, 0x0c, ++ 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x11, 0x41, 0x22, 0x16, 0x0e, 0x40, 0x0e, 0x11, 0x0c, ++ 0x15, 0x0e, 0x1e, 0x13, 0x15, 0x0e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x4c, 0x15, 0x01, 0x4c, 0x40, ++ 0x09, 0x4c, 0x56, 0x27, 0x40, 0x01, 0x40, 0x40, 0x40, 0x0f, 0x01, 0x09, 0x42, 0x13, 0x40, ++ 0x09, 0x13, 0x27, 0x27, 0x07, 0x07, 0x05, 0x03, 0x09, 0x07, 0x07, 0x4a, 0x27, 0x15, 0x0d, ++ 0x40, 0x46, 0x01, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x07, 0x42, 0x40, 0x09, 0x44, ++ 0x4a, 0x42, 0x11, 0x42, 0x4a, 0x4a, 0x40, 0x07, 0x0d, 0x0b, 0x0d, 0x44, 0x42, 0x07, 0x42, ++ 0x40, 0x09, 0x44, 0x4a, 0x42, 0x11, 0x42, 0x4a, 0x4a, 0x40, 0x07, 0x0d, 0x0b, 0x0d, 0x1b, ++ 0x46, 0x23, 0x40, 0x48, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x13, 0x07, 0x15, 0x03, 0x46, ++ 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, ++ 0x4a, 0x07, 0x0b, 0x0b, 0x15, 0x1b, 0x15, 0x1b, 0x0d, 0x17, 0x03, 0x46, 0x17, 0x03, 0x46, ++ 0x40, 0x40, 0x40, 0x11, 0x11, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x29, 0x27, 0x19, 0x07, ++ 0x1b, 0x19, 0x11, 0x42, 0x21, 0x15, 0x0d, 0x40, 0x0d, 0x11, 0x0b, 0x15, 0x0d, 0x1f, 0x13, ++ 0x15, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x4c, 0x16, 0x02, 0x4b, 0x40, 0x09, 0x4c, 0x56, 0x27, ++ 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f, 0x02, 0x0b, 0x41, 0x14, 0x01, 0x0b, 0x15, 0x2a, 0x2a, ++ 0x07, 0x07, 0x05, 0x04, 0x0a, 0x09, 0x07, 0x49, 0x27, 0x16, 0x0d, 0x40, 0x45, 0x01, 0x40, ++ 0x40, 0x40, 0x02, 0x02, 0x43, 0x41, 0x09, 0x41, 0x01, 0x0b, 0x43, 0x49, 0x41, 0x13, 0x41, ++ 0x49, 0x49, 0x01, 0x09, 0x0e, 0x0c, 0x0e, 0x43, 0x41, 0x09, 0x41, 0x01, 0x0b, 0x43, 0x49, ++ 0x41, 0x13, 0x41, 0x49, 0x49, 0x01, 0x09, 0x0e, 0x0c, 0x0e, 0x1c, 0x45, 0x25, 0x40, 0x48, ++ 0x40, 0x02, 0x07, 0x02, 0x0c, 0x0c, 0x15, 0x07, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, ++ 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x4a, 0x07, 0x0c, 0x0c, ++ 0x16, 0x1c, 0x16, 0x1c, 0x0d, 0x17, 0x03, 0x45, 0x17, 0x03, 0x45, 0x40, 0x40, 0x40, 0x11, ++ 0x11, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x2a, 0x27, 0x1a, 0x07, 0x1c, 0x1a, 0x12, 0x42, ++ 0x21, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0b, 0x16, 0x0d, 0x21, 0x14, 0x16, 0x0d, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x07, 0x4d, 0x17, 0x02, 0x4a, 0x40, 0x08, 0x4d, 0x57, 0x27, 0x40, 0x02, 0x40, 0x40, ++ 0x40, 0x0f, 0x02, 0x0d, 0x40, 0x15, 0x02, 0x0d, 0x17, 0x2c, 0x2c, 0x07, 0x07, 0x05, 0x05, ++ 0x0a, 0x0a, 0x07, 0x48, 0x27, 0x17, 0x0d, 0x40, 0x45, 0x00, 0x40, 0x40, 0x40, 0x02, 0x02, ++ 0x42, 0x40, 0x0a, 0x40, 0x02, 0x0d, 0x42, 0x48, 0x40, 0x15, 0x40, 0x48, 0x48, 0x02, 0x0a, ++ 0x0f, 0x0d, 0x0f, 0x42, 0x40, 0x0a, 0x40, 0x02, 0x0d, 0x42, 0x48, 0x40, 0x15, 0x40, 0x48, ++ 0x48, 0x02, 0x0a, 0x0f, 0x0d, 0x0f, 0x1d, 0x45, 0x27, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, ++ 0x0d, 0x0d, 0x17, 0x07, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, ++ 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, 0x07, 0x0d, 0x0d, 0x17, 0x1d, 0x17, 0x1d, ++ 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, 0x40, 0x10, 0x10, 0x0d, 0x40, 0x0f, ++ 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x12, 0x42, 0x20, 0x15, 0x0d, 0x40, ++ 0x0d, 0x12, 0x0a, 0x17, 0x0d, 0x22, 0x15, 0x17, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x4d, 0x18, ++ 0x02, 0x4a, 0x40, 0x07, 0x4d, 0x58, 0x27, 0x40, 0x02, 0x40, 0x40, 0x40, 0x0f, 0x02, 0x0e, ++ 0x00, 0x15, 0x03, 0x0e, 0x19, 0x2f, 0x2f, 0x07, 0x07, 0x05, 0x05, 0x0a, 0x0b, 0x07, 0x47, ++ 0x27, 0x18, 0x0d, 0x40, 0x45, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x00, 0x0b, 0x00, ++ 0x03, 0x0e, 0x42, 0x47, 0x00, 0x16, 0x00, 0x47, 0x47, 0x03, 0x0b, 0x10, 0x0d, 0x10, 0x42, ++ 0x00, 0x0b, 0x00, 0x03, 0x0e, 0x42, 0x47, 0x00, 0x16, 0x00, 0x47, 0x47, 0x03, 0x0b, 0x10, ++ 0x0d, 0x10, 0x1d, 0x45, 0x29, 0x40, 0x48, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, 0x19, 0x07, ++ 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, ++ 0x1a, 0x07, 0x40, 0x4a, 0x07, 0x0d, 0x0d, 0x18, 0x1d, 0x18, 0x1d, 0x0d, 0x17, 0x02, 0x45, ++ 0x17, 0x02, 0x45, 0x40, 0x40, 0x40, 0x0f, 0x0f, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, ++ 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x12, 0x42, 0x1f, 0x15, 0x0d, 0x40, 0x0d, 0x12, 0x0a, 0x18, ++ 0x0d, 0x23, 0x15, 0x18, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x4e, 0x19, 0x03, 0x49, 0x40, 0x06, ++ 0x4e, 0x59, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, 0x0f, 0x03, 0x10, 0x01, 0x16, 0x04, 0x10, ++ 0x1b, 0x31, 0x31, 0x07, 0x07, 0x04, 0x06, 0x0b, 0x0c, 0x07, 0x46, 0x27, 0x19, 0x0c, 0x40, ++ 0x44, 0x41, 0x40, 0x40, 0x40, 0x03, 0x03, 0x41, 0x01, 0x0c, 0x01, 0x04, 0x10, 0x41, 0x46, ++ 0x01, 0x18, 0x01, 0x46, 0x46, 0x04, 0x0c, 0x11, 0x0e, 0x11, 0x41, 0x01, 0x0c, 0x01, 0x04, ++ 0x10, 0x41, 0x46, 0x01, 0x18, 0x01, 0x46, 0x46, 0x04, 0x0c, 0x11, 0x0e, 0x11, 0x1e, 0x44, ++ 0x2b, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0e, 0x0e, 0x1b, 0x07, 0x14, 0x01, 0x44, 0x1b, ++ 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x4b, ++ 0x07, 0x0e, 0x0e, 0x19, 0x1e, 0x19, 0x1e, 0x0c, 0x17, 0x01, 0x44, 0x17, 0x01, 0x44, 0x40, ++ 0x40, 0x40, 0x0e, 0x0e, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x09, 0x2b, 0x27, 0x1b, 0x07, 0x1e, ++ 0x1b, 0x13, 0x43, 0x1e, 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x09, 0x19, 0x0c, 0x24, 0x16, 0x19, ++ 0x0c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x07, 0x4f, 0x1a, 0x03, 0x48, 0x40, 0x05, 0x4f, 0x5a, 0x27, 0x40, ++ 0x03, 0x40, 0x40, 0x40, 0x0f, 0x03, 0x11, 0x02, 0x17, 0x06, 0x11, 0x1d, 0x34, 0x34, 0x07, ++ 0x07, 0x04, 0x07, 0x0b, 0x0e, 0x07, 0x45, 0x27, 0x1a, 0x0c, 0x40, 0x44, 0x42, 0x40, 0x40, ++ 0x40, 0x03, 0x03, 0x40, 0x02, 0x0e, 0x02, 0x06, 0x11, 0x40, 0x45, 0x02, 0x19, 0x02, 0x45, ++ 0x45, 0x06, 0x0e, 0x12, 0x0f, 0x12, 0x40, 0x02, 0x0e, 0x02, 0x06, 0x11, 0x40, 0x45, 0x02, ++ 0x19, 0x02, 0x45, 0x45, 0x06, 0x0e, 0x12, 0x0f, 0x12, 0x1f, 0x44, 0x2d, 0x40, 0x48, 0x40, ++ 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1d, 0x07, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, ++ 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, 0x07, 0x0f, 0x0f, 0x1a, ++ 0x1f, 0x1a, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, 0x40, 0x0d, 0x0d, ++ 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x13, 0x43, 0x1d, ++ 0x14, 0x0c, 0x40, 0x0c, 0x13, 0x08, 0x1a, 0x0c, 0x26, 0x17, 0x1a, 0x0c, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x4f, 0x1b, 0x03, 0x48, 0x40, 0x04, 0x4f, 0x5b, 0x27, 0x40, 0x03, 0x40, 0x40, 0x40, ++ 0x0f, 0x03, 0x13, 0x03, 0x17, 0x07, 0x13, 0x1f, 0x36, 0x36, 0x07, 0x07, 0x04, 0x07, 0x0b, ++ 0x0f, 0x07, 0x44, 0x27, 0x1b, 0x0c, 0x40, 0x44, 0x43, 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, ++ 0x03, 0x0f, 0x03, 0x07, 0x13, 0x40, 0x44, 0x03, 0x1b, 0x03, 0x44, 0x44, 0x07, 0x0f, 0x13, ++ 0x0f, 0x13, 0x40, 0x03, 0x0f, 0x03, 0x07, 0x13, 0x40, 0x44, 0x03, 0x1b, 0x03, 0x44, 0x44, ++ 0x07, 0x0f, 0x13, 0x0f, 0x13, 0x1f, 0x44, 0x2f, 0x40, 0x48, 0x40, 0x03, 0x07, 0x03, 0x0f, ++ 0x0f, 0x1f, 0x07, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, ++ 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, 0x07, 0x0f, 0x0f, 0x1b, 0x1f, 0x1b, 0x1f, 0x0c, ++ 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, 0x40, 0x0c, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, ++ 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x13, 0x43, 0x1c, 0x14, 0x0c, 0x40, 0x0c, ++ 0x13, 0x08, 0x1b, 0x0c, 0x27, 0x17, 0x1b, 0x0c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x50, 0x1c, 0x04, ++ 0x47, 0x40, 0x03, 0x50, 0x5c, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, 0x04, 0x14, 0x04, ++ 0x18, 0x08, 0x14, 0x21, 0x39, 0x39, 0x07, 0x07, 0x03, 0x08, 0x0c, 0x10, 0x07, 0x43, 0x27, ++ 0x1c, 0x0b, 0x40, 0x43, 0x44, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x04, 0x10, 0x04, 0x08, ++ 0x14, 0x00, 0x43, 0x04, 0x1c, 0x04, 0x43, 0x43, 0x08, 0x10, 0x14, 0x10, 0x14, 0x00, 0x04, ++ 0x10, 0x04, 0x08, 0x14, 0x00, 0x43, 0x04, 0x1c, 0x04, 0x43, 0x43, 0x08, 0x10, 0x14, 0x10, ++ 0x14, 0x20, 0x43, 0x31, 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x21, 0x07, 0x13, ++ 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, ++ 0x07, 0x40, 0x4c, 0x07, 0x10, 0x10, 0x1c, 0x20, 0x1c, 0x20, 0x0b, 0x17, 0x40, 0x43, 0x17, ++ 0x40, 0x43, 0x40, 0x40, 0x40, 0x0b, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x07, 0x2c, 0x27, ++ 0x1c, 0x07, 0x20, 0x1c, 0x14, 0x44, 0x1b, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x07, 0x1c, 0x0b, ++ 0x28, 0x18, 0x1c, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x51, 0x1d, 0x04, 0x47, 0x40, 0x02, 0x51, ++ 0x5d, 0x27, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, 0x04, 0x16, 0x05, 0x18, 0x09, 0x16, 0x22, ++ 0x3b, 0x3b, 0x07, 0x07, 0x03, 0x08, 0x0c, 0x11, 0x07, 0x42, 0x27, 0x1d, 0x0b, 0x40, 0x43, ++ 0x45, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x05, 0x11, 0x05, 0x09, 0x16, 0x00, 0x42, 0x05, ++ 0x1e, 0x05, 0x42, 0x42, 0x09, 0x11, 0x15, 0x10, 0x15, 0x00, 0x05, 0x11, 0x05, 0x09, 0x16, ++ 0x00, 0x42, 0x05, 0x1e, 0x05, 0x42, 0x42, 0x09, 0x11, 0x15, 0x10, 0x15, 0x20, 0x43, 0x32, ++ 0x40, 0x48, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x22, 0x07, 0x13, 0x41, 0x43, 0x1c, 0x07, ++ 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, 0x07, ++ 0x10, 0x10, 0x1d, 0x20, 0x1d, 0x20, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, ++ 0x40, 0x0a, 0x0a, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, ++ 0x14, 0x44, 0x1a, 0x13, 0x0b, 0x40, 0x0b, 0x14, 0x06, 0x1d, 0x0b, 0x29, 0x18, 0x1d, 0x0b, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x51, 0x1e, 0x04, 0x46, 0x40, 0x01, 0x51, 0x5e, 0x27, 0x40, 0x04, ++ 0x40, 0x40, 0x40, 0x0f, 0x04, 0x18, 0x06, 0x19, 0x0b, 0x18, 0x24, 0x3e, 0x3e, 0x07, 0x07, ++ 0x03, 0x09, 0x0c, 0x13, 0x07, 0x41, 0x27, 0x1e, 0x0b, 0x40, 0x43, 0x46, 0x40, 0x40, 0x40, ++ 0x04, 0x04, 0x01, 0x06, 0x13, 0x06, 0x0b, 0x18, 0x01, 0x41, 0x06, 0x20, 0x06, 0x41, 0x41, ++ 0x0b, 0x13, 0x16, 0x11, 0x16, 0x01, 0x06, 0x13, 0x06, 0x0b, 0x18, 0x01, 0x41, 0x06, 0x20, ++ 0x06, 0x41, 0x41, 0x0b, 0x13, 0x16, 0x11, 0x16, 0x21, 0x43, 0x34, 0x40, 0x48, 0x40, 0x04, ++ 0x07, 0x04, 0x11, 0x11, 0x24, 0x07, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, ++ 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, 0x07, 0x11, 0x11, 0x1e, 0x21, ++ 0x1e, 0x21, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, 0x40, 0x09, 0x09, 0x0b, ++ 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x21, 0x1c, 0x14, 0x44, 0x19, 0x13, ++ 0x0b, 0x40, 0x0b, 0x14, 0x06, 0x1e, 0x0b, 0x2b, 0x19, 0x1e, 0x0b, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x52, 0x1f, 0x05, 0x45, 0x40, 0x00, 0x52, 0x5f, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f, ++ 0x05, 0x19, 0x07, 0x1a, 0x0c, 0x19, 0x26, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0a, 0x0d, 0x14, ++ 0x07, 0x40, 0x27, 0x1f, 0x0a, 0x40, 0x42, 0x47, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x07, ++ 0x14, 0x07, 0x0c, 0x19, 0x02, 0x40, 0x07, 0x21, 0x07, 0x40, 0x40, 0x0c, 0x14, 0x17, 0x12, ++ 0x17, 0x02, 0x07, 0x14, 0x07, 0x0c, 0x19, 0x02, 0x40, 0x07, 0x21, 0x07, 0x40, 0x40, 0x0c, ++ 0x14, 0x17, 0x12, 0x17, 0x22, 0x42, 0x36, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, ++ 0x26, 0x07, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, ++ 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d, 0x07, 0x12, 0x12, 0x1f, 0x22, 0x1f, 0x22, 0x0a, 0x17, ++ 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40, 0x40, 0x08, 0x08, 0x0a, 0x40, 0x0f, 0x0a, 0x05, ++ 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x15, 0x45, 0x18, 0x12, 0x0a, 0x40, 0x0a, 0x15, ++ 0x05, 0x1f, 0x0a, 0x2c, 0x1a, 0x1f, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x52, 0x20, 0x05, 0x45, ++ 0x40, 0x40, 0x52, 0x60, 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f, 0x05, 0x1b, 0x08, 0x1a, ++ 0x0d, 0x1b, 0x28, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0a, 0x0d, 0x15, 0x07, 0x00, 0x27, 0x20, ++ 0x0a, 0x40, 0x42, 0x48, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x08, 0x15, 0x08, 0x0d, 0x1b, ++ 0x02, 0x00, 0x08, 0x23, 0x08, 0x00, 0x00, 0x0d, 0x15, 0x18, 0x12, 0x18, 0x02, 0x08, 0x15, ++ 0x08, 0x0d, 0x1b, 0x02, 0x00, 0x08, 0x23, 0x08, 0x00, 0x00, 0x0d, 0x15, 0x18, 0x12, 0x18, ++ 0x22, 0x42, 0x38, 0x40, 0x48, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x28, 0x07, 0x12, 0x42, ++ 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, ++ 0x40, 0x4d, 0x07, 0x12, 0x12, 0x20, 0x22, 0x20, 0x22, 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, ++ 0x42, 0x40, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, ++ 0x07, 0x22, 0x1d, 0x15, 0x45, 0x17, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x05, 0x20, 0x0a, 0x2d, ++ 0x1a, 0x20, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x53, 0x21, 0x05, 0x44, 0x40, 0x41, 0x53, 0x61, ++ 0x27, 0x40, 0x05, 0x40, 0x40, 0x40, 0x0f, 0x05, 0x1c, 0x09, 0x1b, 0x0e, 0x1c, 0x2a, 0x3e, ++ 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0d, 0x16, 0x07, 0x01, 0x27, 0x21, 0x0a, 0x40, 0x42, 0x49, ++ 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x16, 0x09, 0x0e, 0x1c, 0x03, 0x01, 0x09, 0x24, ++ 0x09, 0x01, 0x01, 0x0e, 0x16, 0x19, 0x13, 0x19, 0x03, 0x09, 0x16, 0x09, 0x0e, 0x1c, 0x03, ++ 0x01, 0x09, 0x24, 0x09, 0x01, 0x01, 0x0e, 0x16, 0x19, 0x13, 0x19, 0x23, 0x42, 0x3a, 0x40, ++ 0x48, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x07, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, ++ 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d, 0x07, 0x13, ++ 0x13, 0x21, 0x23, 0x21, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, 0x40, 0x40, ++ 0x06, 0x06, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, 0x1d, 0x15, ++ 0x45, 0x16, 0x12, 0x0a, 0x40, 0x0a, 0x15, 0x04, 0x21, 0x0a, 0x2e, 0x1b, 0x21, 0x0a, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x07, 0x54, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x27, 0x40, 0x06, 0x40, ++ 0x40, 0x40, 0x0f, 0x06, 0x1e, 0x0a, 0x1c, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, 0x07, 0x01, ++ 0x0c, 0x0e, 0x18, 0x07, 0x02, 0x27, 0x22, 0x09, 0x40, 0x41, 0x4a, 0x40, 0x40, 0x40, 0x06, ++ 0x06, 0x04, 0x0a, 0x18, 0x0a, 0x10, 0x1e, 0x04, 0x02, 0x0a, 0x26, 0x0a, 0x02, 0x02, 0x10, ++ 0x18, 0x1a, 0x14, 0x1a, 0x04, 0x0a, 0x18, 0x0a, 0x10, 0x1e, 0x04, 0x02, 0x0a, 0x26, 0x0a, ++ 0x02, 0x02, 0x10, 0x18, 0x1a, 0x14, 0x1a, 0x24, 0x41, 0x3c, 0x40, 0x48, 0x40, 0x06, 0x07, ++ 0x06, 0x14, 0x14, 0x2c, 0x07, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, ++ 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, 0x07, 0x14, 0x14, 0x22, 0x24, 0x22, ++ 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, 0x40, 0x05, 0x05, 0x09, 0x40, ++ 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x16, 0x46, 0x15, 0x11, 0x09, ++ 0x40, 0x09, 0x16, 0x03, 0x22, 0x09, 0x30, 0x1c, 0x22, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x54, ++ 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, 0x06, ++ 0x1f, 0x0b, 0x1c, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0c, 0x0e, 0x19, 0x07, ++ 0x03, 0x27, 0x23, 0x09, 0x40, 0x41, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, 0x0b, 0x19, ++ 0x0b, 0x11, 0x1f, 0x04, 0x03, 0x0b, 0x27, 0x0b, 0x03, 0x03, 0x11, 0x19, 0x1b, 0x14, 0x1b, ++ 0x04, 0x0b, 0x19, 0x0b, 0x11, 0x1f, 0x04, 0x03, 0x0b, 0x27, 0x0b, 0x03, 0x03, 0x11, 0x19, ++ 0x1b, 0x14, 0x1b, 0x24, 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x14, 0x14, 0x2e, ++ 0x07, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, ++ 0x41, 0x1e, 0x07, 0x40, 0x4e, 0x07, 0x14, 0x14, 0x23, 0x24, 0x23, 0x24, 0x09, 0x17, 0x44, ++ 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, 0x40, 0x04, 0x04, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, ++ 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x16, 0x46, 0x14, 0x11, 0x09, 0x40, 0x09, 0x16, 0x03, ++ 0x23, 0x09, 0x31, 0x1c, 0x23, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x55, 0x24, 0x06, 0x42, 0x40, ++ 0x44, 0x55, 0x64, 0x27, 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, 0x06, 0x21, 0x0c, 0x1d, 0x12, ++ 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x0d, 0x0e, 0x1a, 0x07, 0x04, 0x27, 0x24, 0x09, ++ 0x40, 0x41, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x1a, 0x0c, 0x12, 0x21, 0x05, ++ 0x04, 0x0c, 0x29, 0x0c, 0x04, 0x04, 0x12, 0x1a, 0x1c, 0x15, 0x1c, 0x05, 0x0c, 0x1a, 0x0c, ++ 0x12, 0x21, 0x05, 0x04, 0x0c, 0x29, 0x0c, 0x04, 0x04, 0x12, 0x1a, 0x1c, 0x15, 0x1c, 0x25, ++ 0x41, 0x3e, 0x40, 0x48, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x07, 0x11, 0x45, 0x41, ++ 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, ++ 0x4e, 0x07, 0x15, 0x15, 0x24, 0x25, 0x24, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, 0x45, 0x41, ++ 0x40, 0x40, 0x40, 0x03, 0x03, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, 0x1e, 0x07, ++ 0x25, 0x1e, 0x16, 0x46, 0x13, 0x11, 0x09, 0x40, 0x09, 0x16, 0x02, 0x24, 0x09, 0x32, 0x1d, ++ 0x24, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x56, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, 0x65, 0x27, ++ 0x40, 0x06, 0x40, 0x40, 0x40, 0x0f, 0x06, 0x22, 0x0c, 0x1d, 0x13, 0x22, 0x31, 0x3e, 0x3e, ++ 0x07, 0x07, 0x00, 0x0d, 0x0e, 0x1b, 0x07, 0x04, 0x27, 0x24, 0x08, 0x40, 0x41, 0x4d, 0x40, ++ 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x1b, 0x0c, 0x13, 0x22, 0x05, 0x04, 0x0c, 0x2a, 0x0c, ++ 0x04, 0x04, 0x13, 0x1b, 0x1c, 0x15, 0x1c, 0x05, 0x0c, 0x1b, 0x0c, 0x13, 0x22, 0x05, 0x04, ++ 0x0c, 0x2a, 0x0c, 0x04, 0x04, 0x13, 0x1b, 0x1c, 0x15, 0x1c, 0x25, 0x41, 0x3e, 0x40, 0x48, ++ 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x07, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, ++ 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f, 0x07, 0x15, 0x15, ++ 0x24, 0x25, 0x24, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40, 0x40, 0x02, ++ 0x02, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, 0x16, 0x47, ++ 0x12, 0x10, 0x08, 0x40, 0x08, 0x16, 0x01, 0x24, 0x08, 0x33, 0x1d, 0x24, 0x08, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x07, 0x56, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x27, 0x40, 0x07, 0x40, 0x40, ++ 0x40, 0x0f, 0x07, 0x24, 0x0d, 0x1e, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0e, ++ 0x0f, 0x1d, 0x07, 0x05, 0x27, 0x25, 0x08, 0x40, 0x40, 0x4d, 0x40, 0x40, 0x40, 0x07, 0x07, ++ 0x06, 0x0d, 0x1d, 0x0d, 0x15, 0x24, 0x06, 0x05, 0x0d, 0x2c, 0x0d, 0x05, 0x05, 0x15, 0x1d, ++ 0x1d, 0x16, 0x1d, 0x06, 0x0d, 0x1d, 0x0d, 0x15, 0x24, 0x06, 0x05, 0x0d, 0x2c, 0x0d, 0x05, ++ 0x05, 0x15, 0x1d, 0x1d, 0x16, 0x1d, 0x26, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, ++ 0x16, 0x16, 0x33, 0x07, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, ++ 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f, 0x07, 0x16, 0x16, 0x25, 0x26, 0x25, 0x26, ++ 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x08, 0x40, 0x0f, ++ 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x17, 0x47, 0x12, 0x10, 0x08, 0x40, ++ 0x08, 0x17, 0x01, 0x25, 0x08, 0x35, 0x1e, 0x25, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x57, 0x26, ++ 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f, 0x07, 0x26, ++ 0x0e, 0x1f, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0f, 0x0f, 0x1e, 0x07, 0x06, ++ 0x27, 0x26, 0x08, 0x40, 0x40, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, 0x1e, 0x0e, ++ 0x16, 0x26, 0x07, 0x06, 0x0e, 0x2e, 0x0e, 0x06, 0x06, 0x16, 0x1e, 0x1e, 0x17, 0x1e, 0x07, ++ 0x0e, 0x1e, 0x0e, 0x16, 0x26, 0x07, 0x06, 0x0e, 0x2e, 0x0e, 0x06, 0x06, 0x16, 0x1e, 0x1e, ++ 0x17, 0x1e, 0x27, 0x40, 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x35, 0x07, ++ 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, ++ 0x1f, 0x07, 0x40, 0x4f, 0x07, 0x17, 0x17, 0x26, 0x27, 0x26, 0x27, 0x08, 0x17, 0x47, 0x40, ++ 0x17, 0x47, 0x40, 0x40, 0x40, 0x40, 0x01, 0x01, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, ++ 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x17, 0x47, 0x11, 0x10, 0x08, 0x40, 0x08, 0x17, 0x00, 0x26, ++ 0x08, 0x36, 0x1f, 0x26, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x57, 0x27, 0x07, 0x40, 0x40, 0x47, ++ 0x57, 0x67, 0x27, 0x40, 0x07, 0x40, 0x40, 0x40, 0x0f, 0x07, 0x27, 0x0f, 0x1f, 0x17, 0x27, ++ 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x0f, 0x0f, 0x1f, 0x07, 0x07, 0x27, 0x27, 0x08, 0x40, ++ 0x40, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x1f, 0x0f, 0x17, 0x27, 0x07, 0x07, ++ 0x0f, 0x2f, 0x0f, 0x07, 0x07, 0x17, 0x1f, 0x1f, 0x17, 0x1f, 0x07, 0x0f, 0x1f, 0x0f, 0x17, ++ 0x27, 0x07, 0x07, 0x0f, 0x2f, 0x0f, 0x07, 0x07, 0x17, 0x1f, 0x1f, 0x17, 0x1f, 0x27, 0x40, ++ 0x3e, 0x40, 0x48, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x07, 0x10, 0x47, 0x40, 0x1f, ++ 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, ++ 0x07, 0x17, 0x17, 0x27, 0x27, 0x27, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, ++ 0x1f, 0x17, 0x47, 0x10, 0x10, 0x08, 0x40, 0x08, 0x17, 0x00, 0x27, 0x08, 0x37, 0x1f, 0x27, ++ 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x48, 0x48, 0x60, 0x40, 0x27, 0x07, 0x07, 0x1f, 0x40, ++ 0x48, 0x40, 0x40, 0x17, 0x0f, 0x48, 0x68, 0x40, 0x07, 0x68, 0x68, 0x68, 0x68, 0x68, 0x07, ++ 0x07, 0x0f, 0x3e, 0x17, 0x40, 0x07, 0x68, 0x27, 0x50, 0x17, 0x40, 0x07, 0x1f, 0x40, 0x40, ++ 0x40, 0x48, 0x48, 0x58, 0x60, 0x50, 0x60, 0x68, 0x60, 0x58, 0x68, 0x68, 0x68, 0x58, 0x60, ++ 0x68, 0x68, 0x68, 0x50, 0x48, 0x58, 0x58, 0x60, 0x50, 0x60, 0x68, 0x60, 0x58, 0x68, 0x68, ++ 0x68, 0x58, 0x60, 0x68, 0x68, 0x68, 0x50, 0x48, 0x58, 0x07, 0x50, 0x58, 0x40, 0x40, 0x40, ++ 0x48, 0x07, 0x48, 0x48, 0x48, 0x68, 0x50, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, ++ 0x50, 0x0f, 0x07, 0x40, 0x1f, 0x17, 0x50, 0x0f, 0x07, 0x40, 0x40, 0x07, 0x40, 0x40, 0x40, ++ 0x07, 0x40, 0x07, 0x17, 0x17, 0x17, 0x50, 0x17, 0x17, 0x50, 0x40, 0x40, 0x40, 0x2f, 0x17, ++ 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x1f, 0x1f, 0x27, 0x0f, 0x07, 0x07, 0x0f, 0x40, 0x07, 0x3e, ++ 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1f, 0x48, 0x17, 0x48, 0x48, 0x48, 0x17, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x47, 0x47, 0x5f, 0x40, 0x27, 0x07, 0x07, 0x20, 0x40, 0x47, 0x40, 0x40, 0x17, ++ 0x0f, 0x47, 0x66, 0x40, 0x08, 0x66, 0x66, 0x66, 0x65, 0x65, 0x07, 0x07, 0x0f, 0x3e, 0x17, ++ 0x00, 0x07, 0x67, 0x27, 0x4e, 0x17, 0x40, 0x07, 0x1f, 0x40, 0x40, 0x40, 0x47, 0x47, 0x57, ++ 0x5f, 0x4f, 0x5f, 0x66, 0x5e, 0x57, 0x67, 0x67, 0x66, 0x57, 0x5f, 0x67, 0x67, 0x66, 0x4f, ++ 0x47, 0x56, 0x57, 0x5f, 0x4f, 0x5f, 0x66, 0x5e, 0x57, 0x67, 0x67, 0x66, 0x57, 0x5f, 0x67, ++ 0x67, 0x66, 0x4f, 0x47, 0x56, 0x08, 0x4f, 0x56, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x47, ++ 0x47, 0x66, 0x4f, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, ++ 0x1f, 0x17, 0x4f, 0x10, 0x07, 0x40, 0x40, 0x07, 0x00, 0x00, 0x00, 0x08, 0x00, 0x08, 0x17, ++ 0x17, 0x17, 0x4f, 0x17, 0x17, 0x4f, 0x40, 0x40, 0x40, 0x2f, 0x17, 0x17, 0x40, 0x0f, 0x17, ++ 0x1f, 0x1f, 0x20, 0x27, 0x10, 0x07, 0x08, 0x10, 0x00, 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, ++ 0x17, 0x1f, 0x47, 0x17, 0x46, 0x47, 0x47, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x46, 0x47, ++ 0x5e, 0x40, 0x26, 0x06, 0x06, 0x20, 0x40, 0x47, 0x40, 0x40, 0x16, 0x0f, 0x47, 0x64, 0x40, ++ 0x08, 0x65, 0x64, 0x64, 0x63, 0x63, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x01, 0x07, 0x66, 0x27, ++ 0x4d, 0x17, 0x40, 0x07, 0x1e, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5e, 0x4e, 0x5e, 0x65, ++ 0x5d, 0x56, 0x66, 0x66, 0x64, 0x56, 0x5e, 0x66, 0x66, 0x64, 0x4e, 0x46, 0x55, 0x56, 0x5e, ++ 0x4e, 0x5e, 0x65, 0x5d, 0x56, 0x66, 0x66, 0x64, 0x56, 0x5e, 0x66, 0x66, 0x64, 0x4e, 0x46, ++ 0x55, 0x09, 0x4f, 0x54, 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x64, 0x4e, 0x1f, ++ 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, ++ 0x07, 0x40, 0x40, 0x07, 0x00, 0x00, 0x01, 0x09, 0x01, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, ++ 0x16, 0x4f, 0x40, 0x40, 0x40, 0x2e, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, ++ 0x10, 0x07, 0x09, 0x10, 0x01, 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x46, 0x17, ++ 0x45, 0x46, 0x46, 0x17, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x45, 0x47, 0x5e, 0x40, 0x25, 0x06, ++ 0x05, 0x20, 0x40, 0x47, 0x40, 0x40, 0x16, 0x0f, 0x47, 0x63, 0x40, 0x08, 0x64, 0x63, 0x62, ++ 0x60, 0x60, 0x07, 0x07, 0x0f, 0x3e, 0x17, 0x01, 0x07, 0x65, 0x27, 0x4c, 0x17, 0x40, 0x07, ++ 0x1d, 0x40, 0x40, 0x40, 0x47, 0x47, 0x56, 0x5d, 0x4e, 0x5d, 0x64, 0x5c, 0x56, 0x65, 0x65, ++ 0x63, 0x56, 0x5e, 0x65, 0x65, 0x63, 0x4d, 0x46, 0x54, 0x56, 0x5d, 0x4e, 0x5d, 0x64, 0x5c, ++ 0x56, 0x65, 0x65, 0x63, 0x56, 0x5e, 0x65, 0x65, 0x63, 0x4d, 0x46, 0x54, 0x09, 0x4f, 0x52, ++ 0x40, 0x40, 0x40, 0x47, 0x07, 0x47, 0x46, 0x46, 0x62, 0x4e, 0x1f, 0x16, 0x4f, 0x10, 0x07, ++ 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x1f, 0x16, 0x4f, 0x10, 0x07, 0x40, 0x40, 0x07, ++ 0x00, 0x00, 0x01, 0x09, 0x01, 0x09, 0x17, 0x17, 0x16, 0x4f, 0x17, 0x16, 0x4f, 0x40, 0x40, ++ 0x40, 0x2d, 0x17, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x1e, 0x20, 0x27, 0x10, 0x07, 0x09, 0x10, ++ 0x01, 0x07, 0x3e, 0x1f, 0x17, 0x40, 0x0f, 0x17, 0x1e, 0x45, 0x17, 0x44, 0x45, 0x45, 0x17, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x3e, 0x44, 0x46, 0x5d, 0x40, 0x24, 0x05, 0x04, 0x21, 0x40, 0x46, ++ 0x40, 0x40, 0x15, 0x0f, 0x46, 0x61, 0x40, 0x09, 0x63, 0x61, 0x60, 0x5e, 0x5e, 0x07, 0x07, ++ 0x0e, 0x3e, 0x16, 0x02, 0x07, 0x64, 0x27, 0x4b, 0x16, 0x40, 0x06, 0x1c, 0x40, 0x40, 0x40, ++ 0x46, 0x46, 0x55, 0x5c, 0x4d, 0x5c, 0x63, 0x5b, 0x55, 0x64, 0x64, 0x61, 0x55, 0x5d, 0x64, ++ 0x64, 0x61, 0x4c, 0x45, 0x53, 0x55, 0x5c, 0x4d, 0x5c, 0x63, 0x5b, 0x55, 0x64, 0x64, 0x61, ++ 0x55, 0x5d, 0x64, 0x64, 0x61, 0x4c, 0x45, 0x53, 0x0a, 0x4e, 0x50, 0x40, 0x41, 0x40, 0x46, ++ 0x07, 0x46, 0x45, 0x45, 0x60, 0x4d, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, ++ 0x11, 0x07, 0x40, 0x1e, 0x15, 0x4e, 0x11, 0x07, 0x40, 0x41, 0x07, 0x01, 0x01, 0x02, 0x0a, ++ 0x02, 0x0a, 0x16, 0x17, 0x15, 0x4e, 0x17, 0x15, 0x4e, 0x40, 0x40, 0x40, 0x2c, 0x16, 0x16, ++ 0x40, 0x0f, 0x16, 0x1d, 0x1d, 0x21, 0x27, 0x11, 0x07, 0x0a, 0x11, 0x02, 0x06, 0x3e, 0x1e, ++ 0x16, 0x40, 0x0f, 0x16, 0x1d, 0x44, 0x16, 0x43, 0x44, 0x44, 0x16, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x3e, 0x43, 0x46, 0x5c, 0x40, 0x23, 0x04, 0x03, 0x21, 0x40, 0x46, 0x40, 0x40, 0x14, 0x0f, ++ 0x46, 0x60, 0x40, 0x09, 0x61, 0x60, 0x5e, 0x5b, 0x5b, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x03, ++ 0x07, 0x63, 0x27, 0x49, 0x16, 0x40, 0x06, 0x1b, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5b, ++ 0x4c, 0x5b, 0x61, 0x59, 0x54, 0x63, 0x63, 0x60, 0x54, 0x5c, 0x63, 0x63, 0x60, 0x4b, 0x44, ++ 0x51, 0x54, 0x5b, 0x4c, 0x5b, 0x61, 0x59, 0x54, 0x63, 0x63, 0x60, 0x54, 0x5c, 0x63, 0x63, ++ 0x60, 0x4b, 0x44, 0x51, 0x0b, 0x4e, 0x4e, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, ++ 0x5e, 0x4c, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, ++ 0x14, 0x4e, 0x11, 0x07, 0x40, 0x41, 0x07, 0x01, 0x01, 0x03, 0x0b, 0x03, 0x0b, 0x16, 0x17, ++ 0x14, 0x4e, 0x17, 0x14, 0x4e, 0x40, 0x40, 0x40, 0x2b, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1c, ++ 0x1c, 0x21, 0x27, 0x11, 0x07, 0x0b, 0x11, 0x03, 0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, ++ 0x1c, 0x43, 0x16, 0x41, 0x43, 0x43, 0x16, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x42, 0x46, 0x5c, ++ 0x40, 0x22, 0x04, 0x02, 0x21, 0x40, 0x46, 0x40, 0x40, 0x14, 0x0f, 0x46, 0x5e, 0x40, 0x09, ++ 0x60, 0x5e, 0x5c, 0x59, 0x59, 0x07, 0x07, 0x0e, 0x3e, 0x16, 0x03, 0x07, 0x62, 0x27, 0x48, ++ 0x16, 0x40, 0x06, 0x1a, 0x40, 0x40, 0x40, 0x46, 0x46, 0x54, 0x5a, 0x4c, 0x5a, 0x60, 0x58, ++ 0x54, 0x62, 0x62, 0x5e, 0x54, 0x5c, 0x62, 0x62, 0x5e, 0x4a, 0x44, 0x50, 0x54, 0x5a, 0x4c, ++ 0x5a, 0x60, 0x58, 0x54, 0x62, 0x62, 0x5e, 0x54, 0x5c, 0x62, 0x62, 0x5e, 0x4a, 0x44, 0x50, ++ 0x0b, 0x4e, 0x4c, 0x40, 0x41, 0x40, 0x46, 0x07, 0x46, 0x44, 0x44, 0x5c, 0x4c, 0x1e, 0x14, ++ 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, 0x40, 0x1e, 0x14, 0x4e, 0x11, 0x07, ++ 0x40, 0x41, 0x07, 0x01, 0x01, 0x03, 0x0b, 0x03, 0x0b, 0x16, 0x17, 0x14, 0x4e, 0x17, 0x14, ++ 0x4e, 0x40, 0x40, 0x40, 0x2a, 0x16, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x1c, 0x21, 0x27, 0x11, ++ 0x07, 0x0b, 0x11, 0x03, 0x06, 0x3e, 0x1e, 0x16, 0x40, 0x0f, 0x16, 0x1c, 0x42, 0x16, 0x40, ++ 0x42, 0x42, 0x16, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x41, 0x45, 0x5b, 0x40, 0x21, 0x03, 0x01, ++ 0x22, 0x40, 0x45, 0x40, 0x40, 0x13, 0x0f, 0x45, 0x5d, 0x40, 0x0a, 0x5f, 0x5d, 0x5a, 0x56, ++ 0x56, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x04, 0x07, 0x61, 0x27, 0x47, 0x15, 0x40, 0x05, 0x19, ++ 0x40, 0x40, 0x40, 0x45, 0x45, 0x53, 0x59, 0x4b, 0x59, 0x5f, 0x57, 0x53, 0x61, 0x61, 0x5d, ++ 0x53, 0x5b, 0x61, 0x61, 0x5d, 0x49, 0x43, 0x4f, 0x53, 0x59, 0x4b, 0x59, 0x5f, 0x57, 0x53, ++ 0x61, 0x61, 0x5d, 0x53, 0x5b, 0x61, 0x61, 0x5d, 0x49, 0x43, 0x4f, 0x0c, 0x4d, 0x4a, 0x40, ++ 0x42, 0x40, 0x45, 0x07, 0x45, 0x43, 0x43, 0x5a, 0x4b, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, ++ 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x13, 0x4d, 0x12, 0x07, 0x40, 0x42, 0x07, 0x02, ++ 0x02, 0x04, 0x0c, 0x04, 0x0c, 0x15, 0x17, 0x13, 0x4d, 0x17, 0x13, 0x4d, 0x40, 0x40, 0x40, ++ 0x29, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x1b, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x04, ++ 0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1b, 0x41, 0x15, 0x00, 0x41, 0x41, 0x15, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x07, 0x3e, 0x40, 0x45, 0x5b, 0x40, 0x20, 0x02, 0x00, 0x22, 0x40, 0x45, 0x40, ++ 0x40, 0x12, 0x0f, 0x45, 0x5b, 0x40, 0x0a, 0x5e, 0x5b, 0x59, 0x54, 0x54, 0x07, 0x07, 0x0d, ++ 0x3e, 0x15, 0x04, 0x07, 0x60, 0x27, 0x46, 0x15, 0x40, 0x05, 0x18, 0x40, 0x40, 0x40, 0x45, ++ 0x45, 0x53, 0x58, 0x4b, 0x58, 0x5e, 0x56, 0x53, 0x60, 0x60, 0x5b, 0x53, 0x5b, 0x60, 0x60, ++ 0x5b, 0x48, 0x43, 0x4e, 0x53, 0x58, 0x4b, 0x58, 0x5e, 0x56, 0x53, 0x60, 0x60, 0x5b, 0x53, ++ 0x5b, 0x60, 0x60, 0x5b, 0x48, 0x43, 0x4e, 0x0c, 0x4d, 0x49, 0x40, 0x42, 0x40, 0x45, 0x07, ++ 0x45, 0x43, 0x43, 0x59, 0x4b, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, ++ 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x42, 0x07, 0x02, 0x02, 0x04, 0x0c, 0x04, ++ 0x0c, 0x15, 0x17, 0x12, 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, 0x40, 0x28, 0x15, 0x15, 0x40, ++ 0x0f, 0x15, 0x1a, 0x1a, 0x22, 0x27, 0x12, 0x07, 0x0c, 0x12, 0x04, 0x05, 0x3e, 0x1d, 0x15, ++ 0x40, 0x0f, 0x15, 0x1a, 0x40, 0x15, 0x01, 0x40, 0x40, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, ++ 0x00, 0x45, 0x5a, 0x40, 0x1f, 0x02, 0x40, 0x22, 0x40, 0x45, 0x40, 0x40, 0x12, 0x0f, 0x45, ++ 0x59, 0x40, 0x0a, 0x5c, 0x59, 0x57, 0x51, 0x51, 0x07, 0x07, 0x0d, 0x3e, 0x15, 0x05, 0x07, ++ 0x5f, 0x27, 0x44, 0x15, 0x40, 0x05, 0x17, 0x40, 0x40, 0x40, 0x45, 0x45, 0x52, 0x57, 0x4a, ++ 0x57, 0x5c, 0x54, 0x52, 0x5f, 0x5f, 0x59, 0x52, 0x5a, 0x5f, 0x5f, 0x59, 0x47, 0x42, 0x4c, ++ 0x52, 0x57, 0x4a, 0x57, 0x5c, 0x54, 0x52, 0x5f, 0x5f, 0x59, 0x52, 0x5a, 0x5f, 0x5f, 0x59, ++ 0x47, 0x42, 0x4c, 0x0d, 0x4d, 0x47, 0x40, 0x42, 0x40, 0x45, 0x07, 0x45, 0x42, 0x42, 0x57, ++ 0x4a, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, 0x4d, 0x12, 0x07, 0x40, 0x1d, 0x12, ++ 0x4d, 0x12, 0x07, 0x40, 0x42, 0x07, 0x02, 0x02, 0x05, 0x0d, 0x05, 0x0d, 0x15, 0x17, 0x12, ++ 0x4d, 0x17, 0x12, 0x4d, 0x40, 0x40, 0x40, 0x27, 0x15, 0x15, 0x40, 0x0f, 0x15, 0x1a, 0x1a, ++ 0x22, 0x27, 0x12, 0x07, 0x0d, 0x12, 0x05, 0x05, 0x3e, 0x1d, 0x15, 0x40, 0x0f, 0x15, 0x1a, ++ 0x00, 0x15, 0x03, 0x00, 0x00, 0x15, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x01, 0x44, 0x59, 0x40, ++ 0x1e, 0x01, 0x41, 0x23, 0x40, 0x44, 0x40, 0x40, 0x11, 0x0f, 0x44, 0x58, 0x40, 0x0b, 0x5b, ++ 0x58, 0x55, 0x4f, 0x4f, 0x07, 0x07, 0x0c, 0x3e, 0x14, 0x06, 0x07, 0x5e, 0x27, 0x43, 0x14, ++ 0x40, 0x04, 0x16, 0x40, 0x40, 0x40, 0x44, 0x44, 0x51, 0x56, 0x49, 0x56, 0x5b, 0x53, 0x51, ++ 0x5e, 0x5e, 0x58, 0x51, 0x59, 0x5e, 0x5e, 0x58, 0x46, 0x41, 0x4b, 0x51, 0x56, 0x49, 0x56, ++ 0x5b, 0x53, 0x51, 0x5e, 0x5e, 0x58, 0x51, 0x59, 0x5e, 0x5e, 0x58, 0x46, 0x41, 0x4b, 0x0e, ++ 0x4c, 0x45, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x55, 0x49, 0x1c, 0x11, 0x4c, ++ 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, ++ 0x43, 0x07, 0x03, 0x03, 0x06, 0x0e, 0x06, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, ++ 0x40, 0x40, 0x40, 0x26, 0x14, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, ++ 0x0e, 0x13, 0x06, 0x04, 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x01, 0x14, 0x04, 0x01, ++ 0x01, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x02, 0x44, 0x59, 0x40, 0x1d, 0x01, 0x42, 0x23, ++ 0x40, 0x44, 0x40, 0x40, 0x11, 0x0f, 0x44, 0x56, 0x40, 0x0b, 0x5a, 0x56, 0x53, 0x4c, 0x4c, ++ 0x07, 0x07, 0x0c, 0x3e, 0x14, 0x06, 0x07, 0x5d, 0x27, 0x42, 0x14, 0x40, 0x04, 0x15, 0x40, ++ 0x40, 0x40, 0x44, 0x44, 0x51, 0x55, 0x49, 0x55, 0x5a, 0x52, 0x51, 0x5d, 0x5d, 0x56, 0x51, ++ 0x59, 0x5d, 0x5d, 0x56, 0x45, 0x41, 0x4a, 0x51, 0x55, 0x49, 0x55, 0x5a, 0x52, 0x51, 0x5d, ++ 0x5d, 0x56, 0x51, 0x59, 0x5d, 0x5d, 0x56, 0x45, 0x41, 0x4a, 0x0e, 0x4c, 0x43, 0x40, 0x43, ++ 0x40, 0x44, 0x07, 0x44, 0x41, 0x41, 0x53, 0x49, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, ++ 0x11, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x11, 0x4c, 0x13, 0x07, 0x40, 0x43, 0x07, 0x03, 0x03, ++ 0x06, 0x0e, 0x06, 0x0e, 0x14, 0x17, 0x11, 0x4c, 0x17, 0x11, 0x4c, 0x40, 0x40, 0x40, 0x25, ++ 0x14, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x19, 0x23, 0x27, 0x13, 0x07, 0x0e, 0x13, 0x06, 0x04, ++ 0x3e, 0x1c, 0x14, 0x40, 0x0f, 0x14, 0x19, 0x02, 0x14, 0x05, 0x02, 0x02, 0x14, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x07, 0x3e, 0x03, 0x44, 0x58, 0x40, 0x1c, 0x00, 0x43, 0x23, 0x40, 0x44, 0x40, 0x40, ++ 0x10, 0x0f, 0x44, 0x55, 0x40, 0x0b, 0x59, 0x55, 0x51, 0x4a, 0x4a, 0x07, 0x07, 0x0c, 0x3d, ++ 0x14, 0x07, 0x07, 0x5c, 0x27, 0x41, 0x14, 0x40, 0x04, 0x14, 0x40, 0x40, 0x40, 0x44, 0x44, ++ 0x50, 0x54, 0x48, 0x54, 0x59, 0x51, 0x50, 0x5c, 0x5c, 0x55, 0x50, 0x58, 0x5c, 0x5c, 0x55, ++ 0x44, 0x40, 0x49, 0x50, 0x54, 0x48, 0x54, 0x59, 0x51, 0x50, 0x5c, 0x5c, 0x55, 0x50, 0x58, ++ 0x5c, 0x5c, 0x55, 0x44, 0x40, 0x49, 0x0f, 0x4c, 0x41, 0x40, 0x43, 0x40, 0x44, 0x07, 0x44, ++ 0x40, 0x40, 0x51, 0x48, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, ++ 0x40, 0x1c, 0x10, 0x4c, 0x13, 0x07, 0x40, 0x43, 0x07, 0x03, 0x03, 0x07, 0x0f, 0x07, 0x0f, ++ 0x14, 0x17, 0x10, 0x4c, 0x17, 0x10, 0x4c, 0x40, 0x40, 0x40, 0x24, 0x14, 0x14, 0x40, 0x0f, ++ 0x14, 0x18, 0x18, 0x23, 0x27, 0x13, 0x07, 0x0f, 0x13, 0x07, 0x04, 0x3e, 0x1c, 0x14, 0x40, ++ 0x0f, 0x14, 0x18, 0x03, 0x14, 0x06, 0x03, 0x03, 0x14, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x04, ++ 0x43, 0x57, 0x40, 0x1b, 0x40, 0x44, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0f, 0x0f, 0x43, 0x53, ++ 0x40, 0x0c, 0x57, 0x53, 0x4f, 0x47, 0x47, 0x07, 0x07, 0x0b, 0x3b, 0x13, 0x08, 0x07, 0x5b, ++ 0x27, 0x00, 0x13, 0x40, 0x03, 0x13, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x53, 0x47, 0x53, ++ 0x57, 0x4f, 0x4f, 0x5b, 0x5b, 0x53, 0x4f, 0x57, 0x5b, 0x5b, 0x53, 0x43, 0x00, 0x47, 0x4f, ++ 0x53, 0x47, 0x53, 0x57, 0x4f, 0x4f, 0x5b, 0x5b, 0x53, 0x4f, 0x57, 0x5b, 0x5b, 0x53, 0x43, ++ 0x00, 0x47, 0x10, 0x4b, 0x00, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4f, 0x47, ++ 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, ++ 0x14, 0x07, 0x40, 0x44, 0x07, 0x04, 0x04, 0x08, 0x10, 0x08, 0x10, 0x13, 0x17, 0x0f, 0x4b, ++ 0x17, 0x0f, 0x4b, 0x40, 0x40, 0x40, 0x23, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, ++ 0x27, 0x14, 0x07, 0x10, 0x14, 0x08, 0x03, 0x3e, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x04, ++ 0x13, 0x08, 0x04, 0x04, 0x13, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x05, 0x43, 0x57, 0x40, 0x1a, ++ 0x40, 0x45, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0f, 0x0f, 0x43, 0x52, 0x40, 0x0c, 0x56, 0x52, ++ 0x4d, 0x45, 0x45, 0x07, 0x07, 0x0b, 0x3a, 0x13, 0x08, 0x07, 0x5a, 0x27, 0x01, 0x13, 0x40, ++ 0x03, 0x12, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4f, 0x52, 0x47, 0x52, 0x56, 0x4e, 0x4f, 0x5a, ++ 0x5a, 0x52, 0x4f, 0x57, 0x5a, 0x5a, 0x52, 0x42, 0x00, 0x46, 0x4f, 0x52, 0x47, 0x52, 0x56, ++ 0x4e, 0x4f, 0x5a, 0x5a, 0x52, 0x4f, 0x57, 0x5a, 0x5a, 0x52, 0x42, 0x00, 0x46, 0x10, 0x4b, ++ 0x02, 0x40, 0x44, 0x40, 0x43, 0x07, 0x43, 0x00, 0x00, 0x4d, 0x47, 0x1b, 0x0f, 0x4b, 0x14, ++ 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0f, 0x4b, 0x14, 0x07, 0x40, 0x44, ++ 0x07, 0x04, 0x04, 0x08, 0x10, 0x08, 0x10, 0x13, 0x17, 0x0f, 0x4b, 0x17, 0x0f, 0x4b, 0x40, ++ 0x40, 0x40, 0x22, 0x13, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x17, 0x24, 0x27, 0x14, 0x07, 0x10, ++ 0x14, 0x08, 0x03, 0x3e, 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x17, 0x05, 0x13, 0x09, 0x05, 0x05, ++ 0x13, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x06, 0x43, 0x56, 0x40, 0x19, 0x41, 0x46, 0x24, 0x40, ++ 0x43, 0x40, 0x40, 0x0e, 0x0f, 0x43, 0x50, 0x40, 0x0c, 0x55, 0x50, 0x4b, 0x42, 0x42, 0x07, ++ 0x07, 0x0b, 0x38, 0x13, 0x09, 0x07, 0x59, 0x27, 0x02, 0x13, 0x40, 0x03, 0x11, 0x40, 0x40, ++ 0x40, 0x43, 0x43, 0x4e, 0x51, 0x46, 0x51, 0x55, 0x4d, 0x4e, 0x59, 0x59, 0x50, 0x4e, 0x56, ++ 0x59, 0x59, 0x50, 0x41, 0x01, 0x45, 0x4e, 0x51, 0x46, 0x51, 0x55, 0x4d, 0x4e, 0x59, 0x59, ++ 0x50, 0x4e, 0x56, 0x59, 0x59, 0x50, 0x41, 0x01, 0x45, 0x11, 0x4b, 0x04, 0x40, 0x44, 0x40, ++ 0x43, 0x07, 0x43, 0x01, 0x01, 0x4b, 0x46, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, ++ 0x4b, 0x14, 0x07, 0x40, 0x1b, 0x0e, 0x4b, 0x14, 0x07, 0x40, 0x44, 0x07, 0x04, 0x04, 0x09, ++ 0x11, 0x09, 0x11, 0x13, 0x17, 0x0e, 0x4b, 0x17, 0x0e, 0x4b, 0x40, 0x40, 0x40, 0x21, 0x13, ++ 0x13, 0x40, 0x0f, 0x13, 0x16, 0x16, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x09, 0x03, 0x3d, ++ 0x1b, 0x13, 0x40, 0x0f, 0x13, 0x16, 0x06, 0x13, 0x0a, 0x06, 0x06, 0x13, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x06, 0x43, 0x56, 0x40, 0x18, 0x42, 0x47, 0x24, 0x40, 0x43, 0x40, 0x40, 0x0d, ++ 0x0f, 0x43, 0x4f, 0x40, 0x0c, 0x54, 0x4f, 0x4a, 0x40, 0x40, 0x07, 0x07, 0x0a, 0x36, 0x12, ++ 0x09, 0x07, 0x59, 0x27, 0x03, 0x12, 0x40, 0x02, 0x10, 0x40, 0x40, 0x40, 0x43, 0x43, 0x4e, ++ 0x51, 0x46, 0x51, 0x54, 0x4c, 0x4e, 0x59, 0x59, 0x4f, 0x4e, 0x56, 0x59, 0x59, 0x4f, 0x41, ++ 0x01, 0x44, 0x4e, 0x51, 0x46, 0x51, 0x54, 0x4c, 0x4e, 0x59, 0x59, 0x4f, 0x4e, 0x56, 0x59, ++ 0x59, 0x4f, 0x41, 0x01, 0x44, 0x11, 0x4b, 0x05, 0x40, 0x45, 0x40, 0x43, 0x07, 0x43, 0x01, ++ 0x01, 0x4a, 0x46, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, ++ 0x1a, 0x0d, 0x4b, 0x14, 0x07, 0x40, 0x45, 0x07, 0x04, 0x04, 0x09, 0x11, 0x09, 0x11, 0x12, ++ 0x17, 0x0d, 0x4b, 0x17, 0x0d, 0x4b, 0x40, 0x40, 0x40, 0x20, 0x12, 0x12, 0x40, 0x0f, 0x12, ++ 0x15, 0x15, 0x24, 0x27, 0x14, 0x07, 0x11, 0x14, 0x09, 0x02, 0x3b, 0x1a, 0x12, 0x40, 0x0f, ++ 0x12, 0x15, 0x06, 0x12, 0x0b, 0x06, 0x06, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x07, 0x42, ++ 0x55, 0x40, 0x18, 0x42, 0x47, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0d, 0x0f, 0x42, 0x4d, 0x40, ++ 0x0d, 0x52, 0x4d, 0x48, 0x02, 0x02, 0x07, 0x07, 0x0a, 0x35, 0x12, 0x0a, 0x07, 0x58, 0x27, ++ 0x05, 0x12, 0x40, 0x02, 0x10, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4d, 0x50, 0x45, 0x50, 0x52, ++ 0x4a, 0x4d, 0x58, 0x58, 0x4d, 0x4d, 0x55, 0x58, 0x58, 0x4d, 0x40, 0x02, 0x42, 0x4d, 0x50, ++ 0x45, 0x50, 0x52, 0x4a, 0x4d, 0x58, 0x58, 0x4d, 0x4d, 0x55, 0x58, 0x58, 0x4d, 0x40, 0x02, ++ 0x42, 0x12, 0x4a, 0x07, 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x02, 0x02, 0x48, 0x45, 0x1a, ++ 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0d, 0x4a, 0x15, ++ 0x07, 0x40, 0x45, 0x07, 0x05, 0x05, 0x0a, 0x12, 0x0a, 0x12, 0x12, 0x17, 0x0d, 0x4a, 0x17, ++ 0x0d, 0x4a, 0x40, 0x40, 0x40, 0x20, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x15, 0x25, 0x27, ++ 0x15, 0x07, 0x12, 0x15, 0x0a, 0x02, 0x3a, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x15, 0x07, 0x12, ++ 0x0d, 0x07, 0x07, 0x12, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x08, 0x42, 0x54, 0x40, 0x17, 0x43, ++ 0x48, 0x25, 0x40, 0x42, 0x40, 0x40, 0x0c, 0x0f, 0x42, 0x4b, 0x40, 0x0d, 0x51, 0x4b, 0x46, ++ 0x04, 0x04, 0x07, 0x07, 0x0a, 0x33, 0x12, 0x0b, 0x07, 0x57, 0x27, 0x06, 0x12, 0x40, 0x02, ++ 0x0f, 0x40, 0x40, 0x40, 0x42, 0x42, 0x4c, 0x4f, 0x44, 0x4f, 0x51, 0x49, 0x4c, 0x57, 0x57, ++ 0x4b, 0x4c, 0x54, 0x57, 0x57, 0x4b, 0x00, 0x03, 0x41, 0x4c, 0x4f, 0x44, 0x4f, 0x51, 0x49, ++ 0x4c, 0x57, 0x57, 0x4b, 0x4c, 0x54, 0x57, 0x57, 0x4b, 0x00, 0x03, 0x41, 0x13, 0x4a, 0x09, ++ 0x40, 0x45, 0x40, 0x42, 0x07, 0x42, 0x03, 0x03, 0x46, 0x44, 0x1a, 0x0c, 0x4a, 0x15, 0x07, ++ 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, 0x07, ++ 0x05, 0x05, 0x0b, 0x13, 0x0b, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, ++ 0x40, 0x1f, 0x12, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, ++ 0x0b, 0x02, 0x39, 0x1a, 0x12, 0x40, 0x0f, 0x12, 0x14, 0x08, 0x12, 0x0e, 0x08, 0x08, 0x12, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x3e, 0x09, 0x42, 0x54, 0x40, 0x16, 0x43, 0x49, 0x25, 0x40, 0x42, ++ 0x40, 0x40, 0x0c, 0x0f, 0x42, 0x4a, 0x40, 0x0d, 0x50, 0x4a, 0x44, 0x07, 0x07, 0x07, 0x07, ++ 0x0a, 0x32, 0x12, 0x0b, 0x07, 0x56, 0x27, 0x07, 0x12, 0x40, 0x02, 0x0e, 0x40, 0x40, 0x40, ++ 0x42, 0x42, 0x4c, 0x4e, 0x44, 0x4e, 0x50, 0x48, 0x4c, 0x56, 0x56, 0x4a, 0x4c, 0x54, 0x56, ++ 0x56, 0x4a, 0x01, 0x03, 0x40, 0x4c, 0x4e, 0x44, 0x4e, 0x50, 0x48, 0x4c, 0x56, 0x56, 0x4a, ++ 0x4c, 0x54, 0x56, 0x56, 0x4a, 0x01, 0x03, 0x40, 0x13, 0x4a, 0x0b, 0x40, 0x45, 0x40, 0x42, ++ 0x07, 0x42, 0x03, 0x03, 0x44, 0x44, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, ++ 0x15, 0x07, 0x40, 0x1a, 0x0c, 0x4a, 0x15, 0x07, 0x40, 0x45, 0x07, 0x05, 0x05, 0x0b, 0x13, ++ 0x0b, 0x13, 0x12, 0x17, 0x0c, 0x4a, 0x17, 0x0c, 0x4a, 0x40, 0x40, 0x40, 0x1e, 0x12, 0x12, ++ 0x40, 0x0f, 0x12, 0x14, 0x14, 0x25, 0x27, 0x15, 0x07, 0x13, 0x15, 0x0b, 0x02, 0x38, 0x1a, ++ 0x12, 0x40, 0x0f, 0x12, 0x14, 0x09, 0x12, 0x0f, 0x09, 0x09, 0x12, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x3e, 0x0a, 0x41, 0x53, 0x40, 0x15, 0x44, 0x4a, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0b, 0x0f, ++ 0x41, 0x48, 0x40, 0x0e, 0x4f, 0x48, 0x42, 0x09, 0x09, 0x07, 0x07, 0x09, 0x30, 0x11, 0x0c, ++ 0x07, 0x55, 0x27, 0x08, 0x11, 0x40, 0x01, 0x0d, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4b, 0x4d, ++ 0x43, 0x4d, 0x4f, 0x47, 0x4b, 0x55, 0x55, 0x48, 0x4b, 0x53, 0x55, 0x55, 0x48, 0x02, 0x04, ++ 0x00, 0x4b, 0x4d, 0x43, 0x4d, 0x4f, 0x47, 0x4b, 0x55, 0x55, 0x48, 0x4b, 0x53, 0x55, 0x55, ++ 0x48, 0x02, 0x04, 0x00, 0x14, 0x49, 0x0d, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x04, 0x04, ++ 0x42, 0x43, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0b, 0x49, 0x16, 0x07, 0x40, 0x19, ++ 0x0b, 0x49, 0x16, 0x07, 0x40, 0x46, 0x07, 0x06, 0x06, 0x0c, 0x14, 0x0c, 0x14, 0x11, 0x17, ++ 0x0b, 0x49, 0x17, 0x0b, 0x49, 0x40, 0x40, 0x40, 0x1d, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x13, ++ 0x13, 0x26, 0x27, 0x16, 0x07, 0x14, 0x16, 0x0c, 0x01, 0x36, 0x19, 0x11, 0x40, 0x0f, 0x11, ++ 0x13, 0x0a, 0x11, 0x10, 0x0a, 0x0a, 0x11, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x0b, 0x41, 0x52, ++ 0x40, 0x14, 0x45, 0x4b, 0x26, 0x40, 0x41, 0x40, 0x40, 0x0a, 0x0f, 0x41, 0x47, 0x40, 0x0e, ++ 0x4d, 0x47, 0x40, 0x0c, 0x0c, 0x07, 0x07, 0x09, 0x2f, 0x11, 0x0d, 0x07, 0x54, 0x27, 0x0a, ++ 0x11, 0x40, 0x01, 0x0c, 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4c, 0x42, 0x4c, 0x4d, 0x45, ++ 0x4a, 0x54, 0x54, 0x47, 0x4a, 0x52, 0x54, 0x54, 0x47, 0x03, 0x05, 0x02, 0x4a, 0x4c, 0x42, ++ 0x4c, 0x4d, 0x45, 0x4a, 0x54, 0x54, 0x47, 0x4a, 0x52, 0x54, 0x54, 0x47, 0x03, 0x05, 0x02, ++ 0x15, 0x49, 0x0f, 0x40, 0x46, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x40, 0x42, 0x19, 0x0a, ++ 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, ++ 0x40, 0x46, 0x07, 0x06, 0x06, 0x0d, 0x15, 0x0d, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, ++ 0x49, 0x40, 0x40, 0x40, 0x1c, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, ++ 0x07, 0x15, 0x16, 0x0d, 0x01, 0x35, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x0b, 0x11, 0x12, ++ 0x0b, 0x0b, 0x11, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x0c, 0x41, 0x52, 0x40, 0x13, 0x45, 0x4c, ++ 0x26, 0x40, 0x41, 0x40, 0x40, 0x0a, 0x0f, 0x41, 0x45, 0x40, 0x0e, 0x4c, 0x45, 0x01, 0x0e, ++ 0x0e, 0x07, 0x07, 0x09, 0x2d, 0x11, 0x0d, 0x07, 0x53, 0x27, 0x0b, 0x11, 0x40, 0x01, 0x0b, ++ 0x40, 0x40, 0x40, 0x41, 0x41, 0x4a, 0x4b, 0x42, 0x4b, 0x4c, 0x44, 0x4a, 0x53, 0x53, 0x45, ++ 0x4a, 0x52, 0x53, 0x53, 0x45, 0x04, 0x05, 0x03, 0x4a, 0x4b, 0x42, 0x4b, 0x4c, 0x44, 0x4a, ++ 0x53, 0x53, 0x45, 0x4a, 0x52, 0x53, 0x53, 0x45, 0x04, 0x05, 0x03, 0x15, 0x49, 0x11, 0x40, ++ 0x46, 0x40, 0x41, 0x07, 0x41, 0x05, 0x05, 0x01, 0x42, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, ++ 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x19, 0x0a, 0x49, 0x16, 0x07, 0x40, 0x46, 0x07, 0x06, ++ 0x06, 0x0d, 0x15, 0x0d, 0x15, 0x11, 0x17, 0x0a, 0x49, 0x17, 0x0a, 0x49, 0x40, 0x40, 0x40, ++ 0x1b, 0x11, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x12, 0x26, 0x27, 0x16, 0x07, 0x15, 0x16, 0x0d, ++ 0x01, 0x34, 0x19, 0x11, 0x40, 0x0f, 0x11, 0x12, 0x0c, 0x11, 0x13, 0x0c, 0x0c, 0x11, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x07, 0x3e, 0x0d, 0x40, 0x51, 0x40, 0x12, 0x46, 0x4d, 0x27, 0x40, 0x40, 0x40, ++ 0x40, 0x09, 0x0f, 0x40, 0x44, 0x40, 0x0f, 0x4b, 0x44, 0x03, 0x11, 0x11, 0x07, 0x07, 0x08, ++ 0x2c, 0x10, 0x0e, 0x07, 0x52, 0x27, 0x0c, 0x10, 0x40, 0x00, 0x0a, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x49, 0x4a, 0x41, 0x4a, 0x4b, 0x43, 0x49, 0x52, 0x52, 0x44, 0x49, 0x51, 0x52, 0x52, ++ 0x44, 0x05, 0x06, 0x04, 0x49, 0x4a, 0x41, 0x4a, 0x4b, 0x43, 0x49, 0x52, 0x52, 0x44, 0x49, ++ 0x51, 0x52, 0x52, 0x44, 0x05, 0x06, 0x04, 0x16, 0x48, 0x13, 0x40, 0x47, 0x40, 0x40, 0x07, ++ 0x40, 0x06, 0x06, 0x03, 0x41, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, ++ 0x07, 0x40, 0x18, 0x09, 0x48, 0x17, 0x07, 0x40, 0x47, 0x07, 0x07, 0x07, 0x0e, 0x16, 0x0e, ++ 0x16, 0x10, 0x17, 0x09, 0x48, 0x17, 0x09, 0x48, 0x40, 0x40, 0x40, 0x1a, 0x10, 0x10, 0x40, ++ 0x0f, 0x10, 0x11, 0x11, 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0e, 0x00, 0x33, 0x18, 0x10, ++ 0x40, 0x0f, 0x10, 0x11, 0x0d, 0x10, 0x14, 0x0d, 0x0d, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, ++ 0x0e, 0x40, 0x51, 0x40, 0x11, 0x47, 0x4e, 0x27, 0x40, 0x40, 0x40, 0x40, 0x08, 0x0f, 0x40, ++ 0x42, 0x40, 0x0f, 0x4a, 0x42, 0x04, 0x13, 0x13, 0x07, 0x07, 0x08, 0x2a, 0x10, 0x0e, 0x07, ++ 0x51, 0x27, 0x0d, 0x10, 0x40, 0x00, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x49, 0x49, 0x41, ++ 0x49, 0x4a, 0x42, 0x49, 0x51, 0x51, 0x42, 0x49, 0x51, 0x51, 0x51, 0x42, 0x06, 0x06, 0x05, ++ 0x49, 0x49, 0x41, 0x49, 0x4a, 0x42, 0x49, 0x51, 0x51, 0x42, 0x49, 0x51, 0x51, 0x51, 0x42, ++ 0x06, 0x06, 0x05, 0x16, 0x48, 0x14, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x06, 0x06, 0x04, ++ 0x41, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, ++ 0x48, 0x17, 0x07, 0x40, 0x47, 0x07, 0x07, 0x07, 0x0e, 0x16, 0x0e, 0x16, 0x10, 0x17, 0x08, ++ 0x48, 0x17, 0x08, 0x48, 0x40, 0x40, 0x40, 0x19, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, ++ 0x27, 0x27, 0x17, 0x07, 0x16, 0x17, 0x0e, 0x00, 0x31, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, ++ 0x0e, 0x10, 0x15, 0x0e, 0x0e, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x0f, 0x40, 0x50, 0x40, ++ 0x10, 0x47, 0x4f, 0x27, 0x40, 0x40, 0x40, 0x40, 0x08, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x48, ++ 0x40, 0x06, 0x16, 0x16, 0x07, 0x07, 0x08, 0x28, 0x10, 0x0f, 0x07, 0x50, 0x27, 0x0f, 0x10, ++ 0x40, 0x00, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x40, 0x48, 0x48, 0x40, 0x48, ++ 0x50, 0x50, 0x40, 0x48, 0x50, 0x50, 0x50, 0x40, 0x07, 0x07, 0x07, 0x48, 0x48, 0x40, 0x48, ++ 0x48, 0x40, 0x48, 0x50, 0x50, 0x40, 0x48, 0x50, 0x50, 0x50, 0x40, 0x07, 0x07, 0x07, 0x17, ++ 0x48, 0x16, 0x40, 0x47, 0x40, 0x40, 0x07, 0x40, 0x07, 0x07, 0x06, 0x40, 0x18, 0x08, 0x48, ++ 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, 0x18, 0x08, 0x48, 0x17, 0x07, 0x40, ++ 0x47, 0x07, 0x07, 0x07, 0x0f, 0x17, 0x0f, 0x17, 0x10, 0x17, 0x08, 0x48, 0x17, 0x08, 0x48, ++ 0x40, 0x40, 0x40, 0x18, 0x10, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x10, 0x27, 0x27, 0x17, 0x07, ++ 0x17, 0x17, 0x0f, 0x00, 0x30, 0x18, 0x10, 0x40, 0x0f, 0x10, 0x10, 0x0f, 0x10, 0x17, 0x0f, ++ 0x0f, 0x10, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x10, 0x00, 0x4f, 0x40, 0x0f, 0x48, 0x50, 0x28, ++ 0x40, 0x00, 0x40, 0x40, 0x07, 0x0f, 0x00, 0x00, 0x40, 0x10, 0x47, 0x00, 0x08, 0x18, 0x18, ++ 0x07, 0x07, 0x07, 0x27, 0x0f, 0x10, 0x07, 0x4f, 0x27, 0x10, 0x0f, 0x40, 0x40, 0x07, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x47, 0x47, 0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, 0x4f, 0x00, 0x47, ++ 0x4f, 0x4f, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x47, 0x47, 0x00, 0x47, 0x47, 0x00, 0x47, 0x4f, ++ 0x4f, 0x00, 0x47, 0x4f, 0x4f, 0x4f, 0x00, 0x08, 0x08, 0x08, 0x18, 0x47, 0x18, 0x40, 0x48, ++ 0x40, 0x00, 0x07, 0x00, 0x08, 0x08, 0x08, 0x00, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, ++ 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, 0x07, 0x08, 0x08, ++ 0x10, 0x18, 0x10, 0x18, 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, 0x40, 0x17, ++ 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, 0x40, ++ 0x2f, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0f, 0x10, 0x0f, 0x18, 0x10, 0x10, 0x0f, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x07, 0x3e, 0x11, 0x00, 0x4f, 0x40, 0x0e, 0x48, 0x51, 0x28, 0x40, 0x00, 0x40, 0x40, ++ 0x07, 0x0f, 0x00, 0x02, 0x40, 0x10, 0x46, 0x02, 0x0a, 0x1b, 0x1b, 0x07, 0x07, 0x07, 0x25, ++ 0x0f, 0x10, 0x07, 0x4e, 0x27, 0x11, 0x0f, 0x40, 0x40, 0x06, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x47, 0x46, 0x00, 0x46, 0x46, 0x01, 0x47, 0x4e, 0x4e, 0x02, 0x47, 0x4f, 0x4e, 0x4e, 0x02, ++ 0x09, 0x08, 0x09, 0x47, 0x46, 0x00, 0x46, 0x46, 0x01, 0x47, 0x4e, 0x4e, 0x02, 0x47, 0x4f, ++ 0x4e, 0x4e, 0x02, 0x09, 0x08, 0x09, 0x18, 0x47, 0x1a, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, ++ 0x08, 0x08, 0x0a, 0x00, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, ++ 0x40, 0x17, 0x07, 0x47, 0x18, 0x07, 0x40, 0x48, 0x07, 0x08, 0x08, 0x10, 0x18, 0x10, 0x18, ++ 0x0f, 0x17, 0x07, 0x47, 0x17, 0x07, 0x47, 0x40, 0x40, 0x40, 0x16, 0x0f, 0x0f, 0x40, 0x0f, ++ 0x0f, 0x0f, 0x0f, 0x28, 0x27, 0x18, 0x07, 0x18, 0x18, 0x10, 0x40, 0x2e, 0x17, 0x0f, 0x40, ++ 0x0f, 0x0f, 0x0f, 0x11, 0x0f, 0x19, 0x11, 0x11, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x12, ++ 0x00, 0x4e, 0x40, 0x0d, 0x49, 0x52, 0x28, 0x40, 0x00, 0x40, 0x40, 0x06, 0x0f, 0x00, 0x03, ++ 0x40, 0x10, 0x45, 0x03, 0x0c, 0x1d, 0x1d, 0x07, 0x07, 0x07, 0x24, 0x0f, 0x11, 0x07, 0x4d, ++ 0x27, 0x12, 0x0f, 0x40, 0x40, 0x05, 0x40, 0x40, 0x40, 0x00, 0x00, 0x46, 0x45, 0x01, 0x45, ++ 0x45, 0x02, 0x46, 0x4d, 0x4d, 0x03, 0x46, 0x4e, 0x4d, 0x4d, 0x03, 0x0a, 0x09, 0x0a, 0x46, ++ 0x45, 0x01, 0x45, 0x45, 0x02, 0x46, 0x4d, 0x4d, 0x03, 0x46, 0x4e, 0x4d, 0x4d, 0x03, 0x0a, ++ 0x09, 0x0a, 0x19, 0x47, 0x1c, 0x40, 0x48, 0x40, 0x00, 0x07, 0x00, 0x09, 0x09, 0x0c, 0x01, ++ 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, 0x18, 0x07, 0x40, 0x17, 0x06, 0x47, ++ 0x18, 0x07, 0x40, 0x48, 0x07, 0x08, 0x08, 0x11, 0x19, 0x11, 0x19, 0x0f, 0x17, 0x06, 0x47, ++ 0x17, 0x06, 0x47, 0x40, 0x40, 0x40, 0x15, 0x0f, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x0e, 0x28, ++ 0x27, 0x18, 0x07, 0x19, 0x18, 0x11, 0x40, 0x2c, 0x17, 0x0f, 0x40, 0x0f, 0x0f, 0x0e, 0x12, ++ 0x0f, 0x1a, 0x12, 0x12, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x13, 0x01, 0x4d, 0x40, 0x0c, ++ 0x4a, 0x53, 0x29, 0x40, 0x01, 0x40, 0x40, 0x05, 0x0f, 0x01, 0x05, 0x40, 0x11, 0x43, 0x05, ++ 0x0e, 0x20, 0x20, 0x07, 0x07, 0x06, 0x22, 0x0e, 0x12, 0x07, 0x4c, 0x27, 0x14, 0x0e, 0x40, ++ 0x41, 0x04, 0x40, 0x40, 0x40, 0x01, 0x01, 0x45, 0x44, 0x02, 0x44, 0x43, 0x04, 0x45, 0x4c, ++ 0x4c, 0x05, 0x45, 0x4d, 0x4c, 0x4c, 0x05, 0x0b, 0x0a, 0x0c, 0x45, 0x44, 0x02, 0x44, 0x43, ++ 0x04, 0x45, 0x4c, 0x4c, 0x05, 0x45, 0x4d, 0x4c, 0x4c, 0x05, 0x0b, 0x0a, 0x0c, 0x1a, 0x46, ++ 0x1e, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x0e, 0x02, 0x16, 0x05, 0x46, 0x19, ++ 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, ++ 0x07, 0x09, 0x09, 0x12, 0x1a, 0x12, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, ++ 0x40, 0x40, 0x14, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, ++ 0x19, 0x12, 0x41, 0x2b, 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x13, 0x0e, 0x1c, 0x13, 0x13, ++ 0x0e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x14, 0x01, 0x4d, 0x40, 0x0b, 0x4a, 0x54, 0x29, 0x40, ++ 0x01, 0x40, 0x40, 0x05, 0x0f, 0x01, 0x06, 0x40, 0x11, 0x42, 0x06, 0x10, 0x22, 0x22, 0x07, ++ 0x07, 0x06, 0x21, 0x0e, 0x12, 0x07, 0x4b, 0x27, 0x15, 0x0e, 0x40, 0x41, 0x03, 0x40, 0x40, ++ 0x40, 0x01, 0x01, 0x45, 0x43, 0x02, 0x43, 0x42, 0x05, 0x45, 0x4b, 0x4b, 0x06, 0x45, 0x4d, ++ 0x4b, 0x4b, 0x06, 0x0c, 0x0a, 0x0d, 0x45, 0x43, 0x02, 0x43, 0x42, 0x05, 0x45, 0x4b, 0x4b, ++ 0x06, 0x45, 0x4d, 0x4b, 0x4b, 0x06, 0x0c, 0x0a, 0x0d, 0x1a, 0x46, 0x20, 0x40, 0x49, 0x40, ++ 0x01, 0x07, 0x01, 0x0a, 0x0a, 0x10, 0x02, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, ++ 0x46, 0x19, 0x07, 0x40, 0x16, 0x05, 0x46, 0x19, 0x07, 0x40, 0x49, 0x07, 0x09, 0x09, 0x12, ++ 0x1a, 0x12, 0x1a, 0x0e, 0x17, 0x05, 0x46, 0x17, 0x05, 0x46, 0x40, 0x40, 0x40, 0x13, 0x0e, ++ 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x0d, 0x29, 0x27, 0x19, 0x07, 0x1a, 0x19, 0x12, 0x41, 0x2a, ++ 0x16, 0x0e, 0x40, 0x0f, 0x0e, 0x0d, 0x14, 0x0e, 0x1d, 0x14, 0x14, 0x0e, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x15, 0x01, 0x4c, 0x40, 0x0a, 0x4b, 0x55, 0x29, 0x40, 0x01, 0x40, 0x40, 0x04, ++ 0x0f, 0x01, 0x08, 0x40, 0x11, 0x41, 0x08, 0x12, 0x25, 0x25, 0x07, 0x07, 0x06, 0x1f, 0x0e, ++ 0x13, 0x07, 0x4a, 0x27, 0x16, 0x0e, 0x40, 0x41, 0x02, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, ++ 0x42, 0x03, 0x42, 0x41, 0x06, 0x44, 0x4a, 0x4a, 0x08, 0x44, 0x4c, 0x4a, 0x4a, 0x08, 0x0d, ++ 0x0b, 0x0e, 0x44, 0x42, 0x03, 0x42, 0x41, 0x06, 0x44, 0x4a, 0x4a, 0x08, 0x44, 0x4c, 0x4a, ++ 0x4a, 0x08, 0x0d, 0x0b, 0x0e, 0x1b, 0x46, 0x22, 0x40, 0x49, 0x40, 0x01, 0x07, 0x01, 0x0b, ++ 0x0b, 0x12, 0x03, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, ++ 0x16, 0x04, 0x46, 0x19, 0x07, 0x40, 0x49, 0x07, 0x09, 0x09, 0x13, 0x1b, 0x13, 0x1b, 0x0e, ++ 0x17, 0x04, 0x46, 0x17, 0x04, 0x46, 0x40, 0x40, 0x40, 0x12, 0x0e, 0x0e, 0x40, 0x0f, 0x0e, ++ 0x0c, 0x0c, 0x29, 0x27, 0x19, 0x07, 0x1b, 0x19, 0x13, 0x41, 0x29, 0x16, 0x0e, 0x40, 0x0f, ++ 0x0e, 0x0c, 0x15, 0x0e, 0x1e, 0x15, 0x15, 0x0e, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x15, 0x01, ++ 0x4c, 0x40, 0x09, 0x4c, 0x56, 0x29, 0x40, 0x01, 0x40, 0x40, 0x03, 0x0f, 0x01, 0x09, 0x40, ++ 0x11, 0x40, 0x09, 0x13, 0x27, 0x27, 0x07, 0x07, 0x05, 0x1d, 0x0d, 0x13, 0x07, 0x4a, 0x27, ++ 0x17, 0x0d, 0x40, 0x42, 0x01, 0x40, 0x40, 0x40, 0x01, 0x01, 0x44, 0x42, 0x03, 0x42, 0x40, ++ 0x07, 0x44, 0x4a, 0x4a, 0x09, 0x44, 0x4c, 0x4a, 0x4a, 0x09, 0x0d, 0x0b, 0x0f, 0x44, 0x42, ++ 0x03, 0x42, 0x40, 0x07, 0x44, 0x4a, 0x4a, 0x09, 0x44, 0x4c, 0x4a, 0x4a, 0x09, 0x0d, 0x0b, ++ 0x0f, 0x1b, 0x46, 0x23, 0x40, 0x4a, 0x40, 0x01, 0x07, 0x01, 0x0b, 0x0b, 0x13, 0x03, 0x15, ++ 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, 0x07, 0x40, 0x15, 0x03, 0x46, 0x19, ++ 0x07, 0x40, 0x4a, 0x07, 0x09, 0x09, 0x13, 0x1b, 0x13, 0x1b, 0x0d, 0x17, 0x03, 0x46, 0x17, ++ 0x03, 0x46, 0x40, 0x40, 0x40, 0x11, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x29, 0x27, ++ 0x19, 0x07, 0x1b, 0x19, 0x13, 0x42, 0x27, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x15, 0x0d, ++ 0x1f, 0x15, 0x15, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x16, 0x02, 0x4b, 0x40, 0x09, 0x4c, ++ 0x56, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x03, 0x0f, 0x02, 0x0b, 0x40, 0x12, 0x01, 0x0b, 0x15, ++ 0x2a, 0x2a, 0x07, 0x07, 0x05, 0x1c, 0x0d, 0x14, 0x07, 0x49, 0x27, 0x19, 0x0d, 0x40, 0x42, ++ 0x01, 0x40, 0x40, 0x40, 0x02, 0x02, 0x43, 0x41, 0x04, 0x41, 0x01, 0x09, 0x43, 0x49, 0x49, ++ 0x0b, 0x43, 0x4b, 0x49, 0x49, 0x0b, 0x0e, 0x0c, 0x11, 0x43, 0x41, 0x04, 0x41, 0x01, 0x09, ++ 0x43, 0x49, 0x49, 0x0b, 0x43, 0x4b, 0x49, 0x49, 0x0b, 0x0e, 0x0c, 0x11, 0x1c, 0x45, 0x25, ++ 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0c, 0x0c, 0x15, 0x04, 0x15, 0x03, 0x45, 0x1a, 0x07, ++ 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x03, 0x45, 0x1a, 0x07, 0x40, 0x4a, 0x07, ++ 0x0a, 0x0a, 0x14, 0x1c, 0x14, 0x1c, 0x0d, 0x17, 0x03, 0x45, 0x17, 0x03, 0x45, 0x40, 0x40, ++ 0x40, 0x11, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x0b, 0x2a, 0x27, 0x1a, 0x07, 0x1c, 0x1a, ++ 0x14, 0x42, 0x26, 0x15, 0x0d, 0x40, 0x0f, 0x0d, 0x0b, 0x16, 0x0d, 0x21, 0x16, 0x16, 0x0d, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x3e, 0x17, 0x02, 0x4a, 0x40, 0x08, 0x4d, 0x57, 0x2a, 0x40, 0x02, ++ 0x40, 0x40, 0x02, 0x0f, 0x02, 0x0d, 0x40, 0x12, 0x02, 0x0d, 0x17, 0x2c, 0x2c, 0x07, 0x07, ++ 0x05, 0x1a, 0x0d, 0x15, 0x07, 0x48, 0x27, 0x1a, 0x0d, 0x40, 0x42, 0x00, 0x40, 0x40, 0x40, ++ 0x02, 0x02, 0x42, 0x40, 0x05, 0x40, 0x02, 0x0a, 0x42, 0x48, 0x48, 0x0d, 0x42, 0x4a, 0x48, ++ 0x48, 0x0d, 0x0f, 0x0d, 0x12, 0x42, 0x40, 0x05, 0x40, 0x02, 0x0a, 0x42, 0x48, 0x48, 0x0d, ++ 0x42, 0x4a, 0x48, 0x48, 0x0d, 0x0f, 0x0d, 0x12, 0x1d, 0x45, 0x27, 0x40, 0x4a, 0x40, 0x02, ++ 0x07, 0x02, 0x0d, 0x0d, 0x17, 0x05, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, ++ 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, 0x07, 0x0a, 0x0a, 0x15, 0x1d, ++ 0x15, 0x1d, 0x0d, 0x17, 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, 0x40, 0x10, 0x0d, 0x0d, ++ 0x40, 0x0f, 0x0d, 0x0a, 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x15, 0x42, 0x25, 0x15, ++ 0x0d, 0x40, 0x0f, 0x0d, 0x0a, 0x17, 0x0d, 0x22, 0x17, 0x17, 0x0d, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x3e, 0x18, 0x02, 0x4a, 0x40, 0x07, 0x4d, 0x58, 0x2a, 0x40, 0x02, 0x40, 0x40, 0x02, 0x0f, ++ 0x02, 0x0e, 0x40, 0x12, 0x03, 0x0e, 0x19, 0x2f, 0x2f, 0x07, 0x07, 0x05, 0x19, 0x0d, 0x15, ++ 0x07, 0x47, 0x27, 0x1b, 0x0d, 0x40, 0x42, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x42, 0x00, ++ 0x05, 0x00, 0x03, 0x0b, 0x42, 0x47, 0x47, 0x0e, 0x42, 0x4a, 0x47, 0x47, 0x0e, 0x10, 0x0d, ++ 0x13, 0x42, 0x00, 0x05, 0x00, 0x03, 0x0b, 0x42, 0x47, 0x47, 0x0e, 0x42, 0x4a, 0x47, 0x47, ++ 0x0e, 0x10, 0x0d, 0x13, 0x1d, 0x45, 0x29, 0x40, 0x4a, 0x40, 0x02, 0x07, 0x02, 0x0d, 0x0d, ++ 0x19, 0x05, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, 0x02, 0x45, 0x1a, 0x07, 0x40, 0x15, ++ 0x02, 0x45, 0x1a, 0x07, 0x40, 0x4a, 0x07, 0x0a, 0x0a, 0x15, 0x1d, 0x15, 0x1d, 0x0d, 0x17, ++ 0x02, 0x45, 0x17, 0x02, 0x45, 0x40, 0x40, 0x40, 0x0f, 0x0d, 0x0d, 0x40, 0x0f, 0x0d, 0x0a, ++ 0x0a, 0x2a, 0x27, 0x1a, 0x07, 0x1d, 0x1a, 0x15, 0x42, 0x24, 0x15, 0x0d, 0x40, 0x0f, 0x0d, ++ 0x0a, 0x18, 0x0d, 0x23, 0x18, 0x18, 0x0d, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x19, 0x03, 0x49, ++ 0x40, 0x06, 0x4e, 0x59, 0x2b, 0x40, 0x03, 0x40, 0x40, 0x01, 0x0f, 0x03, 0x10, 0x40, 0x13, ++ 0x04, 0x10, 0x1b, 0x31, 0x31, 0x07, 0x07, 0x04, 0x17, 0x0c, 0x16, 0x07, 0x46, 0x27, 0x1c, ++ 0x0c, 0x40, 0x43, 0x41, 0x40, 0x40, 0x40, 0x03, 0x03, 0x41, 0x01, 0x06, 0x01, 0x04, 0x0c, ++ 0x41, 0x46, 0x46, 0x10, 0x41, 0x49, 0x46, 0x46, 0x10, 0x11, 0x0e, 0x14, 0x41, 0x01, 0x06, ++ 0x01, 0x04, 0x0c, 0x41, 0x46, 0x46, 0x10, 0x41, 0x49, 0x46, 0x46, 0x10, 0x11, 0x0e, 0x14, ++ 0x1e, 0x44, 0x2b, 0x40, 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0e, 0x0e, 0x1b, 0x06, 0x14, 0x01, ++ 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x01, 0x44, 0x1b, 0x07, ++ 0x40, 0x4b, 0x07, 0x0b, 0x0b, 0x16, 0x1e, 0x16, 0x1e, 0x0c, 0x17, 0x01, 0x44, 0x17, 0x01, ++ 0x44, 0x40, 0x40, 0x40, 0x0e, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x09, 0x2b, 0x27, 0x1b, ++ 0x07, 0x1e, 0x1b, 0x16, 0x43, 0x22, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x09, 0x19, 0x0c, 0x24, ++ 0x19, 0x19, 0x0c, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x1a, 0x03, 0x48, 0x40, 0x05, 0x4f, 0x5a, ++ 0x2b, 0x40, 0x03, 0x40, 0x40, 0x00, 0x0f, 0x03, 0x11, 0x40, 0x13, 0x06, 0x11, 0x1d, 0x34, ++ 0x34, 0x07, 0x07, 0x04, 0x16, 0x0c, 0x17, 0x07, 0x45, 0x27, 0x1e, 0x0c, 0x40, 0x43, 0x42, ++ 0x40, 0x40, 0x40, 0x03, 0x03, 0x40, 0x02, 0x07, 0x02, 0x06, 0x0e, 0x40, 0x45, 0x45, 0x11, ++ 0x40, 0x48, 0x45, 0x45, 0x11, 0x12, 0x0f, 0x16, 0x40, 0x02, 0x07, 0x02, 0x06, 0x0e, 0x40, ++ 0x45, 0x45, 0x11, 0x40, 0x48, 0x45, 0x45, 0x11, 0x12, 0x0f, 0x16, 0x1f, 0x44, 0x2d, 0x40, ++ 0x4b, 0x40, 0x03, 0x07, 0x03, 0x0f, 0x0f, 0x1d, 0x07, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, ++ 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, 0x07, 0x0b, ++ 0x0b, 0x17, 0x1f, 0x17, 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, 0x40, ++ 0x0d, 0x0c, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x17, ++ 0x43, 0x21, 0x14, 0x0c, 0x40, 0x0f, 0x0c, 0x08, 0x1a, 0x0c, 0x26, 0x1a, 0x1a, 0x0c, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x07, 0x3e, 0x1b, 0x03, 0x48, 0x40, 0x04, 0x4f, 0x5b, 0x2b, 0x40, 0x03, 0x40, ++ 0x40, 0x00, 0x0f, 0x03, 0x13, 0x40, 0x13, 0x07, 0x13, 0x1f, 0x36, 0x36, 0x07, 0x07, 0x04, ++ 0x14, 0x0c, 0x17, 0x07, 0x44, 0x27, 0x1f, 0x0c, 0x40, 0x43, 0x43, 0x40, 0x40, 0x40, 0x03, ++ 0x03, 0x40, 0x03, 0x07, 0x03, 0x07, 0x0f, 0x40, 0x44, 0x44, 0x13, 0x40, 0x48, 0x44, 0x44, ++ 0x13, 0x13, 0x0f, 0x17, 0x40, 0x03, 0x07, 0x03, 0x07, 0x0f, 0x40, 0x44, 0x44, 0x13, 0x40, ++ 0x48, 0x44, 0x44, 0x13, 0x13, 0x0f, 0x17, 0x1f, 0x44, 0x2f, 0x40, 0x4b, 0x40, 0x03, 0x07, ++ 0x03, 0x0f, 0x0f, 0x1f, 0x07, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, ++ 0x07, 0x40, 0x14, 0x00, 0x44, 0x1b, 0x07, 0x40, 0x4b, 0x07, 0x0b, 0x0b, 0x17, 0x1f, 0x17, ++ 0x1f, 0x0c, 0x17, 0x00, 0x44, 0x17, 0x00, 0x44, 0x40, 0x40, 0x40, 0x0c, 0x0c, 0x0c, 0x40, ++ 0x0f, 0x0c, 0x08, 0x08, 0x2b, 0x27, 0x1b, 0x07, 0x1f, 0x1b, 0x17, 0x43, 0x20, 0x14, 0x0c, ++ 0x40, 0x0f, 0x0c, 0x08, 0x1b, 0x0c, 0x27, 0x1b, 0x1b, 0x0c, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, ++ 0x1c, 0x04, 0x47, 0x40, 0x03, 0x50, 0x5c, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x40, 0x0f, 0x04, ++ 0x14, 0x40, 0x14, 0x08, 0x14, 0x21, 0x39, 0x39, 0x07, 0x07, 0x03, 0x13, 0x0b, 0x18, 0x07, ++ 0x43, 0x27, 0x20, 0x0b, 0x40, 0x44, 0x44, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x04, 0x08, ++ 0x04, 0x08, 0x10, 0x00, 0x43, 0x43, 0x14, 0x00, 0x47, 0x43, 0x43, 0x14, 0x14, 0x10, 0x18, ++ 0x00, 0x04, 0x08, 0x04, 0x08, 0x10, 0x00, 0x43, 0x43, 0x14, 0x00, 0x47, 0x43, 0x43, 0x14, ++ 0x14, 0x10, 0x18, 0x20, 0x43, 0x31, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x21, ++ 0x08, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x40, ++ 0x43, 0x1c, 0x07, 0x40, 0x4c, 0x07, 0x0c, 0x0c, 0x18, 0x20, 0x18, 0x20, 0x0b, 0x17, 0x40, ++ 0x43, 0x17, 0x40, 0x43, 0x40, 0x40, 0x40, 0x0b, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x07, 0x07, ++ 0x2c, 0x27, 0x1c, 0x07, 0x20, 0x1c, 0x18, 0x44, 0x1f, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x07, ++ 0x1c, 0x0b, 0x28, 0x1c, 0x1c, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x1d, 0x04, 0x47, 0x40, ++ 0x02, 0x51, 0x5d, 0x2c, 0x40, 0x04, 0x40, 0x40, 0x41, 0x0f, 0x04, 0x16, 0x40, 0x14, 0x09, ++ 0x16, 0x22, 0x3b, 0x3b, 0x07, 0x07, 0x03, 0x11, 0x0b, 0x18, 0x07, 0x42, 0x27, 0x21, 0x0b, ++ 0x40, 0x44, 0x45, 0x40, 0x40, 0x40, 0x04, 0x04, 0x00, 0x05, 0x08, 0x05, 0x09, 0x11, 0x00, ++ 0x42, 0x42, 0x16, 0x00, 0x47, 0x42, 0x42, 0x16, 0x15, 0x10, 0x19, 0x00, 0x05, 0x08, 0x05, ++ 0x09, 0x11, 0x00, 0x42, 0x42, 0x16, 0x00, 0x47, 0x42, 0x42, 0x16, 0x15, 0x10, 0x19, 0x20, ++ 0x43, 0x32, 0x40, 0x4c, 0x40, 0x04, 0x07, 0x04, 0x10, 0x10, 0x22, 0x08, 0x13, 0x41, 0x43, ++ 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, ++ 0x4c, 0x07, 0x0c, 0x0c, 0x18, 0x20, 0x18, 0x20, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, ++ 0x40, 0x40, 0x40, 0x0a, 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, ++ 0x20, 0x1c, 0x18, 0x44, 0x1d, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x1d, 0x0b, 0x29, 0x1d, ++ 0x1d, 0x0b, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x1e, 0x04, 0x46, 0x40, 0x01, 0x51, 0x5e, 0x2c, ++ 0x40, 0x04, 0x40, 0x40, 0x41, 0x0f, 0x04, 0x18, 0x40, 0x14, 0x0b, 0x18, 0x24, 0x3e, 0x3e, ++ 0x07, 0x07, 0x03, 0x0f, 0x0b, 0x19, 0x07, 0x41, 0x27, 0x23, 0x0b, 0x40, 0x44, 0x46, 0x40, ++ 0x40, 0x40, 0x04, 0x04, 0x01, 0x06, 0x09, 0x06, 0x0b, 0x13, 0x01, 0x41, 0x41, 0x18, 0x01, ++ 0x46, 0x41, 0x41, 0x18, 0x16, 0x11, 0x1b, 0x01, 0x06, 0x09, 0x06, 0x0b, 0x13, 0x01, 0x41, ++ 0x41, 0x18, 0x01, 0x46, 0x41, 0x41, 0x18, 0x16, 0x11, 0x1b, 0x21, 0x43, 0x34, 0x40, 0x4c, ++ 0x40, 0x04, 0x07, 0x04, 0x11, 0x11, 0x24, 0x09, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, ++ 0x41, 0x43, 0x1c, 0x07, 0x40, 0x13, 0x41, 0x43, 0x1c, 0x07, 0x40, 0x4c, 0x07, 0x0c, 0x0c, ++ 0x19, 0x21, 0x19, 0x21, 0x0b, 0x17, 0x41, 0x43, 0x17, 0x41, 0x43, 0x40, 0x40, 0x40, 0x09, ++ 0x0b, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x06, 0x2c, 0x27, 0x1c, 0x07, 0x21, 0x1c, 0x19, 0x44, ++ 0x1c, 0x13, 0x0b, 0x40, 0x0f, 0x0b, 0x06, 0x1e, 0x0b, 0x2b, 0x1e, 0x1e, 0x0b, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x07, 0x3e, 0x1f, 0x05, 0x45, 0x40, 0x00, 0x52, 0x5f, 0x2d, 0x40, 0x05, 0x40, 0x40, ++ 0x42, 0x0f, 0x05, 0x19, 0x40, 0x15, 0x0c, 0x19, 0x26, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0e, ++ 0x0a, 0x1a, 0x07, 0x40, 0x27, 0x24, 0x0a, 0x40, 0x45, 0x47, 0x40, 0x40, 0x40, 0x05, 0x05, ++ 0x02, 0x07, 0x0a, 0x07, 0x0c, 0x14, 0x02, 0x40, 0x40, 0x19, 0x02, 0x45, 0x40, 0x40, 0x19, ++ 0x17, 0x12, 0x1c, 0x02, 0x07, 0x0a, 0x07, 0x0c, 0x14, 0x02, 0x40, 0x40, 0x19, 0x02, 0x45, ++ 0x40, 0x40, 0x19, 0x17, 0x12, 0x1c, 0x22, 0x42, 0x36, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, ++ 0x12, 0x12, 0x26, 0x0a, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, ++ 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x4d, 0x07, 0x0d, 0x0d, 0x1a, 0x22, 0x1a, 0x22, ++ 0x0a, 0x17, 0x42, 0x42, 0x17, 0x42, 0x42, 0x40, 0x40, 0x40, 0x08, 0x0a, 0x0a, 0x40, 0x0f, ++ 0x0a, 0x05, 0x05, 0x2d, 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a, 0x45, 0x1b, 0x12, 0x0a, 0x40, ++ 0x0f, 0x0a, 0x05, 0x1f, 0x0a, 0x2c, 0x1f, 0x1f, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x20, ++ 0x05, 0x45, 0x40, 0x40, 0x52, 0x60, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x42, 0x0f, 0x05, 0x1b, ++ 0x40, 0x15, 0x0d, 0x1b, 0x28, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0c, 0x0a, 0x1a, 0x07, 0x00, ++ 0x27, 0x25, 0x0a, 0x40, 0x45, 0x48, 0x40, 0x40, 0x40, 0x05, 0x05, 0x02, 0x08, 0x0a, 0x08, ++ 0x0d, 0x15, 0x02, 0x00, 0x00, 0x1b, 0x02, 0x45, 0x00, 0x00, 0x1b, 0x18, 0x12, 0x1d, 0x02, ++ 0x08, 0x0a, 0x08, 0x0d, 0x15, 0x02, 0x00, 0x00, 0x1b, 0x02, 0x45, 0x00, 0x00, 0x1b, 0x18, ++ 0x12, 0x1d, 0x22, 0x42, 0x38, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x12, 0x12, 0x28, 0x0a, ++ 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x42, 0x42, ++ 0x1d, 0x07, 0x40, 0x4d, 0x07, 0x0d, 0x0d, 0x1a, 0x22, 0x1a, 0x22, 0x0a, 0x17, 0x42, 0x42, ++ 0x17, 0x42, 0x42, 0x40, 0x40, 0x40, 0x07, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x05, 0x2d, ++ 0x27, 0x1d, 0x07, 0x22, 0x1d, 0x1a, 0x45, 0x1a, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x05, 0x20, ++ 0x0a, 0x2d, 0x20, 0x20, 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x21, 0x05, 0x44, 0x40, 0x41, ++ 0x53, 0x61, 0x2d, 0x40, 0x05, 0x40, 0x40, 0x43, 0x0f, 0x05, 0x1c, 0x40, 0x15, 0x0e, 0x1c, ++ 0x2a, 0x3e, 0x3e, 0x07, 0x07, 0x02, 0x0b, 0x0a, 0x1b, 0x07, 0x01, 0x27, 0x26, 0x0a, 0x40, ++ 0x45, 0x49, 0x40, 0x40, 0x40, 0x05, 0x05, 0x03, 0x09, 0x0b, 0x09, 0x0e, 0x16, 0x03, 0x01, ++ 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e, 0x03, 0x09, 0x0b, 0x09, 0x0e, ++ 0x16, 0x03, 0x01, 0x01, 0x1c, 0x03, 0x44, 0x01, 0x01, 0x1c, 0x19, 0x13, 0x1e, 0x23, 0x42, ++ 0x3a, 0x40, 0x4d, 0x40, 0x05, 0x07, 0x05, 0x13, 0x13, 0x2a, 0x0b, 0x12, 0x43, 0x42, 0x1d, ++ 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x12, 0x43, 0x42, 0x1d, 0x07, 0x40, 0x4d, ++ 0x07, 0x0d, 0x0d, 0x1b, 0x23, 0x1b, 0x23, 0x0a, 0x17, 0x43, 0x42, 0x17, 0x43, 0x42, 0x40, ++ 0x40, 0x40, 0x06, 0x0a, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x04, 0x2d, 0x27, 0x1d, 0x07, 0x23, ++ 0x1d, 0x1b, 0x45, 0x18, 0x12, 0x0a, 0x40, 0x0f, 0x0a, 0x04, 0x21, 0x0a, 0x2e, 0x21, 0x21, ++ 0x0a, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x22, 0x06, 0x43, 0x40, 0x42, 0x54, 0x62, 0x2e, 0x40, ++ 0x06, 0x40, 0x40, 0x44, 0x0f, 0x06, 0x1e, 0x40, 0x16, 0x10, 0x1e, 0x2c, 0x3e, 0x3e, 0x07, ++ 0x07, 0x01, 0x09, 0x09, 0x1c, 0x07, 0x02, 0x27, 0x28, 0x09, 0x40, 0x46, 0x4a, 0x40, 0x40, ++ 0x40, 0x06, 0x06, 0x04, 0x0a, 0x0c, 0x0a, 0x10, 0x18, 0x04, 0x02, 0x02, 0x1e, 0x04, 0x43, ++ 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20, 0x04, 0x0a, 0x0c, 0x0a, 0x10, 0x18, 0x04, 0x02, 0x02, ++ 0x1e, 0x04, 0x43, 0x02, 0x02, 0x1e, 0x1a, 0x14, 0x20, 0x24, 0x41, 0x3c, 0x40, 0x4e, 0x40, ++ 0x06, 0x07, 0x06, 0x14, 0x14, 0x2c, 0x0c, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, ++ 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, 0x07, 0x0e, 0x0e, 0x1c, ++ 0x24, 0x1c, 0x24, 0x09, 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, 0x40, 0x05, 0x09, ++ 0x09, 0x40, 0x0f, 0x09, 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c, 0x46, 0x17, ++ 0x11, 0x09, 0x40, 0x0f, 0x09, 0x03, 0x22, 0x09, 0x30, 0x22, 0x22, 0x09, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x3e, 0x23, 0x06, 0x43, 0x40, 0x43, 0x54, 0x63, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x44, ++ 0x0f, 0x06, 0x1f, 0x40, 0x16, 0x11, 0x1f, 0x2e, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x08, 0x09, ++ 0x1c, 0x07, 0x03, 0x27, 0x29, 0x09, 0x40, 0x46, 0x4b, 0x40, 0x40, 0x40, 0x06, 0x06, 0x04, ++ 0x0b, 0x0c, 0x0b, 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, 0x03, 0x1f, 0x1b, ++ 0x14, 0x21, 0x04, 0x0b, 0x0c, 0x0b, 0x11, 0x19, 0x04, 0x03, 0x03, 0x1f, 0x04, 0x43, 0x03, ++ 0x03, 0x1f, 0x1b, 0x14, 0x21, 0x24, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x14, ++ 0x14, 0x2e, 0x0c, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, ++ 0x11, 0x44, 0x41, 0x1e, 0x07, 0x40, 0x4e, 0x07, 0x0e, 0x0e, 0x1c, 0x24, 0x1c, 0x24, 0x09, ++ 0x17, 0x44, 0x41, 0x17, 0x44, 0x41, 0x40, 0x40, 0x40, 0x04, 0x09, 0x09, 0x40, 0x0f, 0x09, ++ 0x03, 0x03, 0x2e, 0x27, 0x1e, 0x07, 0x24, 0x1e, 0x1c, 0x46, 0x16, 0x11, 0x09, 0x40, 0x0f, ++ 0x09, 0x03, 0x23, 0x09, 0x31, 0x23, 0x23, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x24, 0x06, ++ 0x42, 0x40, 0x44, 0x55, 0x64, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x45, 0x0f, 0x06, 0x21, 0x40, ++ 0x16, 0x12, 0x21, 0x30, 0x3e, 0x3e, 0x07, 0x07, 0x01, 0x06, 0x09, 0x1d, 0x07, 0x04, 0x27, ++ 0x2a, 0x09, 0x40, 0x46, 0x4c, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c, 0x12, ++ 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, 0x22, 0x05, 0x0c, ++ 0x0d, 0x0c, 0x12, 0x1a, 0x05, 0x04, 0x04, 0x21, 0x05, 0x42, 0x04, 0x04, 0x21, 0x1c, 0x15, ++ 0x22, 0x25, 0x41, 0x3e, 0x40, 0x4e, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x30, 0x0d, 0x11, ++ 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, 0x07, 0x40, 0x11, 0x45, 0x41, 0x1e, ++ 0x07, 0x40, 0x4e, 0x07, 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x09, 0x17, 0x45, 0x41, 0x17, ++ 0x45, 0x41, 0x40, 0x40, 0x40, 0x03, 0x09, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x02, 0x2e, 0x27, ++ 0x1e, 0x07, 0x25, 0x1e, 0x1d, 0x46, 0x15, 0x11, 0x09, 0x40, 0x0f, 0x09, 0x02, 0x24, 0x09, ++ 0x32, 0x24, 0x24, 0x09, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x24, 0x06, 0x42, 0x40, 0x45, 0x56, ++ 0x65, 0x2e, 0x40, 0x06, 0x40, 0x40, 0x46, 0x0f, 0x06, 0x22, 0x40, 0x16, 0x13, 0x22, 0x31, ++ 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x04, 0x08, 0x1d, 0x07, 0x04, 0x27, 0x2b, 0x08, 0x40, 0x47, ++ 0x4d, 0x40, 0x40, 0x40, 0x06, 0x06, 0x05, 0x0c, 0x0d, 0x0c, 0x13, 0x1b, 0x05, 0x04, 0x04, ++ 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x05, 0x0c, 0x0d, 0x0c, 0x13, 0x1b, ++ 0x05, 0x04, 0x04, 0x22, 0x05, 0x42, 0x04, 0x04, 0x22, 0x1c, 0x15, 0x23, 0x25, 0x41, 0x3e, ++ 0x40, 0x4f, 0x40, 0x06, 0x07, 0x06, 0x15, 0x15, 0x31, 0x0d, 0x10, 0x46, 0x41, 0x1e, 0x07, ++ 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x10, 0x46, 0x41, 0x1e, 0x07, 0x40, 0x4f, 0x07, ++ 0x0e, 0x0e, 0x1d, 0x25, 0x1d, 0x25, 0x08, 0x17, 0x46, 0x41, 0x17, 0x46, 0x41, 0x40, 0x40, ++ 0x40, 0x02, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2e, 0x27, 0x1e, 0x07, 0x25, 0x1e, ++ 0x1d, 0x47, 0x13, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x01, 0x24, 0x08, 0x33, 0x24, 0x24, 0x08, ++ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x07, 0x3e, 0x25, 0x07, 0x41, 0x40, 0x45, 0x56, 0x65, 0x2f, 0x40, 0x07, ++ 0x40, 0x40, 0x46, 0x0f, 0x07, 0x24, 0x40, 0x17, 0x15, 0x24, 0x33, 0x3e, 0x3e, 0x07, 0x07, ++ 0x00, 0x03, 0x08, 0x1e, 0x07, 0x05, 0x27, 0x2d, 0x08, 0x40, 0x47, 0x4d, 0x40, 0x40, 0x40, ++ 0x07, 0x07, 0x06, 0x0d, 0x0e, 0x0d, 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, 0x06, 0x41, 0x05, ++ 0x05, 0x24, 0x1d, 0x16, 0x25, 0x06, 0x0d, 0x0e, 0x0d, 0x15, 0x1d, 0x06, 0x05, 0x05, 0x24, ++ 0x06, 0x41, 0x05, 0x05, 0x24, 0x1d, 0x16, 0x25, 0x26, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, ++ 0x07, 0x07, 0x16, 0x16, 0x33, 0x0e, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, ++ 0x1f, 0x07, 0x40, 0x10, 0x46, 0x40, 0x1f, 0x07, 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1e, 0x26, ++ 0x1e, 0x26, 0x08, 0x17, 0x46, 0x40, 0x17, 0x46, 0x40, 0x40, 0x40, 0x40, 0x02, 0x08, 0x08, ++ 0x40, 0x0f, 0x08, 0x01, 0x01, 0x2f, 0x27, 0x1f, 0x07, 0x26, 0x1f, 0x1e, 0x47, 0x12, 0x10, ++ 0x08, 0x40, 0x0f, 0x08, 0x01, 0x25, 0x08, 0x35, 0x25, 0x25, 0x08, 0x40, 0x40, 0x40, 0x40, ++ 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, ++ 0x3e, 0x26, 0x07, 0x40, 0x40, 0x46, 0x57, 0x66, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, ++ 0x07, 0x26, 0x40, 0x17, 0x16, 0x26, 0x35, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x01, 0x08, 0x1f, ++ 0x07, 0x06, 0x27, 0x2e, 0x08, 0x40, 0x47, 0x4e, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0e, ++ 0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, 0x26, 0x1e, 0x17, ++ 0x26, 0x07, 0x0e, 0x0f, 0x0e, 0x16, 0x1e, 0x07, 0x06, 0x06, 0x26, 0x07, 0x40, 0x06, 0x06, ++ 0x26, 0x1e, 0x17, 0x26, 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, ++ 0x35, 0x0f, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, ++ 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, ++ 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, 0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, ++ 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08, ++ 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x27, 0x07, 0x40, ++ 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, 0x07, 0x27, 0x40, 0x17, ++ 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, 0x07, 0x27, 0x2f, ++ 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x17, 0x1f, ++ 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f, 0x0f, ++ 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, ++ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47, ++ 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, ++ 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47, ++ 0x40, 0x40, 0x40, 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f, ++ 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37, ++ 0x27, 0x27, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}; +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c +new file mode 100644 +index 000000000000..9b5cf70188db +--- /dev/null ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c +@@ -0,0 +1,817 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Rockchip Video Decoder HEVC backend ++ * ++ * Copyright (C) 2023 Collabora, Ltd. ++ * Sebastian Fricke ++ * ++ * Copyright (C) 2019 Collabora, Ltd. ++ * Boris Brezillon ++ * ++ * Copyright (C) 2016 Rockchip Electronics Co., Ltd. ++ * Jeffy Chen ++ */ ++ ++#include ++ ++#include "rkvdec.h" ++#include "rkvdec-regs.h" ++#include "rkvdec-hevc-data.c" ++ ++/* Size in u8/u32 units. */ ++#define RKV_SCALING_LIST_SIZE 1360 ++#define RKV_PPS_SIZE (80 / 4) ++#define RKV_PPS_LEN 64 ++#define RKV_RPS_SIZE (32 / 4) ++#define RKV_RPS_LEN 600 ++ ++struct rkvdec_sps_pps_packet { ++ u32 info[RKV_PPS_SIZE]; ++}; ++ ++struct rkvdec_rps_packet { ++ u32 info[RKV_RPS_SIZE]; ++}; ++ ++struct rkvdec_ps_field { ++ u16 offset; ++ u8 len; ++}; ++ ++#define PS_FIELD(_offset, _len) \ ++ ((struct rkvdec_ps_field){ _offset, _len }) ++ ++/* SPS */ ++#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4) ++#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4) ++#define CHROMA_FORMAT_IDC PS_FIELD(8, 2) ++#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13) ++#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13) ++#define BIT_DEPTH_LUMA PS_FIELD(36, 4) ++#define BIT_DEPTH_CHROMA PS_FIELD(40, 4) ++#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5) ++#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2) ++#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3) ++#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3) ++#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2) ++#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3) ++#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3) ++#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1) ++#define AMP_ENABLED_FLAG PS_FIELD(66, 1) ++#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1) ++#define PCM_ENABLED_FLAG PS_FIELD(68, 1) ++#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4) ++#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4) ++#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1) ++#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3) ++#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3) ++#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7) ++#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1) ++#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6) ++#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1) ++#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1) ++/* PPS */ ++#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6) ++#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4) ++#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1) ++#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1) ++#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13) ++#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1) ++#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1) ++#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4) ++#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4) ++#define INIT_QP_MINUS26 PS_FIELD(163, 7) ++#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1) ++#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1) ++#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1) ++#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3) ++#define PPS_CB_QP_OFFSET PS_FIELD(176, 5) ++#define PPS_CR_QP_OFFSET PS_FIELD(181, 5) ++#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1) ++#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1) ++#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1) ++#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1) ++#define TILES_ENABLED_FLAG PS_FIELD(190, 1) ++#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1) ++#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1) ++#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1) ++#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1) ++#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1) ++#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4) ++#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4) ++#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1) ++#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3) ++#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1) ++#define NUM_TILE_COLUMNS PS_FIELD(212, 5) ++#define NUM_TILE_ROWS PS_FIELD(217, 5) ++#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8) ++#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8) ++#define SCALING_LIST_ADDRESS PS_FIELD(592, 32) ++ ++/* Data structure describing auxiliary buffer format. */ ++struct rkvdec_hevc_priv_tbl { ++ u8 cabac_table[RKV_CABAC_TABLE_SIZE]; ++ u8 scaling_list[RKV_SCALING_LIST_SIZE]; ++ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN]; ++ struct rkvdec_rps_packet rps[RKV_RPS_LEN]; ++}; ++ ++struct rkvdec_hevc_run { ++ struct rkvdec_run base; ++ const struct v4l2_ctrl_hevc_slice_params *slices_params; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params; ++ const struct v4l2_ctrl_hevc_sps *sps; ++ const struct v4l2_ctrl_hevc_pps *pps; ++ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix; ++ int num_slices; ++}; ++ ++struct rkvdec_hevc_ctx { ++ struct rkvdec_aux_buf priv_tbl; ++ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache; ++}; ++ ++struct scaling_factor { ++ u8 scalingfactor0[1248]; ++ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/ ++ u8 scalingdc[12]; /*N1005 Vienna Meeting*/ ++ u8 reserved[4]; /*16Bytes align*/ ++}; ++ ++static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value) ++{ ++ u8 bit = field.offset % 32, word = field.offset / 32; ++ u64 mask = GENMASK_ULL(bit + field.len - 1, bit); ++ u64 val = ((u64)value << bit) & mask; ++ ++ buf[word] &= ~mask; ++ buf[word] |= val; ++ if (bit + field.len > 32) { ++ buf[word + 1] &= ~(mask >> 32); ++ buf[word + 1] |= val >> 32; ++ } ++} ++ ++static void assemble_hw_pps(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ const struct v4l2_ctrl_hevc_sps *sps = run->sps; ++ const struct v4l2_ctrl_hevc_pps *pps = run->pps; ++ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; ++ struct rkvdec_sps_pps_packet *hw_ps; ++ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y; ++ u32 log2_min_cu_qp_delta_size, scaling_distance; ++ dma_addr_t scaling_list_address; ++ int i; ++ ++ /* ++ * HW read the SPS/PPS information from PPS packet index by PPS id. ++ * offset from the base can be calculated by PPS_id * 80 (size per PPS ++ * packet unit). so the driver copy SPS/PPS information to the exact PPS ++ * packet unit for HW accessing. ++ */ ++ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; ++ memset(hw_ps, 0, sizeof(*hw_ps)); ++ ++#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value) ++ /* write sps */ ++ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID); ++ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID); ++ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC); ++ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES); ++ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES); ++ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA); ++ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA); ++ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4, ++ LOG2_MAX_PIC_ORDER_CNT_LSB); ++ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size, ++ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE); ++ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3, ++ LOG2_MIN_LUMA_CODING_BLOCK_SIZE); ++ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2, ++ LOG2_MIN_TRANSFORM_BLOCK_SIZE); ++ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size, ++ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE); ++ WRITE_PPS(sps->max_transform_hierarchy_depth_inter, ++ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER); ++ WRITE_PPS(sps->max_transform_hierarchy_depth_intra, ++ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED), ++ SCALING_LIST_ENABLED_FLAG); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED), ++ AMP_ENABLED_FLAG); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET), ++ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG); ++ if (sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED) { ++ WRITE_PPS(1, PCM_ENABLED_FLAG); ++ WRITE_PPS(sps->pcm_sample_bit_depth_luma_minus1 + 1, ++ PCM_SAMPLE_BIT_DEPTH_LUMA); ++ WRITE_PPS(sps->pcm_sample_bit_depth_chroma_minus1 + 1, ++ PCM_SAMPLE_BIT_DEPTH_CHROMA); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED), ++ PCM_LOOP_FILTER_DISABLED_FLAG); ++ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size, ++ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE); ++ WRITE_PPS(sps->log2_min_pcm_luma_coding_block_size_minus3 + 3, ++ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE); ++ } ++ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT), ++ LONG_TERM_REF_PICS_PRESENT_FLAG); ++ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED), ++ SPS_TEMPORAL_MVP_ENABLED_FLAG); ++ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED), ++ STRONG_INTRA_SMOOTHING_ENABLED_FLAG); ++ ++ /* write pps */ ++ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); ++ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), ++ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), ++ OUTPUT_FLAG_PRESENT_FLAG); ++ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), ++ SIGN_DATA_HIDING_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), ++ CABAC_INIT_PRESENT_FLAG); ++ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, ++ NUM_REF_IDX_L0_DEFAULT_ACTIVE); ++ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, ++ NUM_REF_IDX_L1_DEFAULT_ACTIVE); ++ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED), ++ CONSTRAINED_INTRA_PRED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED), ++ TRANSFORM_SKIP_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED), ++ CU_QP_DELTA_ENABLED_FLAG); ++ ++ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3; ++ ctb_log2_size_y = min_cb_log2_size_y + ++ sps->log2_diff_max_min_luma_coding_block_size; ++ ctb_size_y = 1 << ctb_log2_size_y; ++ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth; ++ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE); ++ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET); ++ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT), ++ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED), ++ WEIGHTED_PRED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED), ++ WEIGHTED_BIPRED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED), ++ TRANSQUANT_BYPASS_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED), ++ TILES_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED), ++ ENTROPY_CODING_SYNC_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED), ++ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED), ++ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED), ++ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER), ++ PPS_DEBLOCKING_FILTER_DISABLED_FLAG); ++ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2); ++ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT), ++ LISTS_MODIFICATION_PRESENT_FLAG); ++ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL); ++ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT), ++ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG); ++ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS); ++ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS); ++ ++ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) { ++ /* Userspace also provide column width and row height for uniform spacing */ ++ for (i = 0; i <= pps->num_tile_columns_minus1; i++) ++ WRITE_PPS(pps->column_width_minus1[i], COLUMN_WIDTH(i)); ++ for (i = 0; i <= pps->num_tile_rows_minus1; i++) ++ WRITE_PPS(pps->row_height_minus1[i], ROW_HEIGHT(i)); ++ } else { ++ WRITE_PPS(((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, ++ COLUMN_WIDTH(0)); ++ WRITE_PPS(((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1, ++ ROW_HEIGHT(0)); ++ } ++ ++ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list); ++ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance; ++ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS); ++} ++ ++/* ++ * Creation of the Reference Picture Set memory blob for the hardware. ++ * The layout looks like this: ++ * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference) ++ * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references ++ * + 4 bits of the 13th reference) ++ * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and ++ * 21 bits for L1 (4 references + first bit of 5) ++ * [3] 32 bits of padding with 0s ++ * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11) ++ * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references) ++ * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32) ++ * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12) ++ * number of references (bit 13 - 16), remaining 16 bits of padding with 0s ++ * [7] 32 bits of padding with 0s ++ * ++ * Thus we have to set up padding in between reference 5 of the L1 list. ++ */ ++static void assemble_sw_rps(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_ctrl_hevc_sps *sps = run->sps; ++ const struct v4l2_ctrl_hevc_slice_params *sl_params; ++ const struct v4l2_hevc_dpb_entry *dpb; ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu; ++ struct rkvdec_rps_packet *hw_ps; ++ int i, j; ++ unsigned int lowdelay; ++ ++#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value) ++ ++#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1) ++#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4) ++#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1) ++#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4) ++ ++#define LOWDELAY PS_FIELD(182, 1) ++#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10) ++#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9) ++#define NUM_RPS_POC PS_FIELD(202, 4) ++ ++ for (j = 0; j < run->num_slices; j++) { ++ uint st_bit_offset = 0; ++ uint num_l0_refs = 0; ++ uint num_l1_refs = 0; ++ ++ sl_params = &run->slices_params[j]; ++ dpb = decode_params->dpb; ++ ++ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { ++ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1; ++ ++ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) ++ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1; ++ ++ lowdelay = 1; ++ } else { ++ lowdelay = 0; ++ } ++ ++ hw_ps = &priv_tbl->rps[j]; ++ memset(hw_ps, 0, sizeof(*hw_ps)); ++ ++ for (i = 0; i < num_l0_refs; i++) { ++ const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]]; ++ ++ WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE), ++ REF_PIC_LONG_TERM_L0(i)); ++ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i)); ++ ++ if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt) ++ lowdelay = 0; ++ } ++ ++ for (i = 0; i < num_l1_refs; i++) { ++ const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]]; ++ int is_long_term = ++ !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE); ++ ++ WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i)); ++ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i)); ++ ++ if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt) ++ lowdelay = 0; ++ } ++ ++ WRITE_RPS(lowdelay, LOWDELAY); ++ ++ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) { ++ if (sl_params->short_term_ref_pic_set_size) ++ st_bit_offset = sl_params->short_term_ref_pic_set_size; ++ else if (sps->num_short_term_ref_pic_sets > 1) ++ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1); ++ } ++ ++ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size, ++ LONG_TERM_RPS_BIT_OFFSET); ++ WRITE_RPS(sl_params->short_term_ref_pic_set_size, ++ SHORT_TERM_RPS_BIT_OFFSET); ++ ++ WRITE_RPS(decode_params->num_poc_st_curr_before + ++ decode_params->num_poc_st_curr_after + ++ decode_params->num_poc_lt_curr, ++ NUM_RPS_POC); ++ } ++} ++ ++/* ++ * Flip one or more matrices along their main diagonal and flatten them ++ * before writing it to the memory. ++ * Convert: ++ * ABCD AEIM ++ * EFGH => BFJN => AEIMBFJNCGKODHLP ++ * IJKL CGKO ++ * MNOP DHLP ++ */ ++static void transpose_and_flatten_matrices(u8 *output, const u8 *input, ++ int matrices, int row_length) ++{ ++ int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value; ++ ++ matrix_size = row_length * row_length; ++ for (i = 0; i < matrices; i++) { ++ row = 0; ++ x_offset = 0; ++ matrix_offset = i * matrix_size; ++ for (j = 0; j < matrix_size; j++) { ++ y_offset = j - (row * row_length); ++ rot_index = y_offset * row_length + x_offset; ++ new_value = *(input + i * matrix_size + j); ++ output[matrix_offset + rot_index] = new_value; ++ if ((j + 1) % row_length == 0) { ++ row += 1; ++ x_offset += 1; ++ } ++ } ++ } ++} ++ ++static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) ++{ ++ int offset = 0; ++ ++ transpose_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4); ++ offset = 6 * 16 * sizeof(u8); ++ transpose_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8); ++ offset += 6 * 64 * sizeof(u8); ++ transpose_and_flatten_matrices(output + offset, ++ (const u8 *)input->scaling_list_16x16, 6, 8); ++ offset += 6 * 64 * sizeof(u8); ++ /* Add a 128 byte padding with 0s between the two 32x32 matrices */ ++ transpose_and_flatten_matrices(output + offset, ++ (const u8 *)input->scaling_list_32x32, 1, 8); ++ offset += 64 * sizeof(u8); ++ memset(output + offset, 0, 128); ++ offset += 128 * sizeof(u8); ++ transpose_and_flatten_matrices(output + offset, ++ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)), ++ 1, 8); ++ offset += 64 * sizeof(u8); ++ memset(output + offset, 0, 128); ++} ++ ++/* ++ * Required layout: ++ * A = scaling_list_dc_coef_16x16 ++ * B = scaling_list_dc_coef_32x32 ++ * 0 = Padding ++ * ++ * A, A, A, A, A, A, B, 0, 0, B, 0, 0 ++ */ ++static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input) ++{ ++ u8 list_32x32[6] = {0}; ++ ++ memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8)); ++ list_32x32[0] = input->scaling_list_dc_coef_32x32[0]; ++ list_32x32[3] = input->scaling_list_dc_coef_32x32[1]; ++ memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8)); ++} ++ ++static void translate_scaling_list(struct scaling_factor *output, ++ const struct v4l2_ctrl_hevc_scaling_matrix *input) ++{ ++ assemble_scalingfactor0(output->scalingfactor0, input); ++ memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96); ++ assemble_scalingdc(output->scalingdc, input); ++ memset(output->reserved, 0, 4 * sizeof(u8)); ++} ++ ++static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix; ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu; ++ u8 *dst; ++ ++ if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling, ++ sizeof(struct v4l2_ctrl_hevc_scaling_matrix))) ++ return; ++ ++ dst = tbl->scaling_list; ++ translate_scaling_list((struct scaling_factor *)dst, scaling); ++ ++ memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling, ++ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)); ++} ++ ++static struct vb2_buffer * ++get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, ++ unsigned int dpb_idx) ++{ ++ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; ++ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q; ++ struct vb2_buffer *buf = NULL; ++ ++ if (dpb_idx < decode_params->num_active_dpb_entries) ++ buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp); ++ ++ /* ++ * If a DPB entry is unused or invalid, the address of current destination ++ * buffer is returned. ++ */ ++ if (!buf) ++ return &run->base.bufs.dst->vb2_buf; ++ ++ return buf; ++} ++ ++static void config_registers(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params; ++ const struct v4l2_ctrl_hevc_sps *sps = run->sps; ++ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0]; ++ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb; ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma; ++ const struct v4l2_pix_format_mplane *dst_fmt; ++ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src; ++ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst; ++ const struct v4l2_format *f; ++ dma_addr_t rlc_addr; ++ dma_addr_t refer_addr; ++ u32 rlc_len; ++ u32 hor_virstride; ++ u32 ver_virstride; ++ u32 y_virstride; ++ u32 yuv_virstride = 0; ++ u32 offset; ++ dma_addr_t dst_addr; ++ u32 reg, i; ++ ++ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL); ++ ++ f = &ctx->decoded_fmt; ++ dst_fmt = &f->fmt.pix_mp; ++ hor_virstride = dst_fmt->plane_fmt[0].bytesperline; ++ ver_virstride = dst_fmt->height; ++ y_virstride = hor_virstride * ver_virstride; ++ ++ if (sps->chroma_format_idc == 0) ++ yuv_virstride = y_virstride; ++ else if (sps->chroma_format_idc == 1) ++ yuv_virstride = y_virstride + y_virstride / 2; ++ else if (sps->chroma_format_idc == 2) ++ yuv_virstride = 2 * y_virstride; ++ ++ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) | ++ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) | ++ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR); ++ ++ /* config rlc base address */ ++ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); ++ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE); ++ ++ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0); ++ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN); ++ ++ /* config cabac table */ ++ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table); ++ writel_relaxed(priv_start_addr + offset, ++ rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE); ++ ++ /* config output base address */ ++ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); ++ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE); ++ ++ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE); ++ ++ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE); ++ ++ /* config ref pic address */ ++ for (i = 0; i < 15; i++) { ++ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i); ++ ++ if (i < 4 && decode_params->num_active_dpb_entries) { ++ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0); ++ reg = (reg >> (i * 4)) & 0xf; ++ } else { ++ reg = 0; ++ } ++ ++ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0); ++ writel_relaxed(refer_addr | reg, ++ rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i)); ++ ++ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ? ++ dpb[i].pic_order_cnt_val : 0); ++ writel_relaxed(reg, ++ rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i)); ++ } ++ ++ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0); ++ ++ /* config hw pps address */ ++ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set); ++ writel_relaxed(priv_start_addr + offset, ++ rkvdec->regs + RKVDEC_REG_PPS_BASE); ++ ++ /* config hw rps address */ ++ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps); ++ writel_relaxed(priv_start_addr + offset, ++ rkvdec->regs + RKVDEC_REG_RPS_BASE); ++ ++ reg = RKVDEC_AXI_DDR_RDATA(0); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA); ++ ++ reg = RKVDEC_AXI_DDR_WDATA(0); ++ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA); ++} ++ ++#define RKVDEC_HEVC_MAX_DEPTH_IN_BYTES 2 ++ ++static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, ++ struct v4l2_format *f) ++{ ++ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp; ++ ++ fmt->num_planes = 1; ++ if (!fmt->plane_fmt[0].sizeimage) ++ fmt->plane_fmt[0].sizeimage = fmt->width * fmt->height * ++ RKVDEC_HEVC_MAX_DEPTH_IN_BYTES; ++ return 0; ++} ++ ++static enum rkvdec_image_fmt rkvdec_hevc_get_image_fmt(struct rkvdec_ctx *ctx, ++ struct v4l2_ctrl *ctrl) ++{ ++ const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; ++ ++ if (ctrl->id != V4L2_CID_STATELESS_HEVC_SPS) ++ return RKVDEC_IMG_FMT_ANY; ++ ++ if (sps->bit_depth_luma_minus8 == 0) { ++ if (sps->chroma_format_idc == 2) ++ return RKVDEC_IMG_FMT_422_8BIT; ++ else ++ return RKVDEC_IMG_FMT_420_8BIT; ++ } else if (sps->bit_depth_luma_minus8 == 2) { ++ if (sps->chroma_format_idc == 2) ++ return RKVDEC_IMG_FMT_422_10BIT; ++ else ++ return RKVDEC_IMG_FMT_420_10BIT; ++ } ++ ++ return RKVDEC_IMG_FMT_ANY; ++} ++ ++static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, ++ const struct v4l2_ctrl_hevc_sps *sps) ++{ ++ if (sps->chroma_format_idc > 1) ++ /* Only 4:0:0 and 4:2:0 are supported */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) ++ /* Luma and chroma bit depth mismatch */ ++ return -EINVAL; ++ if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) ++ /* Only 8-bit and 10-bit is supported */ ++ return -EINVAL; ++ ++ if (sps->pic_width_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.width || ++ sps->pic_height_in_luma_samples > ctx->coded_fmt.fmt.pix_mp.height) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static int rkvdec_hevc_start(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ struct rkvdec_hevc_priv_tbl *priv_tbl; ++ struct rkvdec_hevc_ctx *hevc_ctx; ++ ++ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL); ++ if (!hevc_ctx) ++ return -ENOMEM; ++ ++ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl), ++ &hevc_ctx->priv_tbl.dma, GFP_KERNEL); ++ if (!priv_tbl) { ++ kfree(hevc_ctx); ++ return -ENOMEM; ++ } ++ ++ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl); ++ hevc_ctx->priv_tbl.cpu = priv_tbl; ++ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, ++ sizeof(rkvdec_hevc_cabac_table)); ++ ++ ctx->priv = hevc_ctx; ++ return 0; ++} ++ ++static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv; ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ ++ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size, ++ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma); ++ kfree(hevc_ctx); ++} ++ ++static void rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, ++ struct rkvdec_hevc_run *run) ++{ ++ struct v4l2_ctrl *ctrl; ++ ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_DECODE_PARAMS); ++ run->decode_params = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SLICE_PARAMS); ++ run->slices_params = ctrl ? ctrl->p_cur.p : NULL; ++ run->num_slices = ctrl ? ctrl->new_elems : 0; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SPS); ++ run->sps = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_PPS); ++ run->pps = ctrl ? ctrl->p_cur.p : NULL; ++ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, ++ V4L2_CID_STATELESS_HEVC_SCALING_MATRIX); ++ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL; ++ ++ rkvdec_run_preamble(ctx, &run->base); ++} ++ ++static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ struct rkvdec_hevc_run run; ++ u32 reg; ++ ++ rkvdec_hevc_run_preamble(ctx, &run); ++ ++ assemble_hw_scaling_list(ctx, &run); ++ assemble_hw_pps(ctx, &run); ++ assemble_sw_rps(ctx, &run); ++ config_registers(ctx, &run); ++ ++ rkvdec_run_postamble(ctx, &run.base); ++ ++ schedule_delayed_work(&rkvdec->watchdog_work, msecs_to_jiffies(2000)); ++ ++ writel(0, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); ++ writel(0, rkvdec->regs + RKVDEC_REG_H264_ERR_E); ++ writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); ++ writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); ++ ++ /* Start decoding! */ ++ reg = (run.pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ? ++ 0 : RKVDEC_WR_DDR_ALIGN_EN; ++ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | ++ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E | reg, ++ rkvdec->regs + RKVDEC_REG_INTERRUPT); ++ ++ return 0; ++} ++ ++static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl) ++{ ++ if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) ++ return rkvdec_hevc_validate_sps(ctx, ctrl->p_new.p_hevc_sps); ++ ++ return 0; ++} ++ ++const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = { ++ .adjust_fmt = rkvdec_hevc_adjust_fmt, ++ .start = rkvdec_hevc_start, ++ .stop = rkvdec_hevc_stop, ++ .run = rkvdec_hevc_run, ++ .try_ctrl = rkvdec_hevc_try_ctrl, ++ .get_image_fmt = rkvdec_hevc_get_image_fmt, ++}; +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h +index 15b9bee92016..540c8bdf24e4 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h +@@ -28,6 +28,7 @@ + #define RKVDEC_SOFTRST_EN_P BIT(20) + #define RKVDEC_FORCE_SOFTRESET_VALID BIT(21) + #define RKVDEC_SOFTRESET_RDY BIT(22) ++#define RKVDEC_WR_DDR_ALIGN_EN BIT(23) + + #define RKVDEC_REG_SYSCTRL 0x008 + #define RKVDEC_IN_ENDIAN BIT(0) +@@ -43,6 +44,7 @@ + #define RKVDEC_RLC_MODE BIT(11) + #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12) + #define RKVDEC_MODE(x) (((x) & 0x03) << 20) ++#define RKVDEC_MODE_HEVC 0 + #define RKVDEC_MODE_H264 1 + #define RKVDEC_MODE_VP9 2 + #define RKVDEC_RPS_MODE BIT(24) +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +index d3b31f461194..f26e4a1150c9 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +@@ -158,6 +158,67 @@ static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = { + .s_ctrl = rkvdec_s_ctrl, + }; + ++static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = { ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS, ++ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY, ++ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS, ++ .cfg.dims = { 600 }, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS, ++ .cfg.ops = &rkvdec_ctrl_ops, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, ++ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, ++ }, ++ { ++ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE, ++ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, ++ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, ++ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, ++ }, ++ { ++ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, ++ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, ++ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, ++ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, ++ }, ++ { ++ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, ++ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, ++ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, ++ }, ++}; ++ ++static const struct rkvdec_ctrls rkvdec_hevc_ctrls = { ++ .ctrls = rkvdec_hevc_ctrl_descs, ++ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs), ++}; ++ ++static const struct rkvdec_decoded_fmt_desc rkvdec_hevc_decoded_fmts[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_NV12, ++ .image_fmt = RKVDEC_IMG_FMT_420_8BIT, ++ }, ++ { ++ .fourcc = V4L2_PIX_FMT_NV15, ++ .image_fmt = RKVDEC_IMG_FMT_420_10BIT, ++ }, ++}; ++ + static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = { + { + .cfg.id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, +@@ -252,6 +313,21 @@ static const struct rkvdec_decoded_fmt_desc rkvdec_vp9_decoded_fmts[] = { + }; + + static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { ++ { ++ .fourcc = V4L2_PIX_FMT_HEVC_SLICE, ++ .frmsize = { ++ .min_width = 64, ++ .max_width = 4096, ++ .step_width = 64, ++ .min_height = 64, ++ .max_height = 2304, ++ .step_height = 16, ++ }, ++ .ctrls = &rkvdec_hevc_ctrls, ++ .ops = &rkvdec_hevc_fmt_ops, ++ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), ++ .decoded_fmts = rkvdec_hevc_decoded_fmts, ++ }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .frmsize = { +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h +index f6e8bf38add3..c062c5c5bbb2 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h +@@ -139,6 +139,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); + void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); + + extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; ++extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; + extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; + + #endif /* RKVDEC_H_ */ +-- +2.34.1 + +From bc218b36dcc4a6472ac65ee1db817cc64cbf790f Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Fri, 5 Sep 2025 16:19:20 +0000 +Subject: [PATCH 045/108] FROMLIST(v3): media: rkvdec: Add variants support + +Different versions of the Rockchip VDEC IP exists and one way they can +differ is what decoding formats are supported. + +Add a variant implementation in order to support flagging different +capabilities. + +Signed-off-by: Alex Bee +Reviewed-by: Nicolas Dufresne +Signed-off-by: Jonas Karlman +--- + .../media/platform/rockchip/rkvdec/rkvdec.c | 22 ++++++++++++++++++- + .../media/platform/rockchip/rkvdec/rkvdec.h | 11 ++++++++++ + 2 files changed, 32 insertions(+), 1 deletion(-) + +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +index f26e4a1150c9..9406805675d8 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -327,6 +328,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .ops = &rkvdec_hevc_fmt_ops, + .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts), + .decoded_fmts = rkvdec_hevc_decoded_fmts, ++ .capability = RKVDEC_CAPABILITY_HEVC, + }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, +@@ -343,6 +345,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .num_decoded_fmts = ARRAY_SIZE(rkvdec_h264_decoded_fmts), + .decoded_fmts = rkvdec_h264_decoded_fmts, + .subsystem_flags = VB2_V4L2_FL_SUPPORTS_M2M_HOLD_CAPTURE_BUF, ++ .capability = RKVDEC_CAPABILITY_H264, + }, + { + .fourcc = V4L2_PIX_FMT_VP9_FRAME, +@@ -358,6 +361,7 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + .ops = &rkvdec_vp9_fmt_ops, + .num_decoded_fmts = ARRAY_SIZE(rkvdec_vp9_decoded_fmts), + .decoded_fmts = rkvdec_vp9_decoded_fmts, ++ .capability = RKVDEC_CAPABILITY_VP9, + } + }; + +@@ -1186,8 +1190,18 @@ static void rkvdec_watchdog_func(struct work_struct *work) + } + } + ++static const struct rkvdec_variant rk3399_rkvdec_variant = { ++ .num_regs = 78, ++ .capabilities = RKVDEC_CAPABILITY_HEVC | ++ RKVDEC_CAPABILITY_H264 | ++ RKVDEC_CAPABILITY_VP9, ++}; ++ + static const struct of_device_id of_rkvdec_match[] = { +- { .compatible = "rockchip,rk3399-vdec" }, ++ { ++ .compatible = "rockchip,rk3399-vdec", ++ .data = &rk3399_rkvdec_variant, ++ }, + { /* sentinel */ } + }; + MODULE_DEVICE_TABLE(of, of_rkvdec_match); +@@ -1198,16 +1212,22 @@ static const char * const rkvdec_clk_names[] = { + + static int rkvdec_probe(struct platform_device *pdev) + { ++ const struct rkvdec_variant *variant; + struct rkvdec_dev *rkvdec; + unsigned int i; + int ret, irq; + ++ variant = of_device_get_match_data(&pdev->dev); ++ if (!variant) ++ return -EINVAL; ++ + rkvdec = devm_kzalloc(&pdev->dev, sizeof(*rkvdec), GFP_KERNEL); + if (!rkvdec) + return -ENOMEM; + + platform_set_drvdata(pdev, rkvdec); + rkvdec->dev = &pdev->dev; ++ rkvdec->variant = variant; + mutex_init(&rkvdec->vdev_lock); + INIT_DELAYED_WORK(&rkvdec->watchdog_work, rkvdec_watchdog_func); + +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h +index c062c5c5bbb2..d2e17eb2cca6 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h +@@ -22,6 +22,10 @@ + #include + #include + ++#define RKVDEC_CAPABILITY_HEVC BIT(0) ++#define RKVDEC_CAPABILITY_H264 BIT(1) ++#define RKVDEC_CAPABILITY_VP9 BIT(2) ++ + struct rkvdec_ctx; + + struct rkvdec_ctrl_desc { +@@ -63,6 +67,11 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) + base.vb.vb2_buf); + } + ++struct rkvdec_variant { ++ unsigned int num_regs; ++ unsigned int capabilities; ++}; ++ + struct rkvdec_coded_fmt_ops { + int (*adjust_fmt)(struct rkvdec_ctx *ctx, + struct v4l2_format *f); +@@ -98,6 +107,7 @@ struct rkvdec_coded_fmt_desc { + unsigned int num_decoded_fmts; + const struct rkvdec_decoded_fmt_desc *decoded_fmts; + u32 subsystem_flags; ++ unsigned int capability; + }; + + struct rkvdec_dev { +@@ -111,6 +121,7 @@ struct rkvdec_dev { + struct mutex vdev_lock; /* serializes ioctls */ + struct delayed_work watchdog_work; + struct iommu_domain *empty_domain; ++ const struct rkvdec_variant *variant; + }; + + struct rkvdec_ctx { +-- +2.34.1 + +From 61705b83d47a950b13a03b712581f1f31d410bac Mon Sep 17 00:00:00 2001 +From: Jonas Karlman +Date: Sun, 10 Aug 2025 21:24:33 +0000 +Subject: [PATCH 046/108] FROMLIST(v3): media: rkvdec: Implement capability + filtering + +Add filtering of coded formats and controls depending on a variant +capabilities. + +Signed-off-by: Alex Bee +Signed-off-by: Jonas Karlman +--- + .../media/platform/rockchip/rkvdec/rkvdec.c | 67 ++++++++++++++----- + 1 file changed, 49 insertions(+), 18 deletions(-) + +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +index 9406805675d8..adbc277a3112 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +@@ -365,13 +365,36 @@ static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = { + } + }; + ++static bool rkvdec_is_capable(struct rkvdec_ctx *ctx, unsigned int capability) ++{ ++ return (ctx->dev->variant->capabilities & capability) == capability; ++} ++ + static const struct rkvdec_coded_fmt_desc * +-rkvdec_find_coded_fmt_desc(u32 fourcc) ++rkvdec_enum_coded_fmt_desc(struct rkvdec_ctx *ctx, int index) + { ++ int fmt_idx = -1; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { +- if (rkvdec_coded_fmts[i].fourcc == fourcc) ++ if (!rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) ++ continue; ++ fmt_idx++; ++ if (index == fmt_idx) ++ return &rkvdec_coded_fmts[i]; ++ } ++ ++ return NULL; ++} ++ ++static const struct rkvdec_coded_fmt_desc * ++rkvdec_find_coded_fmt_desc(struct rkvdec_ctx *ctx, u32 fourcc) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { ++ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability) && ++ rkvdec_coded_fmts[i].fourcc == fourcc) + return &rkvdec_coded_fmts[i]; + } + +@@ -382,7 +405,7 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) + { + struct v4l2_format *f = &ctx->coded_fmt; + +- ctx->coded_fmt_desc = &rkvdec_coded_fmts[0]; ++ ctx->coded_fmt_desc = rkvdec_enum_coded_fmt_desc(ctx, 0); + rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); + + f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; +@@ -396,21 +419,22 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx) + static int rkvdec_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *fsize) + { +- const struct rkvdec_coded_fmt_desc *fmt; ++ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); ++ const struct rkvdec_coded_fmt_desc *desc; + + if (fsize->index != 0) + return -EINVAL; + +- fmt = rkvdec_find_coded_fmt_desc(fsize->pixel_format); +- if (!fmt) ++ desc = rkvdec_find_coded_fmt_desc(ctx, fsize->pixel_format); ++ if (!desc) + return -EINVAL; + + fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS; + fsize->stepwise.min_width = 1; +- fsize->stepwise.max_width = fmt->frmsize.max_width; ++ fsize->stepwise.max_width = desc->frmsize.max_width; + fsize->stepwise.step_width = 1; + fsize->stepwise.min_height = 1; +- fsize->stepwise.max_height = fmt->frmsize.max_height; ++ fsize->stepwise.max_height = desc->frmsize.max_height; + fsize->stepwise.step_height = 1; + + return 0; +@@ -470,10 +494,10 @@ static int rkvdec_try_output_fmt(struct file *file, void *priv, + struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); + const struct rkvdec_coded_fmt_desc *desc; + +- desc = rkvdec_find_coded_fmt_desc(pix_mp->pixelformat); ++ desc = rkvdec_find_coded_fmt_desc(ctx, pix_mp->pixelformat); + if (!desc) { +- pix_mp->pixelformat = rkvdec_coded_fmts[0].fourcc; +- desc = &rkvdec_coded_fmts[0]; ++ desc = rkvdec_enum_coded_fmt_desc(ctx, 0); ++ pix_mp->pixelformat = desc->fourcc; + } + + v4l2_apply_frmsize_constraints(&pix_mp->width, +@@ -550,7 +574,7 @@ static int rkvdec_s_output_fmt(struct file *file, void *priv, + if (ret) + return ret; + +- desc = rkvdec_find_coded_fmt_desc(f->fmt.pix_mp.pixelformat); ++ desc = rkvdec_find_coded_fmt_desc(ctx, f->fmt.pix_mp.pixelformat); + if (!desc) + return -EINVAL; + ctx->coded_fmt_desc = desc; +@@ -602,10 +626,14 @@ static int rkvdec_g_capture_fmt(struct file *file, void *priv, + static int rkvdec_enum_output_fmt(struct file *file, void *priv, + struct v4l2_fmtdesc *f) + { +- if (f->index >= ARRAY_SIZE(rkvdec_coded_fmts)) ++ struct rkvdec_ctx *ctx = fh_to_rkvdec_ctx(priv); ++ const struct rkvdec_coded_fmt_desc *desc; ++ ++ desc = rkvdec_enum_coded_fmt_desc(ctx, f->index); ++ if (!desc) + return -EINVAL; + +- f->pixelformat = rkvdec_coded_fmts[f->index].fourcc; ++ f->pixelformat = desc->fourcc; + return 0; + } + +@@ -969,14 +997,17 @@ static int rkvdec_init_ctrls(struct rkvdec_ctx *ctx) + int ret; + + for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) +- nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; ++ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) ++ nctrls += rkvdec_coded_fmts[i].ctrls->num_ctrls; + + v4l2_ctrl_handler_init(&ctx->ctrl_hdl, nctrls); + + for (i = 0; i < ARRAY_SIZE(rkvdec_coded_fmts); i++) { +- ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); +- if (ret) +- goto err_free_handler; ++ if (rkvdec_is_capable(ctx, rkvdec_coded_fmts[i].capability)) { ++ ret = rkvdec_add_ctrls(ctx, rkvdec_coded_fmts[i].ctrls); ++ if (ret) ++ goto err_free_handler; ++ } + } + + ret = v4l2_ctrl_handler_setup(&ctx->ctrl_hdl); +-- +2.34.1 + +From d0a24ad239a154b3e967f8c48856fbe7a1491def Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 10 Aug 2025 21:24:34 +0000 +Subject: [PATCH 047/108] FROMLIST(v3): media: rkvdec: Add RK3288 variant + +Add a RK3288 variant, a version of the Rockchip VDEC IP that only +support HEVC decoding. + +Signed-off-by: Alex Bee +Signed-off-by: Jonas Karlman +--- + drivers/media/platform/rockchip/rkvdec/rkvdec.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +index adbc277a3112..918ac6d38950 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +@@ -1221,6 +1221,11 @@ static void rkvdec_watchdog_func(struct work_struct *work) + } + } + ++static const struct rkvdec_variant rk3288_rkvdec_variant = { ++ .num_regs = 68, ++ .capabilities = RKVDEC_CAPABILITY_HEVC, ++}; ++ + static const struct rkvdec_variant rk3399_rkvdec_variant = { + .num_regs = 78, + .capabilities = RKVDEC_CAPABILITY_HEVC | +@@ -1229,6 +1234,10 @@ static const struct rkvdec_variant rk3399_rkvdec_variant = { + }; + + static const struct of_device_id of_rkvdec_match[] = { ++ { ++ .compatible = "rockchip,rk3288-vdec", ++ .data = &rk3288_rkvdec_variant, ++ }, + { + .compatible = "rockchip,rk3399-vdec", + .data = &rk3399_rkvdec_variant, +-- +2.34.1 + +From 887446046b0547e1d76d0eef142a785a339d22b6 Mon Sep 17 00:00:00 2001 +From: Alex Bee +Date: Sun, 10 Aug 2025 21:24:35 +0000 +Subject: [PATCH 048/108] FROMLIST(v3): media: rkvdec: Disable QoS for HEVC and + VP9 on RK3328 + +The RK3328 VDEC has a HW quirk that require QoS to be disabled when HEVC +or VP9 is decoded, otherwise the decoded picture may become corrupted. + +Add a RK3328 variant with a quirk flag to disable QoS when before +decoding is started. + +Signed-off-by: Alex Bee +Signed-off-by: Jonas Karlman +--- + .../platform/rockchip/rkvdec/rkvdec-hevc.c | 3 +++ + .../platform/rockchip/rkvdec/rkvdec-regs.h | 2 ++ + .../platform/rockchip/rkvdec/rkvdec-vp9.c | 4 ++++ + .../media/platform/rockchip/rkvdec/rkvdec.c | 24 +++++++++++++++++++ + .../media/platform/rockchip/rkvdec/rkvdec.h | 5 ++++ + 5 files changed, 38 insertions(+) + +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c +index 9b5cf70188db..fc7e6a260b0a 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c +@@ -789,6 +789,9 @@ static int rkvdec_hevc_run(struct rkvdec_ctx *ctx) + writel(1, rkvdec->regs + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND); + writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); + ++ if (rkvdec->variant->quirks & RKVDEC_QUIRK_DISABLE_QOS) ++ rkvdec_quirks_disable_qos(ctx); ++ + /* Start decoding! */ + reg = (run.pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) ? + 0 : RKVDEC_WR_DDR_ALIGN_EN; +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h +index 540c8bdf24e4..c627b6b6f53a 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-regs.h +@@ -219,6 +219,8 @@ + #define RKVDEC_REG_H264_ERR_E 0x134 + #define RKVDEC_H264_ERR_EN_HIGHBITS(x) ((x) & 0x3fffffff) + ++#define RKVDEC_REG_QOS_CTRL 0x18C ++ + #define RKVDEC_REG_PREF_LUMA_CACHE_COMMAND 0x410 + #define RKVDEC_REG_PREF_CHR_CACHE_COMMAND 0x450 + +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c +index 0e7e16f20eeb..b4bf01e839ef 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vp9.c +@@ -824,6 +824,10 @@ static int rkvdec_vp9_run(struct rkvdec_ctx *ctx) + writel(1, rkvdec->regs + RKVDEC_REG_PREF_CHR_CACHE_COMMAND); + + writel(0xe, rkvdec->regs + RKVDEC_REG_STRMD_ERR_EN); ++ ++ if (rkvdec->variant->quirks & RKVDEC_QUIRK_DISABLE_QOS) ++ rkvdec_quirks_disable_qos(ctx); ++ + /* Start decoding! */ + writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E | + RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E, +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.c b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +index 918ac6d38950..ef0ad92600f3 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.c ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.c +@@ -902,6 +902,18 @@ void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run) + v4l2_ctrl_request_complete(src_req, &ctx->ctrl_hdl); + } + ++void rkvdec_quirks_disable_qos(struct rkvdec_ctx *ctx) ++{ ++ struct rkvdec_dev *rkvdec = ctx->dev; ++ u32 reg; ++ ++ /* Set undocumented swreg_block_gating_e field */ ++ reg = readl(rkvdec->regs + RKVDEC_REG_QOS_CTRL); ++ reg &= GENMASK(31, 16); ++ reg |= 0xEFFF; ++ writel(reg, rkvdec->regs + RKVDEC_REG_QOS_CTRL); ++} ++ + static void rkvdec_device_run(void *priv) + { + struct rkvdec_ctx *ctx = priv; +@@ -1226,6 +1238,14 @@ static const struct rkvdec_variant rk3288_rkvdec_variant = { + .capabilities = RKVDEC_CAPABILITY_HEVC, + }; + ++static const struct rkvdec_variant rk3328_rkvdec_variant = { ++ .num_regs = 109, ++ .capabilities = RKVDEC_CAPABILITY_HEVC | ++ RKVDEC_CAPABILITY_H264 | ++ RKVDEC_CAPABILITY_VP9, ++ .quirks = RKVDEC_QUIRK_DISABLE_QOS, ++}; ++ + static const struct rkvdec_variant rk3399_rkvdec_variant = { + .num_regs = 78, + .capabilities = RKVDEC_CAPABILITY_HEVC | +@@ -1238,6 +1258,10 @@ static const struct of_device_id of_rkvdec_match[] = { + .compatible = "rockchip,rk3288-vdec", + .data = &rk3288_rkvdec_variant, + }, ++ { ++ .compatible = "rockchip,rk3328-vdec", ++ .data = &rk3328_rkvdec_variant, ++ }, + { + .compatible = "rockchip,rk3399-vdec", + .data = &rk3399_rkvdec_variant, +diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec.h b/drivers/media/platform/rockchip/rkvdec/rkvdec.h +index d2e17eb2cca6..892d2380b59d 100644 +--- a/drivers/media/platform/rockchip/rkvdec/rkvdec.h ++++ b/drivers/media/platform/rockchip/rkvdec/rkvdec.h +@@ -26,6 +26,8 @@ + #define RKVDEC_CAPABILITY_H264 BIT(1) + #define RKVDEC_CAPABILITY_VP9 BIT(2) + ++#define RKVDEC_QUIRK_DISABLE_QOS BIT(0) ++ + struct rkvdec_ctx; + + struct rkvdec_ctrl_desc { +@@ -70,6 +72,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf) + struct rkvdec_variant { + unsigned int num_regs; + unsigned int capabilities; ++ unsigned int quirks; + }; + + struct rkvdec_coded_fmt_ops { +@@ -149,6 +152,8 @@ struct rkvdec_aux_buf { + void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); + void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run); + ++void rkvdec_quirks_disable_qos(struct rkvdec_ctx *ctx); ++ + extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops; + extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops; + extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops; +-- +2.34.1 + diff --git a/patch/kernel/archive/rockchip64-6.16/net-ethernet-realtek-add-r8169-LED-configuration-from-OF.patch b/patch/kernel/archive/rockchip64-6.17/net-ethernet-realtek-add-r8169-LED-configuration-from-OF.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/net-ethernet-realtek-add-r8169-LED-configuration-from-OF.patch rename to patch/kernel/archive/rockchip64-6.17/net-ethernet-realtek-add-r8169-LED-configuration-from-OF.patch diff --git a/patch/kernel/archive/rockchip64-6.16/net-phy-realtek-add-rtl8211x-LED-configuration-from-OF.patch b/patch/kernel/archive/rockchip64-6.17/net-phy-realtek-add-rtl8211x-LED-configuration-from-OF.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/net-phy-realtek-add-rtl8211x-LED-configuration-from-OF.patch rename to patch/kernel/archive/rockchip64-6.17/net-phy-realtek-add-rtl8211x-LED-configuration-from-OF.patch diff --git a/patch/kernel/archive/rockchip64-6.16/net-usb-r8152-add-LED-configuration-from-OF.patch b/patch/kernel/archive/rockchip64-6.17/net-usb-r8152-add-LED-configuration-from-OF.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/net-usb-r8152-add-LED-configuration-from-OF.patch rename to patch/kernel/archive/rockchip64-6.17/net-usb-r8152-add-LED-configuration-from-OF.patch diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/Makefile b/patch/kernel/archive/rockchip64-6.17/overlay/Makefile similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/Makefile rename to patch/kernel/archive/rockchip64-6.17/overlay/Makefile diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/README.rockchip-overlays b/patch/kernel/archive/rockchip64-6.17/overlay/README.rockchip-overlays similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/README.rockchip-overlays rename to patch/kernel/archive/rockchip64-6.17/overlay/README.rockchip-overlays diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/hinlink-h88k-240x135-lcd.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/hinlink-h88k-240x135-lcd.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/hinlink-h88k-240x135-lcd.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/hinlink-h88k-240x135-lcd.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rk3308-b@1.3ghz.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rk3308-b@1.3ghz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rk3308-b@1.3ghz.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rk3308-b@1.3ghz.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rk3308-bs.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rk3308-bs.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rk3308-bs.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rk3308-bs.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rk3308-bs@1.3ghz.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rk3308-bs@1.3ghz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rk3308-bs@1.3ghz.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rk3308-bs@1.3ghz.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rk3308-otg-host.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rk3308-otg-host.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rk3308-otg-host.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rk3308-otg-host.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rk3308-pcm5102a.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rk3308-pcm5102a.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rk3308-pcm5102a.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rk3308-pcm5102a.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rk3308-s0-ext-antenna.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rk3308-s0-ext-antenna.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rk3308-s0-ext-antenna.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rk3308-s0-ext-antenna.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-fixup.scr-cmd b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-fixup.scr-cmd similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-fixup.scr-cmd rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-fixup.scr-cmd diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-cpu-hs.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-cpu-hs.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-cpu-hs.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-cpu-hs.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-emmc-ddr.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-emmc-ddr.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-emmc-ddr.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-emmc-ddr.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-emmc-hs200.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-emmc-hs200.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-emmc-hs200.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-emmc-hs200.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-led-conf1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-led-conf1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-led-conf1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-led-conf1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-led-conf2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-led-conf2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-led-conf2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-led-conf2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-led-conf3.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-led-conf3.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-led-conf3.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-led-conf3.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-led-conf4.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-led-conf4.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-led-conf4.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-led-conf4.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-led-conf5.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-led-conf5.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-led-conf5.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-led-conf5.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-wlan-ap6330.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-wlan-ap6330.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-wlan-ap6330.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-wlan-ap6330.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-wlan-ap6334.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-wlan-ap6334.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-wlan-ap6334.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-wlan-ap6334.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-wlan-ext.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-wlan-ext.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3318-box-wlan-ext.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3318-box-wlan-ext.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-i2c0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-i2c0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-i2c0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-i2c0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-i2s1-pcm5102.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-i2s1-pcm5102.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-i2s1-pcm5102.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-i2s1-pcm5102.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-mksklipad50-enable-rtc-end1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-mksklipad50-enable-rtc-end1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-mksklipad50-enable-rtc-end1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-mksklipad50-enable-rtc-end1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-mksklipad50-enable-v4l2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-mksklipad50-enable-v4l2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-mksklipad50-enable-v4l2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-mksklipad50-enable-v4l2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-mkspi-disable-lcd-spi.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-mkspi-disable-lcd-spi.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-mkspi-disable-lcd-spi.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-mkspi-disable-lcd-spi.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-opp-1.4ghz.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-opp-1.4ghz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-opp-1.4ghz.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-opp-1.4ghz.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-opp-1.5ghz.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-opp-1.5ghz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-opp-1.5ghz.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-opp-1.5ghz.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-spi-spidev.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-spi-spidev.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-spi-spidev.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-spi-spidev.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-uart1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-uart1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3328-uart1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3328-uart1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-dwc3-0-host.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-dwc3-0-host.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-dwc3-0-host.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-dwc3-0-host.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-i2c7.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-i2c7.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-i2c7.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-i2c7.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-i2c8.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-i2c8.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-i2c8.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-i2c8.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-opp-2ghz.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-opp-2ghz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-opp-2ghz.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-opp-2ghz.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-pcie-gen2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-pcie-gen2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-pcie-gen2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-pcie-gen2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-spi-jedec-nor.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-spi-jedec-nor.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-spi-jedec-nor.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-spi-jedec-nor.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-spi-spidev.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-spi-spidev.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-spi-spidev.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-spi-spidev.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-uart4.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-uart4.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-uart4.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-uart4.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-w1-gpio.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-w1-gpio.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3399-w1-gpio.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3399-w1-gpio.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3566-sata2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3566-sata2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3566-sata2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3566-sata2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-i2c0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-i2c0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-i2c0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-i2c0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-i2c1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-i2c1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-i2c1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-i2c1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-pwm1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-pwm1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-pwm1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-pwm1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-pwm2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-pwm2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-pwm2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-pwm2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-pwm9.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-pwm9.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-pwm9.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-pwm9.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-spi-spidev.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-spi-spidev.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-spi-spidev.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-spi-spidev.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-uart0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-uart0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-uart0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-uart0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-uart1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-uart1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-hk-uart1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-hk-uart1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-rock-3a-disable-uart2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-rock-3a-disable-uart2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3568-rock-3a-disable-uart2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3568-rock-3a-disable-uart2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-fanctrl.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-fanctrl.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-fanctrl.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-fanctrl.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-hdmirx.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-hdmirx.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-hdmirx.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-hdmirx.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-i2c8-m2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-i2c8-m2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-i2c8-m2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-i2c8-m2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-nanopi-m6-display-dsi1-yx35.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-nanopi-m6-display-dsi1-yx35.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-nanopi-m6-display-dsi1-yx35.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-nanopi-m6-display-dsi1-yx35.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-nanopi-m6-spi-nor-flash.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-nanopi-m6-spi-nor-flash.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-nanopi-m6-spi-nor-flash.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-nanopi-m6-spi-nor-flash.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm0-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm0-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm0-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm0-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm0-m1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm0-m1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm0-m1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm0-m1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm0-m2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm0-m2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm0-m2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm0-m2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm1-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm1-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm1-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm1-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm1-m1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm1-m1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm1-m1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm1-m1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm1-m2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm1-m2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm1-m2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm1-m2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm10-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm10-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm10-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm10-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm11-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm11-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm11-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm11-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm11-m1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm11-m1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm11-m1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm11-m1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm12-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm12-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm12-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm12-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm13-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm13-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm13-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm13-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm13-m2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm13-m2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm13-m2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm13-m2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm14-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm14-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm14-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm14-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm14-m1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm14-m1.dtso similarity index 100% rename from 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b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm15-m1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm15-m1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm15-m1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm15-m2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm15-m2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm15-m2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm15-m2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm15-m3.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm15-m3.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm15-m3.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm15-m3.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm2-m1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm2-m1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm2-m1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm2-m1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm3-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm3-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm3-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm3-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm3-m1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm3-m1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm3-m1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm3-m1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm3-m2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm3-m2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm3-m2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm3-m2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm3-m3.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm3-m3.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm3-m3.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm3-m3.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm5-m2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm5-m2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm5-m2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm5-m2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm6-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm6-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm6-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm6-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm6-m2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm6-m2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm6-m2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm6-m2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm7-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm7-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm7-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm7-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm7-m3.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm7-m3.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm7-m3.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm7-m3.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm8-m0.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm8-m0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-pwm8-m0.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-pwm8-m0.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-rkvenc-overlay.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-rkvenc-overlay.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-rkvenc-overlay.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-rkvenc-overlay.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-sata1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-sata1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-sata1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-sata1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-sata2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-sata2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-sata2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-sata2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart1-m1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart1-m1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart1-m1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart1-m1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart3-m1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart3-m1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart3-m1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart3-m1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart4-m2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart4-m2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart4-m2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart4-m2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart6-m1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart6-m1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart6-m1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart6-m1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart7-m2.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart7-m2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart7-m2.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart7-m2.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart8-m1.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart8-m1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rk3588-uart8-m1.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rk3588-uart8-m1.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rockpi4cplus-usb-host.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rockpi4cplus-usb-host.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rockpi4cplus-usb-host.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rockpi4cplus-usb-host.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rockpro64-lcd.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rockpro64-lcd.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-rockpro64-lcd.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-rockpro64-lcd.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-sakurapi-rk3308b-pcm5102a.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-sakurapi-rk3308b-pcm5102a.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-sakurapi-rk3308b-pcm5102a.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-sakurapi-rk3308b-pcm5102a.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/overlay/rockchip-sakurapi-rk3308b-ws2812.dtso b/patch/kernel/archive/rockchip64-6.17/overlay/rockchip-sakurapi-rk3308b-ws2812.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/overlay/rockchip-sakurapi-rk3308b-ws2812.dtso rename to patch/kernel/archive/rockchip64-6.17/overlay/rockchip-sakurapi-rk3308b-ws2812.dtso diff --git a/patch/kernel/archive/rockchip64-6.16/regulator-add-fan53200-driver.patch b/patch/kernel/archive/rockchip64-6.17/regulator-add-fan53200-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/regulator-add-fan53200-driver.patch rename to patch/kernel/archive/rockchip64-6.17/regulator-add-fan53200-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-0001-pinctrl-slew-mux.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-0001-pinctrl-slew-mux.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-0001-pinctrl-slew-mux.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-0001-pinctrl-slew-mux.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-acodec-vendor-driver.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-acodec-vendor-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-acodec-vendor-driver.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-acodec-vendor-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-add-gmac-alias.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-add-gmac-alias.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-add-gmac-alias.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-add-gmac-alias.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-add-missing-i2s-controllers.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-add-missing-i2s-controllers.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-add-missing-i2s-controllers.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-add-missing-i2s-controllers.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-add-tsadc-driver.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-add-tsadc-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-add-tsadc-driver.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-add-tsadc-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-dts-legacy-cryptov2.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-dts-legacy-cryptov2.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-dts-legacy-cryptov2.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-dts-legacy-cryptov2.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-dts-thermal-zones.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-dts-thermal-zones.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-dts-thermal-zones.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-dts-thermal-zones.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-fix-10mbit-ethernet.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-fix-10mbit-ethernet.patch similarity index 81% rename from patch/kernel/archive/rockchip64-6.16/rk3308-fix-10mbit-ethernet.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-fix-10mbit-ethernet.patch index 846cc55a5f52..cfdeb5627a21 100644 --- a/patch/kernel/archive/rockchip64-6.16/rk3308-fix-10mbit-ethernet.patch +++ b/patch/kernel/archive/rockchip64-6.17/rk3308-fix-10mbit-ethernet.patch @@ -30,10 +30,10 @@ Last-Update: 2025-09-06 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -index 700858f..5a19f70 100644 +index f6687c2f30f6..45dab3b5680f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c -@@ -500,8 +500,8 @@ static const struct rk_gmac_ops rk3288_ops = { +@@ -503,8 +503,8 @@ static const struct rk_gmac_ops rk3288_ops = { /* RK3308_GRF_MAC_CON0 */ #define RK3308_GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(2) | GRF_CLR_BIT(3) | \ GRF_BIT(4)) @@ -44,18 +44,21 @@ index 700858f..5a19f70 100644 #define RK3308_GMAC_SPEED_10M GRF_CLR_BIT(0) #define RK3308_GMAC_SPEED_100M GRF_BIT(0) -@@ -524,6 +524,11 @@ static void rk3308_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) - } else { - dev_err(dev, "unknown speed value for RMII! speed=%d", speed); - } -+ int ret = clk_set_rate(bsp_priv->clks[RK_CLK_MAC_SPEED].clk, 250000*speed); +@@ -522,6 +522,13 @@ static const struct rk_reg_speed_data rk3308_reg_speed_data = { + static int rk3308_set_speed(struct rk_priv_data *bsp_priv, + phy_interface_t interface, int speed) + { ++ ++ int ret = clk_set_rate(bsp_priv->clks[RK_CLK_MAC_SPEED].clk, 250000 * speed); + if (ret) { -+ dev_err(dev, "%s: clk_set_rate for %dMbps returned: %d\n", ++ dev_err(bsp_priv->dev, "%s: clk_set_rate for %dMbps returned: %d\n", + __func__, speed, ret); + } ++ + return rk_set_reg_speed(bsp_priv, &rk3308_reg_speed_data, + RK3308_GRF_MAC_CON0, interface, speed); } - - static const struct rk_gmac_ops rk3308_ops = { + -- 2.39.5 diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-fix-uart-dma.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-fix-uart-dma.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-fix-uart-dma.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-fix-uart-dma.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-i2s-default-rate.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-i2s-default-rate.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-i2s-default-rate.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-i2s-default-rate.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-internal-rgb-lcdc.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-internal-rgb-lcdc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-internal-rgb-lcdc.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-internal-rgb-lcdc.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3308-vop-output.patch b/patch/kernel/archive/rockchip64-6.17/rk3308-vop-output.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3308-vop-output.patch rename to patch/kernel/archive/rockchip64-6.17/rk3308-vop-output.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3328-add-dmc-driver.patch b/patch/kernel/archive/rockchip64-6.17/rk3328-add-dmc-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3328-add-dmc-driver.patch rename to patch/kernel/archive/rockchip64-6.17/rk3328-add-dmc-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3328-add-rga-node.patch b/patch/kernel/archive/rockchip64-6.17/rk3328-add-rga-node.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3328-add-rga-node.patch rename to patch/kernel/archive/rockchip64-6.17/rk3328-add-rga-node.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3328-dtsi-mali-opp-table.patch b/patch/kernel/archive/rockchip64-6.17/rk3328-dtsi-mali-opp-table.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3328-dtsi-mali-opp-table.patch rename to patch/kernel/archive/rockchip64-6.17/rk3328-dtsi-mali-opp-table.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3328-dtsi-spdif.patch b/patch/kernel/archive/rockchip64-6.17/rk3328-dtsi-spdif.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3328-dtsi-spdif.patch rename to patch/kernel/archive/rockchip64-6.17/rk3328-dtsi-spdif.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3328-dtsi-usb3-reset-properties.patch b/patch/kernel/archive/rockchip64-6.17/rk3328-dtsi-usb3-reset-properties.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3328-dtsi-usb3-reset-properties.patch rename to patch/kernel/archive/rockchip64-6.17/rk3328-dtsi-usb3-reset-properties.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3328-gpu-cooling-target.patch b/patch/kernel/archive/rockchip64-6.17/rk3328-gpu-cooling-target.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3328-gpu-cooling-target.patch rename to patch/kernel/archive/rockchip64-6.17/rk3328-gpu-cooling-target.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3328-inno-usb3phy-driver.patch b/patch/kernel/archive/rockchip64-6.17/rk3328-inno-usb3phy-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3328-inno-usb3phy-driver.patch rename to patch/kernel/archive/rockchip64-6.17/rk3328-inno-usb3phy-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3328-roc-cc-add-missing-nodes.patch b/patch/kernel/archive/rockchip64-6.17/rk3328-roc-cc-add-missing-nodes.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3328-roc-cc-add-missing-nodes.patch rename to patch/kernel/archive/rockchip64-6.17/rk3328-roc-cc-add-missing-nodes.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-add-sclk-i2sout-src-clock.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-add-sclk-i2sout-src-clock.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-add-sclk-i2sout-src-clock.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-add-sclk-i2sout-src-clock.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-dmc-polling-rate.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-dmc-polling-rate.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-dmc-polling-rate.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-dmc-polling-rate.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-fix-pci-phy.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-fix-pci-phy.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-fix-pci-phy.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-fix-pci-phy.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-fix-usb-phy.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-fix-usb-phy.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-fix-usb-phy.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-fix-usb-phy.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch similarity index 97% rename from patch/kernel/archive/rockchip64-6.16/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch index 1ddc0b9d1b24..b98656907025 100644 --- a/patch/kernel/archive/rockchip64-6.16/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch +++ b/patch/kernel/archive/rockchip64-6.17/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch @@ -36,18 +36,18 @@ index 111111111111..222222222222 100644 pd_ignore_unused diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c -index 111111111111..222222222222 100644 +index 6a6da404c664..c7d586556eeb 100644 --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c -@@ -32,10 +32,14 @@ +@@ -24,10 +24,14 @@ + #include + #include #include - #include - #include +#include - + #include "../pci.h" #include "pcie-rockchip.h" - + +static int bus_scan_delay = -1; +module_param_named(bus_scan_delay, bus_scan_delay, int, S_IRUGO); + @@ -121,4 +121,3 @@ index 111111111111..222222222222 100644 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg) -- Armbian - diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-sd-drive-level-8ma.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-sd-drive-level-8ma.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-sd-drive-level-8ma.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-sd-drive-level-8ma.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-sd-pwr-pinctrl.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-sd-pwr-pinctrl.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-sd-pwr-pinctrl.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-sd-pwr-pinctrl.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-unlock-temperature.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-unlock-temperature.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-unlock-temperature.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-unlock-temperature.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-Revert-usb-typec-tcpm-unregister-existing-source-cap.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-Revert-usb-typec-tcpm-unregister-existing-source-cap.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-Revert-usb-typec-tcpm-unregister-existing-source-cap.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-Revert-usb-typec-tcpm-unregister-existing-source-cap.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-notify-typec-dp-hpd-state-through-extcon.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-notify-typec-dp-hpd-state-through-extcon.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-notify-typec-dp-hpd-state-through-extcon.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-notify-typec-dp-hpd-state-through-extcon.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-phy-phy-rockchip-inno-usb2-Decrease-delay-between-po.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-phy-phy-rockchip-inno-usb2-Decrease-delay-between-po.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-phy-phy-rockchip-inno-usb2-Decrease-delay-between-po.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-phy-phy-rockchip-inno-usb2-Decrease-delay-between-po.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-phy-rockchip-inno-usb2-More-robust-charger-detection.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-phy-rockchip-inno-usb2-More-robust-charger-detection.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-phy-rockchip-inno-usb2-More-robust-charger-detection.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-phy-rockchip-inno-usb2-More-robust-charger-detection.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-phy-rockchip-naneng-Add-fallback-for-old-DTs.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-phy-rockchip-naneng-Add-fallback-for-old-DTs.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-phy-rockchip-naneng-Add-fallback-for-old-DTs.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-phy-rockchip-naneng-Add-fallback-for-old-DTs.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-dwc3-Extend-reset-quirk-support-to-include-role-.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-dwc3-Extend-reset-quirk-support-to-include-role-.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-dwc3-Extend-reset-quirk-support-to-include-role-.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-dwc3-Extend-reset-quirk-support-to-include-role-.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-dwc3-Track-the-power-state-of-usb3_generic_phy.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-dwc3-Track-the-power-state-of-usb3_generic_phy.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-dwc3-Track-the-power-state-of-usb3_generic_phy.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-dwc3-Track-the-power-state-of-usb3_generic_phy.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPT.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPT.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPT.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPT.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-typec-tcpm-Fix-PD-devices-capabilities-registrat.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-typec-tcpm-Fix-PD-devices-capabilities-registrat.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-typec-tcpm-Fix-PD-devices-capabilities-registrat.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-typec-tcpm-Fix-PD-devices-capabilities-registrat.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-typec-tcpm-Unregister-altmodes-before-registerin.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-typec-tcpm-Unregister-altmodes-before-registerin.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-typec-tcpm-Unregister-altmodes-before-registerin.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-typec-tcpm-Unregister-altmodes-before-registerin.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-typec-typec-extcon-Add-typec-extcon-bridge-drive.patch b/patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-typec-typec-extcon-Add-typec-extcon-bridge-drive.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3399-usbc-usb-typec-typec-extcon-Add-typec-extcon-bridge-drive.patch rename to patch/kernel/archive/rockchip64-6.17/rk3399-usbc-usb-typec-typec-extcon-Add-typec-extcon-bridge-drive.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk356x-add-rkvdec2-support.patch b/patch/kernel/archive/rockchip64-6.17/rk356x-add-rkvdec2-support.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk356x-add-rkvdec2-support.patch rename to patch/kernel/archive/rockchip64-6.17/rk356x-add-rkvdec2-support.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3576-0004-arch-arm64-dts-rockchip-remove-overclocked-CPU-OPP-t.patch b/patch/kernel/archive/rockchip64-6.17/rk3576-0004-arch-arm64-dts-rockchip-remove-overclocked-CPU-OPP-t.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3576-0004-arch-arm64-dts-rockchip-remove-overclocked-CPU-OPP-t.patch rename to patch/kernel/archive/rockchip64-6.17/rk3576-0004-arch-arm64-dts-rockchip-remove-overclocked-CPU-OPP-t.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-0010-fix-clk-divisions.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-0010-fix-clk-divisions.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-0010-fix-clk-divisions.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-0010-fix-clk-divisions.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-0011-irqchip-fix-its-timeout-issue.patch.bak b/patch/kernel/archive/rockchip64-6.17/rk3588-0011-irqchip-fix-its-timeout-issue.patch.bak similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-0011-irqchip-fix-its-timeout-issue.patch.bak rename to patch/kernel/archive/rockchip64-6.17/rk3588-0011-irqchip-fix-its-timeout-issue.patch.bak diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-0025-add-missing-op-nodes.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-0025-add-missing-op-nodes.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-0025-add-missing-op-nodes.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-0025-add-missing-op-nodes.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200.patch similarity index 59% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200.patch index ecea653e6e36..e82c84e48ae3 100644 --- a/patch/kernel/archive/rockchip64-6.16/rk3588-1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200.patch +++ b/patch/kernel/archive/rockchip64-6.17/rk3588-1010-arm64-dts-rock-5b-Slow-down-emmc-to-hs200.patch @@ -7,11 +7,11 @@ Subject: arm64: dts: rock-5b: Slow down emmc freq and add tsadc node arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi | 1 + 1 file changed, 1 insertion(+) -diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi -index 111111111111..222222222222 100644 ---- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi -+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi -@@ -497,6 +497,7 @@ &sdhci { +diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +index 973d39a7e0e0..0510d63f1b3a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +@@ -434,6 +434,7 @@ &sdhci { no-sdio; no-sd; non-removable; diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1040-board-khadas-edge2-add-nodes.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1040-board-khadas-edge2-add-nodes.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1040-board-khadas-edge2-add-nodes.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1040-board-khadas-edge2-add-nodes.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1041-board-khadas-edge2-mcu.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1041-board-khadas-edge2-mcu.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1041-board-khadas-edge2-mcu.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1041-board-khadas-edge2-mcu.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1051-board-nanopc-t6-fan-support.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1051-board-nanopc-t6-fan-support.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1051-board-nanopc-t6-fan-support.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1051-board-nanopc-t6-fan-support.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1052-board-nanopc-t6-fix-usb3-a.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1052-board-nanopc-t6-fix-usb3-a.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1052-board-nanopc-t6-fix-usb3-a.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1052-board-nanopc-t6-fix-usb3-a.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1063-arm64-dts-rockchip-Enable-automatic-fan-control-on-t.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1064-arm64-dts-rockchip-Add-missing-hym8563-clock-frequen.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1072-arm64-dts-rockchip-add-AP6275P-wifi-to-Orange-Pi-5B.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1072-arm64-dts-rockchip-add-AP6275P-wifi-to-Orange-Pi-5B.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1072-arm64-dts-rockchip-add-AP6275P-wifi-to-Orange-Pi-5B.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1072-arm64-dts-rockchip-add-AP6275P-wifi-to-Orange-Pi-5B.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1080-arm64-dts-rockchip-add-USB3-support-to-NanoPi-R6-ser.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1080-arm64-dts-rockchip-add-USB3-support-to-NanoPi-R6-ser.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1080-arm64-dts-rockchip-add-USB3-support-to-NanoPi-R6-ser.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1080-arm64-dts-rockchip-add-USB3-support-to-NanoPi-R6-ser.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1090-arm64-dts-rockchip-Enable-HDMI-receiver-on-CM3588-NAS.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1090-arm64-dts-rockchip-Enable-HDMI-receiver-on-CM3588-NAS.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1090-arm64-dts-rockchip-Enable-HDMI-receiver-on-CM3588-NAS.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1090-arm64-dts-rockchip-Enable-HDMI-receiver-on-CM3588-NAS.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1091-arm64-dts-rockchip-Enable-HDMI-receiver-on-NanoPC-T6.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1091-arm64-dts-rockchip-Enable-HDMI-receiver-on-NanoPC-T6.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1091-arm64-dts-rockchip-Enable-HDMI-receiver-on-NanoPC-T6.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1091-arm64-dts-rockchip-Enable-HDMI-receiver-on-NanoPC-T6.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1100-arm64-dts-rockchip-opi5-max-add-2nd-hdmi.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1100-arm64-dts-rockchip-opi5-max-add-2nd-hdmi.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1100-arm64-dts-rockchip-opi5-max-add-2nd-hdmi.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1100-arm64-dts-rockchip-opi5-max-add-2nd-hdmi.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk3588-1101-arm64-dts-rockchip-opi5-max-add-hdmi-sound.patch b/patch/kernel/archive/rockchip64-6.17/rk3588-1101-arm64-dts-rockchip-opi5-max-add-hdmi-sound.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk3588-1101-arm64-dts-rockchip-opi5-max-add-hdmi-sound.patch rename to patch/kernel/archive/rockchip64-6.17/rk3588-1101-arm64-dts-rockchip-opi5-max-add-hdmi-sound.patch diff --git a/patch/kernel/archive/rockchip64-6.16/rk35xx-montjoie-crypto-v2-rk35xx.patch b/patch/kernel/archive/rockchip64-6.17/rk35xx-montjoie-crypto-v2-rk35xx.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/rk35xx-montjoie-crypto-v2-rk35xx.patch rename to patch/kernel/archive/rockchip64-6.17/rk35xx-montjoie-crypto-v2-rk35xx.patch diff --git a/patch/kernel/archive/rockchip64-6.16/temporary-workaround-dma-reset.patch b/patch/kernel/archive/rockchip64-6.17/temporary-workaround-dma-reset.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/temporary-workaround-dma-reset.patch rename to patch/kernel/archive/rockchip64-6.17/temporary-workaround-dma-reset.patch diff --git a/patch/kernel/archive/rockchip64-6.16/wifi-4003-add-bcm43342-chip.patch b/patch/kernel/archive/rockchip64-6.17/wifi-4003-add-bcm43342-chip.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.16/wifi-4003-add-bcm43342-chip.patch rename to patch/kernel/archive/rockchip64-6.17/wifi-4003-add-bcm43342-chip.patch diff --git a/patch/misc/wireless-uwe5622/uwe5622-v6.17.patch b/patch/misc/wireless-uwe5622/uwe5622-v6.17.patch new file mode 100644 index 000000000000..934d7a6da740 --- /dev/null +++ b/patch/misc/wireless-uwe5622/uwe5622-v6.17.patch @@ -0,0 +1,13 @@ +diff --git a/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c b/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c +index 0014d0946f3c..2e5715e5b84b 100755 +--- a/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c ++++ b/drivers/net/wireless/uwe5622/unisocwifi/cfg80211.c +@@ -2039,7 +2039,7 @@ static int sprdwl_cfg80211_connect(struct wiphy *wiphy, struct net_device *ndev, + return ret; + } + +-static int sprdwl_cfg80211_set_wiphy_params(struct wiphy *wiphy, u32 changed) ++static int sprdwl_cfg80211_set_wiphy_params(struct wiphy *wiphy, int radio_idx, u32 changed) + { + struct sprdwl_priv *priv = wiphy_priv(wiphy); + u32 rts = 0, frag = 0;