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| 1 | +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | +/* |
| 3 | + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. |
| 4 | + * |
| 5 | + */ |
| 6 | + |
| 7 | +/dts-v1/; |
| 8 | + |
| 9 | +#include "rk3588-blueberry-r58-hd3.dtsi" |
| 10 | +#include "rk3588-linux.dtsi" |
| 11 | +#include "rk3588-blueberry-r58-hd3-rk628-hdmi2csi.dtsi" |
| 12 | +/ { |
| 13 | + model = "RK3588 R58-HD Board"; |
| 14 | + compatible = "rockchip,rk3588-R58-HD-v10-linux", "rockchip,rk3588"; |
| 15 | + /delete-node/ chosen; |
| 16 | + |
| 17 | + fan{ |
| 18 | + compatible = "pwm-fan"; |
| 19 | + #cooling-cells = <2>; |
| 20 | + pwms = <&pwm5 0 50000 0>; |
| 21 | + cooling-levels = <0 50 100 150 200 255>; |
| 22 | + rockchip,temp-trips = < |
| 23 | + 60000 1 |
| 24 | + 65000 2 |
| 25 | + 70000 3 |
| 26 | + 75000 4 |
| 27 | + 80000 5 |
| 28 | + >; |
| 29 | + enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; |
| 30 | + pinctrl-names = "default"; |
| 31 | + pinctrl-0 = <&fan_enable_gpio>; |
| 32 | + }; |
| 33 | + |
| 34 | +//软件保留 |
| 35 | + backlight_mipi0: backlight_mipi0 { |
| 36 | + compatible = "pwm-backlight"; |
| 37 | + pwms = <&pwm9 0 25000 0>; |
| 38 | + brightness-levels = < |
| 39 | + 0 20 20 21 21 22 22 23 |
| 40 | + >; |
| 41 | + default-brightness-level = <2>; |
| 42 | + }; |
| 43 | + |
| 44 | +//软件保留 |
| 45 | + backlight_mipi1: backlight_mipi1 { |
| 46 | + compatible = "pwm-backlight"; |
| 47 | + pwms = <&pwm15 0 25000 0>; |
| 48 | + brightness-levels = < |
| 49 | + 0 20 20 21 21 22 22 23 |
| 50 | + >; |
| 51 | + default-brightness-level = <2>; |
| 52 | + }; |
| 53 | + |
| 54 | +}; |
| 55 | + |
| 56 | +&can1 { |
| 57 | + pinctrl-names = "default"; |
| 58 | + pinctrl-0 = <&can1m1_pins>; |
| 59 | + status = "okay"; |
| 60 | +}; |
| 61 | + |
| 62 | +//风扇 |
| 63 | +&pwm4 { |
| 64 | + pinctrl-0 = <&pwm4m0_pins>; |
| 65 | + status = "disabled"; |
| 66 | +}; |
| 67 | + |
| 68 | +&pwm5 { |
| 69 | + pinctrl-0 = <&pwm5m1_pins>; |
| 70 | + status = "okay"; |
| 71 | +}; |
| 72 | + |
| 73 | + |
| 74 | +//mipi0 |
| 75 | +&pwm9 { |
| 76 | + pinctrl-0 = <&pwm9m0_pins>; |
| 77 | + status = "okay"; |
| 78 | +}; |
| 79 | + |
| 80 | +//mipi1 |
| 81 | +&pwm15 { |
| 82 | + pinctrl-0 = <&pwm15m2_pins>; |
| 83 | + status = "okay"; |
| 84 | +}; |
| 85 | + |
| 86 | +#if 1 |
| 87 | +&dsi0 { |
| 88 | + status = "okay"; |
| 89 | + //rockchip,lane-rate = <120>; |
| 90 | + dsi0_panel: panel@0 { |
| 91 | + status = "okay"; |
| 92 | + compatible = "simple-panel-dsi"; |
| 93 | + reg = <0>; |
| 94 | + backlight = <&backlight_mipi0>; |
| 95 | + //power-supply = <&vcc3v3_mipi_lcd_power>; |
| 96 | + reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; |
| 97 | + //enable-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; |
| 98 | + reset-delay-ms = <100>; |
| 99 | + enable-delay-ms = <10>; |
| 100 | + init-delay-ms = <100>; |
| 101 | + prepare-delay-ms = <100>; |
| 102 | + unprepare-delay-ms = <10>; |
| 103 | + disable-delay-ms = <60>; |
| 104 | + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | |
| 105 | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; |
| 106 | + dsi,format = <MIPI_DSI_FMT_RGB888>; |
| 107 | + dsi,lanes = <4>; |
| 108 | + panel-init-sequence = [ |
| 109 | + 05 78 01 11 |
| 110 | + 05 78 01 29 |
| 111 | + ]; |
| 112 | + |
| 113 | + panel-exit-sequence = [ |
| 114 | + 05 00 01 28 |
| 115 | + 05 00 01 10 |
| 116 | + ]; |
| 117 | + |
| 118 | + display-timings { |
| 119 | + native-mode = <&timing0>; |
| 120 | + timing0: timing0 { |
| 121 | + clock-frequency = <148500000>; |
| 122 | + hactive = <1920>; |
| 123 | + vactive = <1080>; |
| 124 | + hback-porch = <148>; |
| 125 | + hfront-porch = <88>; |
| 126 | + hsync-len = <44>; |
| 127 | + vback-porch = <36>; |
| 128 | + vfront-porch = <4>; |
| 129 | + vsync-len = <5>; |
| 130 | + hsync-active = <0>; |
| 131 | + vsync-active = <0>; |
| 132 | + de-active = <0>; |
| 133 | + pixelclk-active = <0>; |
| 134 | + }; |
| 135 | + }; |
| 136 | + |
| 137 | + ports { |
| 138 | + #address-cells = <1>; |
| 139 | + #size-cells = <0>; |
| 140 | + |
| 141 | + port@0 { |
| 142 | + reg = <0>; |
| 143 | + panel_in_dsi0: endpoint { |
| 144 | + remote-endpoint = <&dsi0_out_panel>; |
| 145 | + }; |
| 146 | + }; |
| 147 | + }; |
| 148 | + }; |
| 149 | + |
| 150 | + ports { |
| 151 | + #address-cells = <1>; |
| 152 | + #size-cells = <0>; |
| 153 | + |
| 154 | + port@1 { |
| 155 | + reg = <1>; |
| 156 | + dsi0_out_panel: endpoint { |
| 157 | + remote-endpoint = <&panel_in_dsi0>; |
| 158 | + }; |
| 159 | + }; |
| 160 | + }; |
| 161 | + |
| 162 | +}; |
| 163 | + |
| 164 | +&mipi_dcphy0 { |
| 165 | + status = "okay"; |
| 166 | +}; |
| 167 | + |
| 168 | +&dsi0_in_vp2 { |
| 169 | + status = "okay"; |
| 170 | +}; |
| 171 | + |
| 172 | +&dsi0_in_vp3 { |
| 173 | + status = "disabled"; |
| 174 | +}; |
| 175 | + |
| 176 | +&route_dsi0 { |
| 177 | + status = "disabled"; |
| 178 | + connect = <&vp2_out_dsi0>; |
| 179 | +}; |
| 180 | + |
| 181 | +#endif |
| 182 | + |
| 183 | +#if 1 |
| 184 | +&dsi1 { |
| 185 | + status = "okay"; |
| 186 | + //rockchip,lane-rate = <120>; |
| 187 | + dsi1_panel: panel@1 { |
| 188 | + status = "okay"; |
| 189 | + compatible = "simple-panel-dsi"; |
| 190 | + reg = <0>; |
| 191 | + backlight = <&backlight_mipi1>; |
| 192 | + //power-supply = <&vcc3v3_mipi_lcd_power>; |
| 193 | + reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; |
| 194 | + //enable-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; |
| 195 | + reset-delay-ms = <100>; |
| 196 | + enable-delay-ms = <10>; |
| 197 | + init-delay-ms = <100>; |
| 198 | + prepare-delay-ms = <100>; |
| 199 | + unprepare-delay-ms = <10>; |
| 200 | + disable-delay-ms = <60>; |
| 201 | + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | |
| 202 | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET)>; |
| 203 | + dsi,format = <MIPI_DSI_FMT_RGB888>; |
| 204 | + dsi,lanes = <4>; |
| 205 | + panel-init-sequence = [ |
| 206 | + 05 78 01 11 |
| 207 | + 05 78 01 29 |
| 208 | + ]; |
| 209 | + |
| 210 | + panel-exit-sequence = [ |
| 211 | + 05 00 01 28 |
| 212 | + 05 00 01 10 |
| 213 | + ]; |
| 214 | + |
| 215 | + display-timings { |
| 216 | + native-mode = <&timing1>; |
| 217 | + timing1: timing1 { |
| 218 | + clock-frequency = <148500000>; |
| 219 | + hactive = <1920>; |
| 220 | + vactive = <1080>; |
| 221 | + hback-porch = <148>; |
| 222 | + hfront-porch = <88>; |
| 223 | + hsync-len = <44>; |
| 224 | + vback-porch = <36>; |
| 225 | + vfront-porch = <4>; |
| 226 | + vsync-len = <5>; |
| 227 | + hsync-active = <0>; |
| 228 | + vsync-active = <0>; |
| 229 | + de-active = <0>; |
| 230 | + pixelclk-active = <0>; |
| 231 | + }; |
| 232 | + }; |
| 233 | + |
| 234 | + ports { |
| 235 | + #address-cells = <1>; |
| 236 | + #size-cells = <0>; |
| 237 | + |
| 238 | + port@0 { |
| 239 | + reg = <0>; |
| 240 | + panel_in_dsi1: endpoint { |
| 241 | + remote-endpoint = <&dsi0_out_panel1>; |
| 242 | + }; |
| 243 | + }; |
| 244 | + }; |
| 245 | + }; |
| 246 | + |
| 247 | + ports { |
| 248 | + #address-cells = <1>; |
| 249 | + #size-cells = <0>; |
| 250 | + |
| 251 | + port@1 { |
| 252 | + reg = <1>; |
| 253 | + dsi0_out_panel1: endpoint { |
| 254 | + remote-endpoint = <&panel_in_dsi1>; |
| 255 | + }; |
| 256 | + }; |
| 257 | + }; |
| 258 | + |
| 259 | +}; |
| 260 | + |
| 261 | +&mipi_dcphy1 { |
| 262 | + status = "okay"; |
| 263 | +}; |
| 264 | + |
| 265 | +&dsi1_in_vp3 { |
| 266 | + status = "okay"; |
| 267 | +}; |
| 268 | + |
| 269 | +&route_dsi1 { |
| 270 | + status = "disabled"; |
| 271 | + connect = <&vp3_out_dsi1>; |
| 272 | +}; |
| 273 | + |
| 274 | +#endif |
| 275 | + |
| 276 | + |
| 277 | +&pinctrl { |
| 278 | + |
| 279 | + lt9611 { |
| 280 | + lt9611_reset_gpios: lt9611reset-gpios { |
| 281 | + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; |
| 282 | + }; |
| 283 | + }; |
| 284 | + |
| 285 | + fan_enable_gpio { //v10-1 V09 GPIO0_A0 控制风扇 |
| 286 | + fan_enable_gpio: fan_enable_gpio{ |
| 287 | + rockchip,pins = |
| 288 | + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; |
| 289 | + }; |
| 290 | + }; |
| 291 | +}; |
| 292 | + |
| 293 | + |
| 294 | +&sdmmc_pwr { |
| 295 | + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; |
| 296 | +}; |
| 297 | + |
| 298 | +&vcc_sd { |
| 299 | + compatible = "regulator-fixed"; |
| 300 | + gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; |
| 301 | + pinctrl-names = "default"; |
| 302 | + pinctrl-0 = <&sdmmc_pwr>; |
| 303 | + regulator-always-on; |
| 304 | + regulator-boot-on; |
| 305 | + enable-active-high; |
| 306 | + regulator-name = "vcc_sd"; |
| 307 | + regulator-min-microvolt = <3300000>; |
| 308 | + regulator-max-microvolt = <3300000>; |
| 309 | + startup-delay-us = <100000>; |
| 310 | + vin-supply = <&vcc12v_dcin>; |
| 311 | +}; |
| 312 | + |
| 313 | + |
| 314 | +&gmac0 { |
| 315 | + snps,reset-gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; |
| 316 | +}; |
| 317 | + |
| 318 | +//v10-2 V09版本 GPIO0_C5 作为4G 唤醒口 |
| 319 | +&DP0_HPDIN_gpio{ |
| 320 | + rockchip,pins = |
| 321 | + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; |
| 322 | +}; |
| 323 | +&dp0 { |
| 324 | + pinctrl-names = "default"; |
| 325 | + pinctrl-0 = <&DP0_HPDIN_gpio>; |
| 326 | + hpd-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; |
| 327 | + split-mode; |
| 328 | + status = "okay"; |
| 329 | +}; |
| 330 | + |
| 331 | +<6911_sound { |
| 332 | + compatible; |
| 333 | + simple-audio-card,format = "i2s"; |
| 334 | + simple-audio-card,name = "rockchip,lt6911"; |
| 335 | + simple-audio-card,bitclock-master ; |
| 336 | + simple-audio-card,frame-master ; |
| 337 | + status = "disabled"; |
| 338 | + simple-audio-card,cpu { |
| 339 | + sound-dai ; |
| 340 | + }; |
| 341 | + dailink1_master: simple-audio-card,codec { |
| 342 | + sound-dai ; |
| 343 | + }; |
| 344 | +}; |
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