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[X86] combine-subo.ll - add common CHECK prefix
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‎llvm/test/CodeGen/X86/combine-subo.ll

Lines changed: 29 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
3-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
2+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE
3+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
44

55
declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
66
declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
@@ -10,15 +10,10 @@ declare {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32>, <4 x i32
1010

1111
; fold (ssub x, 0) -> x
1212
define i32 @combine_ssub_zero(i32 %a0, i32 %a1) {
13-
; SSE-LABEL: combine_ssub_zero:
14-
; SSE: # %bb.0:
15-
; SSE-NEXT: movl %edi, %eax
16-
; SSE-NEXT: retq
17-
;
18-
; AVX-LABEL: combine_ssub_zero:
19-
; AVX: # %bb.0:
20-
; AVX-NEXT: movl %edi, %eax
21-
; AVX-NEXT: retq
13+
; CHECK-LABEL: combine_ssub_zero:
14+
; CHECK: # %bb.0:
15+
; CHECK-NEXT: movl %edi, %eax
16+
; CHECK-NEXT: retq
2217
%1 = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a0, i32 zeroinitializer)
2318
%2 = extractvalue {i32, i1} %1, 0
2419
%3 = extractvalue {i32, i1} %1, 1
@@ -27,13 +22,9 @@ define i32 @combine_ssub_zero(i32 %a0, i32 %a1) {
2722
}
2823

2924
define <4 x i32> @combine_vec_ssub_zero(<4 x i32> %a0, <4 x i32> %a1) {
30-
; SSE-LABEL: combine_vec_ssub_zero:
31-
; SSE: # %bb.0:
32-
; SSE-NEXT: retq
33-
;
34-
; AVX-LABEL: combine_vec_ssub_zero:
35-
; AVX: # %bb.0:
36-
; AVX-NEXT: retq
25+
; CHECK-LABEL: combine_vec_ssub_zero:
26+
; CHECK: # %bb.0:
27+
; CHECK-NEXT: retq
3728
%1 = call {<4 x i32>, <4 x i1>} @llvm.ssub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)
3829
%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
3930
%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
@@ -43,15 +34,10 @@ define <4 x i32> @combine_vec_ssub_zero(<4 x i32> %a0, <4 x i32> %a1) {
4334

4435
; fold (usub x, 0) -> x
4536
define i32 @combine_usub_zero(i32 %a0, i32 %a1) {
46-
; SSE-LABEL: combine_usub_zero:
47-
; SSE: # %bb.0:
48-
; SSE-NEXT: movl %edi, %eax
49-
; SSE-NEXT: retq
50-
;
51-
; AVX-LABEL: combine_usub_zero:
52-
; AVX: # %bb.0:
53-
; AVX-NEXT: movl %edi, %eax
54-
; AVX-NEXT: retq
37+
; CHECK-LABEL: combine_usub_zero:
38+
; CHECK: # %bb.0:
39+
; CHECK-NEXT: movl %edi, %eax
40+
; CHECK-NEXT: retq
5541
%1 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a0, i32 zeroinitializer)
5642
%2 = extractvalue {i32, i1} %1, 0
5743
%3 = extractvalue {i32, i1} %1, 1
@@ -60,13 +46,9 @@ define i32 @combine_usub_zero(i32 %a0, i32 %a1) {
6046
}
6147

6248
define <4 x i32> @combine_vec_usub_zero(<4 x i32> %a0, <4 x i32> %a1) {
63-
; SSE-LABEL: combine_vec_usub_zero:
64-
; SSE: # %bb.0:
65-
; SSE-NEXT: retq
66-
;
67-
; AVX-LABEL: combine_vec_usub_zero:
68-
; AVX: # %bb.0:
69-
; AVX-NEXT: retq
49+
; CHECK-LABEL: combine_vec_usub_zero:
50+
; CHECK: # %bb.0:
51+
; CHECK-NEXT: retq
7052
%1 = call {<4 x i32>, <4 x i1>} @llvm.usub.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)
7153
%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
7254
%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
@@ -76,15 +58,10 @@ define <4 x i32> @combine_vec_usub_zero(<4 x i32> %a0, <4 x i32> %a1) {
7658

7759
; fold (ssub x, x) -> 0
7860
define i32 @combine_ssub_self(i32 %a0, i32 %a1) {
79-
; SSE-LABEL: combine_ssub_self:
80-
; SSE: # %bb.0:
81-
; SSE-NEXT: xorl %eax, %eax
82-
; SSE-NEXT: retq
83-
;
84-
; AVX-LABEL: combine_ssub_self:
85-
; AVX: # %bb.0:
86-
; AVX-NEXT: xorl %eax, %eax
87-
; AVX-NEXT: retq
61+
; CHECK-LABEL: combine_ssub_self:
62+
; CHECK: # %bb.0:
63+
; CHECK-NEXT: xorl %eax, %eax
64+
; CHECK-NEXT: retq
8865
%1 = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a0, i32 %a0)
8966
%2 = extractvalue {i32, i1} %1, 0
9067
%3 = extractvalue {i32, i1} %1, 1
@@ -111,15 +88,10 @@ define <4 x i32> @combine_vec_ssub_self(<4 x i32> %a0, <4 x i32> %a1) {
11188

11289
; fold (usub x, x) -> x
11390
define i32 @combine_usub_self(i32 %a0, i32 %a1) {
114-
; SSE-LABEL: combine_usub_self:
115-
; SSE: # %bb.0:
116-
; SSE-NEXT: xorl %eax, %eax
117-
; SSE-NEXT: retq
118-
;
119-
; AVX-LABEL: combine_usub_self:
120-
; AVX: # %bb.0:
121-
; AVX-NEXT: xorl %eax, %eax
122-
; AVX-NEXT: retq
91+
; CHECK-LABEL: combine_usub_self:
92+
; CHECK: # %bb.0:
93+
; CHECK-NEXT: xorl %eax, %eax
94+
; CHECK-NEXT: retq
12395
%1 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a0, i32 %a0)
12496
%2 = extractvalue {i32, i1} %1, 0
12597
%3 = extractvalue {i32, i1} %1, 1
@@ -146,17 +118,11 @@ define <4 x i32> @combine_vec_usub_self(<4 x i32> %a0, <4 x i32> %a1) {
146118

147119
; fold (usub -1, x) -> (xor x, -1) + no borrow
148120
define i32 @combine_usub_negone(i32 %a0, i32 %a1) {
149-
; SSE-LABEL: combine_usub_negone:
150-
; SSE: # %bb.0:
151-
; SSE-NEXT: movl %edi, %eax
152-
; SSE-NEXT: notl %eax
153-
; SSE-NEXT: retq
154-
;
155-
; AVX-LABEL: combine_usub_negone:
156-
; AVX: # %bb.0:
157-
; AVX-NEXT: movl %edi, %eax
158-
; AVX-NEXT: notl %eax
159-
; AVX-NEXT: retq
121+
; CHECK-LABEL: combine_usub_negone:
122+
; CHECK: # %bb.0:
123+
; CHECK-NEXT: movl %edi, %eax
124+
; CHECK-NEXT: notl %eax
125+
; CHECK-NEXT: retq
160126
%1 = call {i32, i1} @llvm.usub.with.overflow.i32(i32 -1, i32 %a0)
161127
%2 = extractvalue {i32, i1} %1, 0
162128
%3 = extractvalue {i32, i1} %1, 1

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