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#-------------------------------------------------------------------------
# XEM6010 - Xilinx constraints file and I/O pin mappings
#
# Company: Intan Technologies, LLC
# Project Name: RHD2000 Rhythm Interface
#
# Pin mappings for the Opal Kelly XEM6010 board.
#
#-------------------------------------------------------------------------
CONFIG VCCAUX = "3.3"; //Required for Spartan-6
############################################################################
## FrontPanel Host Interface pins
############################################################################
NET "hi_in<0>" LOC="Y12" | IOSTANDARD="LVCMOS33";
NET "hi_in<1>" LOC="AB20" | IOSTANDARD="LVCMOS33";
NET "hi_in<2>" LOC="AB7" | IOSTANDARD="LVCMOS33";
NET "hi_in<3>" LOC="AB8" | IOSTANDARD="LVCMOS33";
NET "hi_in<4>" LOC="AA4" | IOSTANDARD="LVCMOS33";
NET "hi_in<5>" LOC="AB4" | IOSTANDARD="LVCMOS33";
NET "hi_in<6>" LOC="Y3" | IOSTANDARD="LVCMOS33";
NET "hi_in<7>" LOC="AB3" | IOSTANDARD="LVCMOS33";
NET "hi_out<0>" LOC="Y19" | IOSTANDARD="LVCMOS33";
NET "hi_out<1>" LOC="AA8" | IOSTANDARD="LVCMOS33";
NET "hi_inout<0>" LOC="AB12" | IOSTANDARD="LVCMOS33";
NET "hi_inout<1>" LOC="AA12" | IOSTANDARD="LVCMOS33";
NET "hi_inout<2>" LOC="Y13" | IOSTANDARD="LVCMOS33";
NET "hi_inout<3>" LOC="AB18" | IOSTANDARD="LVCMOS33";
NET "hi_inout<4>" LOC="AA18" | IOSTANDARD="LVCMOS33";
NET "hi_inout<5>" LOC="V15" | IOSTANDARD="LVCMOS33";
NET "hi_inout<6>" LOC="AB2" | IOSTANDARD="LVCMOS33";
NET "hi_inout<7>" LOC="AA2" | IOSTANDARD="LVCMOS33";
NET "hi_inout<8>" LOC="Y7" | IOSTANDARD="LVCMOS33";
NET "hi_inout<9>" LOC="Y4" | IOSTANDARD="LVCMOS33";
NET "hi_inout<10>" LOC="W4" | IOSTANDARD="LVCMOS33";
NET "hi_inout<11>" LOC="AB6" | IOSTANDARD="LVCMOS33";
NET "hi_inout<12>" LOC="AA6" | IOSTANDARD="LVCMOS33";
NET "hi_inout<13>" LOC="U13" | IOSTANDARD="LVCMOS33";
NET "hi_inout<14>" LOC="U14" | IOSTANDARD="LVCMOS33";
NET "hi_inout<15>" LOC="AA20" | IOSTANDARD="LVCMOS33";
NET "hi_aa" LOC="W11" | IOSTANDARD="LVCMOS33";
NET "hi_muxsel" LOC = "AA22" | IOSTANDARD="LVCMOS33";
NET "i2c_sda" LOC = "AB9" | IOSTANDARD="LVCMOS33" | PULLUP;
NET "i2c_scl" LOC = "Y9" | IOSTANDARD="LVCMOS33" | PULLUP;
NET "hi_in<0>" TNM_NET = "okHostClk";
TIMESPEC "TS_okHostClk" = PERIOD "okHostClk" 20.83 ns HIGH 50%; # 48 MHz
NET "hi_inout[*]" TNM = "okHostINOUT_grp";
TIMEGRP "okHostINOUT_grp" OFFSET = IN 9.83 ns VALID 9.83 ns BEFORE "hi_in<0>" RISING;
TIMEGRP "okHostINOUT_grp" OFFSET = OUT 11.63 ns AFTER "hi_in<0>" RISING;
NET "hi_out<0>" OFFSET = OUT 11.93 ns AFTER "hi_in<0>" RISING;
NET "hi_out<1>" OFFSET = OUT 11.93 ns AFTER "hi_in<0>" RISING;
NET "hi_in<1>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE "hi_in<0>" RISING;
NET "hi_in<2>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE "hi_in<0>" RISING;
NET "hi_in<3>" OFFSET = IN 14.13 ns VALID 20.83 ns BEFORE "hi_in<0>" RISING;
NET "hi_in<4>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE "hi_in<0>" RISING;
NET "hi_in<5>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE "hi_in<0>" RISING;
NET "hi_in<6>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE "hi_in<0>" RISING;
NET "hi_in<7>" OFFSET = IN 13.33 ns VALID 20.83 ns BEFORE "hi_in<0>" RISING;
############################################################################
## System Clocks
############################################################################
# clk1_in = 100 MHz clock generated off-FPGA
NET "clk1_in" LOC="AB13" | IOSTANDARD="LVCMOS33";
############################################################################
## Peripherals
############################################################################
# LEDs ################################################################
NET "led[0]" LOC="Y17" | IOSTANDARD=LVCMOS33;
NET "led[1]" LOC="AB17" | IOSTANDARD=LVCMOS33;
NET "led[2]" LOC="AA14" | IOSTANDARD=LVCMOS33;
NET "led[3]" LOC="AB14" | IOSTANDARD=LVCMOS33;
NET "led[4]" LOC="AA16" | IOSTANDARD=LVCMOS33;
NET "led[5]" LOC="AB16" | IOSTANDARD=LVCMOS33;
NET "led[6]" LOC="AA10" | IOSTANDARD=LVCMOS33;
NET "led[7]" LOC="AB10" | IOSTANDARD=LVCMOS33;
############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
## Tue Nov 9 08:19:20 2010
## Generated by MIG Version 3.5 w/ edits for XEM6010
##
############################################################################
## File name : example_top.ucf
##
## Details : Constraints file
## FPGA family: spartan6
## FPGA: xc6slx45-fgg484
## Speedgrade: -2
## Design Entry: VERILOG
## Design: with Test bench
## DCM Used: Enable
## No.Of Memory Controllers: 1
##
############################################################################
############################################################################
# Extended MCB performance mode requires a different Vccint specification to
# achieve higher maximum frequencies for DDR2 and DDR3.Consult the Spartan-6
#datasheet (DS162) table 2 and 24 for more information
############################################################################
CONFIG MCB_PERFORMANCE= STANDARD;
##################################################################################
# Timing Ignore constraints for paths crossing the clock domain
##################################################################################
NET "SDRAM_FIFO_inst/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "SDRAM_FIFO_inst/c?_pll_lock" TIG;
NET "SDRAM_FIFO_inst/memc?_wrapper_inst/memc?_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/CKE_Train" TIG;
############################################################################
## Memory Controller 3
## Memory Device: DDR2_SDRAM->MT47J64M16XX-3
## Supported Part Numbers: MT47J64M16HQ-3
############################################################################
############################################################################
## Clock constraints
############################################################################
# Note: The following timing constraint always fails, but it was inherited from
# the Opal Kelly RamTest Verilog code, so we will leave it alone.
NET "SDRAM_FIFO_inst/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 10 ns HIGH 50 %;
############################################################################
############################################################################
## I/O TERMINATION
############################################################################
NET "mcb3_dram_dq[*]" IN_TERM = NONE;
NET "mcb3_dram_dqs" IN_TERM = NONE;
NET "mcb3_dram_dqs_n" IN_TERM = NONE;
NET "mcb3_dram_udqs" IN_TERM = NONE;
NET "mcb3_dram_udqs_n" IN_TERM = NONE;
############################################################################
# I/O STANDARDS
############################################################################
NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_a[*]" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL18_II;
NET "mcb3_dram_cke" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_ras_n" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_cas_n" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_we_n" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_odt" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_dm" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_udm" IOSTANDARD = SSTL18_II;
NET "mcb3_rzq" IOSTANDARD = SSTL18_II;
NET "mcb3_zio" IOSTANDARD = SSTL18_II;
NET "mcb3_dram_cs_n" IOSTANDARD = LVCMOS18;
#NET "c3_sys_clk_p" IOSTANDARD = LVDS_25; #OK
#NET "c3_sys_clk_n" IOSTANDARD = LVDS_25; #OK
#NET "c3_sys_rst_n" IOSTANDARD = LVCMOS18; #OK
############################################################################
# MCB 3
# Pin Location Constraints for Clock, Masks, Address, and Controls
############################################################################
NET "mcb3_dram_a[0]" LOC = "H2" ;
NET "mcb3_dram_a[10]" LOC = "G4" ;
NET "mcb3_dram_a[11]" LOC = "C1" ;
NET "mcb3_dram_a[12]" LOC = "D1" ;
NET "mcb3_dram_a[1]" LOC = "H1" ;
NET "mcb3_dram_a[2]" LOC = "H5" ;
NET "mcb3_dram_a[3]" LOC = "K6" ;
NET "mcb3_dram_a[4]" LOC = "F3" ;
NET "mcb3_dram_a[5]" LOC = "K3" ;
NET "mcb3_dram_a[6]" LOC = "J4" ;
NET "mcb3_dram_a[7]" LOC = "H6" ;
NET "mcb3_dram_a[8]" LOC = "E3" ;
NET "mcb3_dram_a[9]" LOC = "E1" ;
NET "mcb3_dram_ba[0]" LOC = "G3" ;
NET "mcb3_dram_ba[1]" LOC = "G1" ;
NET "mcb3_dram_ba[2]" LOC = "F1" ;
NET "mcb3_dram_cas_n" LOC = "K4" ;
NET "mcb3_dram_ck" LOC = "H4" ;
NET "mcb3_dram_ck_n" LOC = "H3" ;
NET "mcb3_dram_cke" LOC = "D2" ;
NET "mcb3_dram_dm" LOC = "L4" ;
NET "mcb3_dram_dq[0]" LOC = "N3" ;
NET "mcb3_dram_dq[10]" LOC = "R3" ;
NET "mcb3_dram_dq[11]" LOC = "R1" ;
NET "mcb3_dram_dq[12]" LOC = "U3" ;
NET "mcb3_dram_dq[13]" LOC = "U1" ;
NET "mcb3_dram_dq[14]" LOC = "V2" ;
NET "mcb3_dram_dq[15]" LOC = "V1" ;
NET "mcb3_dram_dq[1]" LOC = "N1" ;
NET "mcb3_dram_dq[2]" LOC = "M2" ;
NET "mcb3_dram_dq[3]" LOC = "M1" ;
NET "mcb3_dram_dq[4]" LOC = "J3" ;
NET "mcb3_dram_dq[5]" LOC = "J1" ;
NET "mcb3_dram_dq[6]" LOC = "K2" ;
NET "mcb3_dram_dq[7]" LOC = "K1" ;
NET "mcb3_dram_dq[8]" LOC = "P2" ;
NET "mcb3_dram_dq[9]" LOC = "P1" ;
NET "mcb3_dram_dqs" LOC = "L3" ;
NET "mcb3_dram_dqs_n" LOC = "L1" ;
NET "mcb3_dram_odt" LOC = "J6" ;
NET "mcb3_dram_ras_n" LOC = "K5" ;
#NET "c3_sys_clk_n" LOC = "Y12" ; #OK
#NET "c3_sys_clk_p" LOC = "W12" ; #OK
#NET "c3_sys_rst_n" LOC = "R11" ; #OK
NET "mcb3_dram_udm" LOC = "M3" ;
NET "mcb3_dram_udqs" LOC = "T2" ;
NET "mcb3_dram_udqs_n" LOC = "T1" ;
NET "mcb3_dram_we_n" LOC = "F2" ;
NET "mcb3_dram_cs_n" LOC = "C3" ; #OK
##################################################################################
#RZQ is required for all MCB designs. Do not move the location #
#of this pin for ES devices.For production devices, RZQ can be moved to any #
#valid package pin within the MCB bank.For designs using Calibrated Input Termination, #
#a 2R resistor should be connected between RZQand ground, where R is the desired#
#input termination value. Otherwise, RZQ should be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb3_rzq" LOC = "K7" ;
##################################################################################
#ZIO is only required for MCB designs using Calibrated Input Termination.#
#ZIO can be moved to any valid package pin (i.e. bonded IO) within the#
#MCB bank but must be left as a no-connect (NC) pin.#
##################################################################################
NET "mcb3_zio" LOC = "Y2" ;
############################################################################
## Intan Technologies RHD2000 Application-Specific Interface pins
############################################################################
# Note: Setting "DIFF_TERM = TRUE" enables an on-FPGA 100-Ohm LVDS termination
# resistor, so no off-chip resistors are required for the MISO inputs.
NET "MISO_A1_p" LOC="W20" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_A1_n" LOC="W22" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_A2_p" LOC="U19" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_A2_n" LOC="V20" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "CS_b_A_p" LOC="C5" | IOSTANDARD="LVDS_33";
NET "CS_b_A_n" LOC="A5" | IOSTANDARD="LVDS_33";
NET "SCLK_A_p" LOC="D14" | IOSTANDARD="LVDS_33";
NET "SCLK_A_n" LOC="C14" | IOSTANDARD="LVDS_33";
NET "MOSI_A_p" LOC="E16" | IOSTANDARD="LVDS_33";
NET "MOSI_A_n" LOC="D17" | IOSTANDARD="LVDS_33";
NET "MISO_B1_p" LOC="D7" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_B1_n" LOC="D8" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_B2_p" LOC="L17" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_B2_n" LOC="K18" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "CS_b_B_p" LOC="D6" | IOSTANDARD="LVDS_33";
NET "CS_b_B_n" LOC="C6" | IOSTANDARD="LVDS_33";
NET "SCLK_B_p" LOC="A3" | IOSTANDARD="LVDS_33";
NET "SCLK_B_n" LOC="A4" | IOSTANDARD="LVDS_33";
NET "MOSI_B_p" LOC="B8" | IOSTANDARD="LVDS_33";
NET "MOSI_B_n" LOC="A8" | IOSTANDARD="LVDS_33";
NET "MISO_C1_p" LOC="T19" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_C1_n" LOC="T20" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_C2_p" LOC="P17" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_C2_n" LOC="N16" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "CS_b_C_p" LOC="B10" | IOSTANDARD="LVDS_33";
NET "CS_b_C_n" LOC="A10" | IOSTANDARD="LVDS_33";
NET "SCLK_C_p" LOC="C13" | IOSTANDARD="LVDS_33";
NET "SCLK_C_n" LOC="A13" | IOSTANDARD="LVDS_33";
NET "MOSI_C_p" LOC="C15" | IOSTANDARD="LVDS_33";
NET "MOSI_C_n" LOC="A15" | IOSTANDARD="LVDS_33";
NET "MISO_D1_p" LOC="M17" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_D1_n" LOC="M18" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_D2_p" LOC="P18" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "MISO_D2_n" LOC="R19" | IOSTANDARD="LVDS_33" | DIFF_TERM = TRUE;
NET "CS_b_D_p" LOC="C17" | IOSTANDARD="LVDS_33";
NET "CS_b_D_n" LOC="A17" | IOSTANDARD="LVDS_33";
NET "SCLK_D_p" LOC="B18" | IOSTANDARD="LVDS_33";
NET "SCLK_D_n" LOC="A18" | IOSTANDARD="LVDS_33";
NET "MOSI_D_p" LOC="C11" | IOSTANDARD="LVDS_33";
NET "MOSI_D_n" LOC="A11" | IOSTANDARD="LVDS_33";
# Diagnostic pins for testing with oscilloscope
NET "CS_b" LOC="G16" | IOSTANDARD="LVCMOS33";
NET "SCLK" LOC="G17" | IOSTANDARD="LVCMOS33";
NET "MOSI_A" LOC="H19" | IOSTANDARD="LVCMOS33";
NET "MOSI_B" LOC="H18" | IOSTANDARD="LVCMOS33";
NET "MOSI_C" LOC="F16" | IOSTANDARD="LVCMOS33";
NET "MOSI_D" LOC="F17" | IOSTANDARD="LVCMOS33";
# Sample clock output
NET "sample_clk" LOC="U20" | IOSTANDARD="LVCMOS33";
# TTL inputs
NET "TTL_in[0]" LOC="P22" | IOSTANDARD=LVCMOS33;
NET "TTL_in[1]" LOC="M21" | IOSTANDARD=LVCMOS33;
NET "TTL_in[2]" LOC="M22" | IOSTANDARD=LVCMOS33;
NET "TTL_in[3]" LOC="L20" | IOSTANDARD=LVCMOS33;
NET "TTL_in[4]" LOC="L22" | IOSTANDARD=LVCMOS33;
NET "TTL_in[5]" LOC="H21" | IOSTANDARD=LVCMOS33;
NET "TTL_in[6]" LOC="H22" | IOSTANDARD=LVCMOS33;
NET "TTL_in[7]" LOC="F21" | IOSTANDARD=LVCMOS33;
NET "TTL_in[8]" LOC="F22" | IOSTANDARD=LVCMOS33;
NET "TTL_in[9]" LOC="D21" | IOSTANDARD=LVCMOS33;
NET "TTL_in[10]" LOC="D22" | IOSTANDARD=LVCMOS33;
NET "TTL_in[11]" LOC="B21" | IOSTANDARD=LVCMOS33;
NET "TTL_in[12]" LOC="B22" | IOSTANDARD=LVCMOS33;
NET "TTL_in[13]" LOC="A21" | IOSTANDARD=LVCMOS33;
NET "TTL_in[14]" LOC="J20" | IOSTANDARD=LVCMOS33;
NET "TTL_in[15]" LOC="J22" | IOSTANDARD=LVCMOS33;
# TTL outputs
NET "TTL_out[0]" LOC="U22" | IOSTANDARD=LVCMOS33;
NET "TTL_out[1]" LOC="R20" | IOSTANDARD=LVCMOS33;
NET "TTL_out[2]" LOC="R22" | IOSTANDARD=LVCMOS33;
NET "TTL_out[3]" LOC="N20" | IOSTANDARD=LVCMOS33;
NET "TTL_out[4]" LOC="N22" | IOSTANDARD=LVCMOS33;
NET "TTL_out[5]" LOC="M20" | IOSTANDARD=LVCMOS33;
NET "TTL_out[6]" LOC="L19" | IOSTANDARD=LVCMOS33;
NET "TTL_out[7]" LOC="K21" | IOSTANDARD=LVCMOS33;
NET "TTL_out[8]" LOC="K22" | IOSTANDARD=LVCMOS33;
NET "TTL_out[9]" LOC="G20" | IOSTANDARD=LVCMOS33;
NET "TTL_out[10]" LOC="G22" | IOSTANDARD=LVCMOS33;
NET "TTL_out[11]" LOC="E20" | IOSTANDARD=LVCMOS33;
NET "TTL_out[12]" LOC="E22" | IOSTANDARD=LVCMOS33;
NET "TTL_out[13]" LOC="C20" | IOSTANDARD=LVCMOS33;
NET "TTL_out[14]" LOC="C22" | IOSTANDARD=LVCMOS33;
NET "TTL_out[15]" LOC="A20" | IOSTANDARD=LVCMOS33;
# DAC control
NET "DAC_SYNC" LOC="G19" | IOSTANDARD=LVCMOS33;
NET "DAC_SCLK" LOC="F20" | IOSTANDARD=LVCMOS33;
NET "DAC_DIN_1" LOC="H20" | IOSTANDARD=LVCMOS33;
NET "DAC_DIN_2" LOC="J19" | IOSTANDARD=LVCMOS33;
NET "DAC_DIN_3" LOC="D19" | IOSTANDARD=LVCMOS33;
NET "DAC_DIN_4" LOC="D20" | IOSTANDARD=LVCMOS33;
NET "DAC_DIN_5" LOC="F18" | IOSTANDARD=LVCMOS33;
NET "DAC_DIN_6" LOC="F19" | IOSTANDARD=LVCMOS33;
NET "DAC_DIN_7" LOC="M16" | IOSTANDARD=LVCMOS33;
NET "DAC_DIN_8" LOC="L15" | IOSTANDARD=LVCMOS33;
# ADC control
NET "ADC_CS" LOC="K20" | IOSTANDARD=LVCMOS33;
NET "ADC_SCLK" LOC="K19" | IOSTANDARD=LVCMOS33;
NET "ADC_DOUT_1" LOC="K17" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "ADC_DOUT_2" LOC="K16" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "ADC_DOUT_3" LOC="J16" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "ADC_DOUT_4" LOC="V21" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "ADC_DOUT_5" LOC="V22" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "ADC_DOUT_6" LOC="T21" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "ADC_DOUT_7" LOC="T22" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "ADC_DOUT_8" LOC="P21" | IOSTANDARD=LVCMOS33 | PULLDOWN;
# Configuration bits
NET "board_mode[0]" LOC="D9" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "board_mode[1]" LOC="C8" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "board_mode[2]" LOC="D10" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "board_mode[3]" LOC="C10" | IOSTANDARD=LVCMOS33 | PULLDOWN;
# LED data out
NET "LED_OUT" LOC="B14" | IOSTANDARD=LVCMOS33;