Incorporate corrected ORC_B/BREV8 logic from llvm#148076

Author: asb

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -3768,9 +3768,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
     case RISCV::XOR:
     case RISCV::XORI:
     case RISCV::ANDN:
-    case RISCV::BREV8:
     case RISCV::CLMUL:
-    case RISCV::ORC_B:
     case RISCV::ORN:
     case RISCV::XNOR:
     case RISCV::SH1ADD:
@@ -3783,6 +3781,11 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
       if (hasAllNBitUsers(User, Bits, Depth + 1))
         break;
       return false;
+    case RISCV::BREV8:
+    case RISCV::ORC_B:
+      if (hasAllNBitUsers(User, alignDown(Bits, 8), Depth + 1))
+        break;
+      return false;
     case RISCV::CZERO_EQZ:
     case RISCV::CZERO_NEZ:
       if (Use.getOperandNo() != 0)