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[RISCV] Add additional opcodes to RISCVDAGToDAGISel::hasAllNBitUsers
This adds opcodes that are handled in the RISCVOptWInstrs version but not the SDag version.
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llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 29 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3606,11 +3606,15 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
36063606
if (Use.getOperandNo() == 1 && Bits >= Log2_32(Subtarget->getXLen()))
36073607
break;
36083608
return false;
3609-
case RISCV::SLLI:
3609+
case RISCV::SLLI: {
36103610
// SLLI only uses the lower (XLen - ShAmt) bits.
3611-
if (Bits >= Subtarget->getXLen() - User->getConstantOperandVal(1))
3611+
uint64_t ShAmt = User->getConstantOperandVal(1);
3612+
if (Bits >= Subtarget->getXLen() - ShAmt)
3613+
break;
3614+
if (hasAllNBitUsers(User, Bits + ShAmt, Depth + 1))
36123615
break;
36133616
return false;
3617+
}
36143618
case RISCV::ANDI:
36153619
if (Bits >= (unsigned)llvm::bit_width(User->getConstantOperandVal(1)))
36163620
break;
@@ -3621,20 +3625,39 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
36213625
break;
36223626
[[fallthrough]];
36233627
}
3628+
case RISCV::COPY:
3629+
case RISCV::PHI:
3630+
case RISCV::ADD:
3631+
case RISCV::ADDI:
36243632
case RISCV::AND:
3633+
case RISCV::MUL:
36253634
case RISCV::OR:
3635+
case RISCV::SUB:
36263636
case RISCV::XOR:
36273637
case RISCV::XORI:
36283638
case RISCV::ANDN:
3639+
case RISCV::BREV8:
3640+
case RISCV::CLMUL:
3641+
case RISCV::ORC_B:
36293642
case RISCV::ORN:
36303643
case RISCV::XNOR:
36313644
case RISCV::SH1ADD:
36323645
case RISCV::SH2ADD:
36333646
case RISCV::SH3ADD:
3647+
case RISCV::BSETI:
3648+
case RISCV::BCLRI:
3649+
case RISCV::BINVI:
36343650
RecCheck:
36353651
if (hasAllNBitUsers(User, Bits, Depth + 1))
36363652
break;
36373653
return false;
3654+
case RISCV::CZERO_EQZ:
3655+
case RISCV::CZERO_NEZ:
3656+
if (Use.getOperandNo() != 0)
3657+
return false;
3658+
if (hasAllNBitUsers(User, Bits, Depth + 1))
3659+
break;
3660+
return false;
36383661
case RISCV::SRLI: {
36393662
unsigned ShAmt = User->getConstantOperandVal(1);
36403663
// If we are shifting right by less than Bits, and users don't demand any
@@ -3670,6 +3693,10 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits,
36703693
if (Use.getOperandNo() == 0 && Bits >= 32)
36713694
break;
36723695
return false;
3696+
case RISCV::BEXTI:
3697+
if (User->getConstantOperandVal(1) >= Bits)
3698+
return false;
3699+
break;
36733700
case RISCV::SB:
36743701
if (Use.getOperandNo() == 0 && Bits >= 8)
36753702
break;

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