Regarding the speed grade of the LCMXO2-2000HC chip: Apart from being theoretically slower, is the -4 speed grade practically usable?

[ackyeee]

The brand-new -4 chips on the market are relatively cheaper, while the -6 chips are much more expensive. Additionally, many of the cheaper -6 chips are actually refurbished or re-marked -4 chips.

I also noticed that some ready-made boards sold in stores use -4 chips. Therefore, I would like to ask whether the difference in actual performance is significant when using -4 chips in production.

Also, thank you for this project! It looks really great.

[ataradov]

There is no difference in measurable performance. It either works or it breaks. So far, it looks like speed grade 4 works fine under regular conditions. This is not a guarantee, you may run into some marginal device that fails, although I don't think it is very likely.
The project runs at 60 MHz and in speed grade 4 device it is synthesized at 56 MHz or something like that. So, it is very close.

[ackyeee]

Thank you for your reply. When you mentioned 60M, were you referring to the 60MHz t_usb_clk_i input clock provided by the USB PHY to the FPGA?

I was just checking the FPGA manual, but I couldn't find any parameters that would restrict a 60MHz clock operation specifically for the -4 speed grade chips. I'm not very familiar with Lattice FPGAs, so the decision to choose -5 or -6 over -4 was based on which specific parameter limitation stated in the FPGA manual?

Additionally, I know that for Xilinx chips, different speed grades actually come from the same die, with differences mainly due to wafer positioning during manufacturing. I wonder if the same applies to Lattice chips.

[ataradov]

There is no generic parameter. Maximum operating speed depends on the design. You synthesize the design and the tool tells you how fast it will run in the selected device. For the speed grade 4 it said that the maximum allowed clock would be 56 MHz.

Yes, the devices are binned by speed, there is no difference in the actual design. So, on a given day, they may get a slow wafer and speed grade 4 would be really slow. But it is also possible that they need to have speed grade 4 devices, but there is no slow silicon, so they just sell fast one as 4. There is no way to tell.

[ackyeee]

Thanks for your reply. I also installed the lattice development environment today and tried to compile the code. I found the part where you said that the system timing is actually 54M. I checked the relevant content in the manual. The maximum operating frequency of the -4 chip is 269MHZ, which is far more than the 60Mhz that the code runs. So I guess the problem is not related to -4. It may be that the logic path is too long, which makes it impossible to meet the required clock frequency when the timing converges. I simply tried to add a level of always module to the combinational logic in USB_CAPTURE.V and change it to sequential logic, and then compile it again. At this time, the timing is directly increased from the original 54M to 80M. Of course, because I am not very familiar with the logic of USB_CAPTURE.V, there should be some problems in this change, but this should be an optimization direction, proving that this direction is feasible. When I have time, I will study it together. (The translation is translated into English through Google, so it may be a little difficult to understand)

[ataradov]

269 MHz is the limit of the propagation delay of a LUT. If your design consists of a single LUT, then you will get it to run this fast. More complicated logic will always be slower. This is how FPGAs work.

I'm sure you can optimize the design and make it work cleanly in speed grade 4 device. The difference in cost between 4 and 5 on Mouser at the time was $8. There is no way engineering time would be worth it and it is not a fun task to do it for free.

And currently the difference between LCMXO2-2000HC-4TG100C and LCMXO2-2000HC-5TG100C is $2. It is really not worth it trying to optimize it.