slavefifo signal pktend is used？

[DreamerYoung88]

hello Alex：
Is the pktend signal currently in use? I captured the pktend signal through a logic analyzer, but it has been in a low-level state all along. Under what conditions will the fpga send pktend(set high) in the current program?
Thanks！

[ataradov]

It is used at the beginning (restart) of a capture. It is set for 1 cycle when bit 0 in the control register is set. It is there to flush out any leftover bytes in the FIFO. The protocol here relies on perfect stream synchronization, so any data left from the previous capture will interfere with the operation.