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lines changed Original file line number Diff line number Diff line change 1+ SiFive U54 SoC clocks
2+
3+ This binding uses the common clock binding:
4+ Documentation/devicetree/bindings/clock/clock-bindings.txt
5+
6+ The U54 PRCI controller generates clocks for the U54 SoC. There is
7+ a core PLL that sets the processor frequency and PLLs for ethernet
8+ and DDR. It takes an input clock from the board, typically an oscillator
9+ or crystal.
10+
11+ Required properties:
12+ - compatible: Should be "sifive,aloeprci0"
13+ - #clock-cells: Should be <1>
14+ - reg: Specifies base physical address and size of the registers
15+ - clocks: phandles to the parent clock used as input
16+
17+ Example:
18+
19+ refclk: refclk {
20+ #clock-cells = <0>;
21+ compatible = "fixed-clock";
22+ clock-frequency = <33333333>;
23+ clock-output-names = "xtal";
24+ };
25+
26+ u54: prci@10000000 {
27+ compatible = "sifive,aloeprci0";
28+ reg = <0x0 0x10000000 0x0 0x1000>;
29+ clocks = <&refclk>;
30+ #clock-cells = <1>;
31+ };
32+
33+ tlclk: tlclk {
34+ compatible = "fixed-factor-clock";
35+ clocks = <&u54 0>; /* Core frequency */
36+ #clock-cells = <0>;
37+ clock-div = <2>;
38+ clock-mult = <1>;
39+ };
40+
41+ ethernet@10090000 {
42+ ...
43+ clocks = <&prci 1>; /* TX clock */
44+ };
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