RISCV: Disable timer interrupt in handler to fix nohz.

The timer interrupt pending bit is cleared in bbl while
reprogramming the timer. This works fine unless we are
in nohz mode. In nohz mode, the timer is not reprogrammed.
Thus, the pending bits are not cleared leading to continuous
timer interrupt firing and cpu stalls.

Disable timer interrupt in interrupt handler to ignore
the pending bit until next interrupt. Timer interrupt
is enabled again before next timer event is set.

The details of the stalls can be found in
riscvarchive#127

Other possible ideas discussion:
riscv-software-src/riscv-pk#108

Signed-off-by: Atish Patra <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>

Author: atishp04

arch/riscv/kernel/time.c

@@ -35,6 +35,12 @@ void riscv_timer_interrupt(void)
 	 */
 	struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event);
 
+	/*
+	 * There are no direct SBI calls to clear pending timer interrupt bit.
+	 * Disable timer interrupt to ignore pending interrupt until next
+	 * interrupt.
+	 */
+	csr_clear(sie, SIE_STIE);
 	evdev->event_handler(evdev);
 #endif
 }

drivers/clocksource/riscv_timer.c

@@ -38,6 +38,7 @@ static int next_event(unsigned long delta, struct clock_event_device *ce)
 	 * harts.
 	 */
 	BUG_ON(ce != this_cpu_ptr(&riscv_clock_event));
+	csr_set(sie, SIE_STIE);
 	sbi_set_timer(get_cycles64() + delta);
 	return 0;
 }