Missing cache invalidation in dma.c before DMA transfer

[frebjo]

This cache invalidation before DMA transfer ensures that during the DMA transfer the cache has no dirty lines associated to the buffer,
which could be written back to memory.

See
https://developer.arm.com/documentation/den0013/d/Memory-Ordering/Cache-coherency-implications

[frebjo]

dma.patch

PATCH.