|
166 | 166 | available_regs :: [riscv32_register()], |
167 | 167 | used_regs :: [riscv32_register()], |
168 | 168 | labels :: [{integer() | reference(), integer()}], |
169 | | - variant :: non_neg_integer(), |
170 | | - literal_pool :: [{non_neg_integer(), riscv32_register(), non_neg_integer()}] |
| 169 | + variant :: non_neg_integer() |
171 | 170 | }). |
172 | 171 |
|
173 | 172 | -type state() :: #state{}. |
@@ -275,8 +274,7 @@ new(Variant, StreamModule, Stream) -> |
275 | 274 | available_regs = ?AVAILABLE_REGS, |
276 | 275 | used_regs = [], |
277 | 276 | labels = [], |
278 | | - variant = Variant, |
279 | | - literal_pool = [] |
| 277 | + variant = Variant |
280 | 278 | }. |
281 | 279 |
|
282 | 280 | %%----------------------------------------------------------------------------- |
@@ -630,8 +628,7 @@ call_primitive_last( |
630 | 628 | State2 = set_registers_args(State1, ArgsForTailCall, 0), |
631 | 629 | tail_call_with_jit_state_registers_only(State2, Temp) |
632 | 630 | end, |
633 | | - State5 = State4#state{available_regs = ?AVAILABLE_REGS, used_regs = []}, |
634 | | - flush_literal_pool(State5). |
| 631 | + State4#state{available_regs = ?AVAILABLE_REGS, used_regs = []}. |
635 | 632 |
|
636 | 633 | %%----------------------------------------------------------------------------- |
637 | 634 | %% @doc Tail call to address in register. |
@@ -708,15 +705,13 @@ jump_to_label( |
708 | 705 | Offset = StreamModule:offset(Stream0), |
709 | 706 | {State1, CodeBlock} = branch_to_label_code(State0, Offset, Label, LabelLookupResult), |
710 | 707 | Stream1 = StreamModule:append(Stream0, CodeBlock), |
711 | | - State2 = State1#state{stream = Stream1}, |
712 | | - flush_literal_pool(State2). |
| 708 | + State1#state{stream = Stream1}. |
713 | 709 |
|
714 | 710 | jump_to_offset(#state{stream_module = StreamModule, stream = Stream0} = State, TargetOffset) -> |
715 | 711 | Offset = StreamModule:offset(Stream0), |
716 | 712 | CodeBlock = branch_to_offset_code(State, Offset, TargetOffset), |
717 | 713 | Stream1 = StreamModule:append(Stream0, CodeBlock), |
718 | | - State2 = State#state{stream = Stream1}, |
719 | | - flush_literal_pool(State2). |
| 714 | + State#state{stream = Stream1}. |
720 | 715 |
|
721 | 716 | %%----------------------------------------------------------------------------- |
722 | 717 | %% @doc Jump to address in continuation pointer register |
@@ -2531,35 +2526,6 @@ mov_immediate(#state{stream_module = StreamModule, stream = Stream0} = State, Re |
2531 | 2526 | Stream1 = StreamModule:append(Stream0, I), |
2532 | 2527 | State#state{stream = Stream1}. |
2533 | 2528 |
|
2534 | | -flush_literal_pool(#state{literal_pool = []} = State) -> |
2535 | | - State; |
2536 | | -flush_literal_pool( |
2537 | | - #state{stream_module = StreamModule, stream = Stream0, literal_pool = LP} = State |
2538 | | -) -> |
2539 | | - % Align |
2540 | | - Offset = StreamModule:offset(Stream0), |
2541 | | - Stream1 = |
2542 | | - if |
2543 | | - Offset rem 4 =:= 0 -> Stream0; |
2544 | | - true -> StreamModule:append(Stream0, <<0:16>>) |
2545 | | - end, |
2546 | | - % Lay all values and update ldr instructions |
2547 | | - Stream2 = lists:foldl( |
2548 | | - fun({LdrInstructionAddr, Reg, Val}, AccStream) -> |
2549 | | - LiteralPosition = StreamModule:offset(AccStream), |
2550 | | - LdrPC = (LdrInstructionAddr band (bnot 3)) + 4, |
2551 | | - LiteralOffset = LiteralPosition - LdrPC, |
2552 | | - LdrInstruction = jit_riscv32_asm:lw(Reg, pc, LiteralOffset), |
2553 | | - AccStream1 = StreamModule:append(AccStream, <<Val:32/little>>), |
2554 | | - StreamModule:replace( |
2555 | | - AccStream1, LdrInstructionAddr, LdrInstruction |
2556 | | - ) |
2557 | | - end, |
2558 | | - Stream1, |
2559 | | - lists:reverse(LP) |
2560 | | - ), |
2561 | | - State#state{stream = Stream2, literal_pool = []}. |
2562 | | - |
2563 | 2529 | sub(#state{stream_module = StreamModule, stream = Stream0} = State, Reg, Val) when |
2564 | 2530 | Val >= 0 andalso Val =< 255 |
2565 | 2531 | -> |
|
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