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AArch64: use macro for WORD_SIZE
Signed-off-by: Paul Guyot <[email protected]>
1 parent 2c8ce53 commit f6e35af

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‎libs/jit/src/jit_aarch64.erl‎

Lines changed: 27 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -162,19 +162,20 @@
162162

163163
% ctx->e is 0x28
164164
% ctx->x is 0x30
165+
-define(WORD_SIZE, 8).
165166
-define(CTX_REG, r0).
166167
-define(JITSTATE_REG, r1).
167168
-define(NATIVE_INTERFACE_REG, r2).
168169
-define(Y_REGS, {?CTX_REG, 16#28}).
169-
-define(X_REG(N), {?CTX_REG, 16#30 + (N * 8)}).
170+
-define(X_REG(N), {?CTX_REG, 16#30 + (N * ?WORD_SIZE)}).
170171
-define(CP, {?CTX_REG, 16#B8}).
171172
-define(FP_REGS, {?CTX_REG, 16#C0}).
172173
-define(BS, {?CTX_REG, 16#C8}).
173174
-define(BS_OFFSET, {?CTX_REG, 16#D0}).
174175
-define(JITSTATE_MODULE, {?JITSTATE_REG, 0}).
175176
-define(JITSTATE_CONTINUATION, {?JITSTATE_REG, 16#8}).
176177
-define(JITSTATE_REDUCTIONCOUNT, {?JITSTATE_REG, 16#10}).
177-
-define(PRIMITIVE(N), {?NATIVE_INTERFACE_REG, N * 8}).
178+
-define(PRIMITIVE(N), {?NATIVE_INTERFACE_REG, N * ?WORD_SIZE}).
178179
-define(MODULE_INDEX(ModuleReg), {ModuleReg, 0}).
179180

180181
% aarch64 ABI specific
@@ -207,7 +208,7 @@
207208
%% @return Word size in bytes
208209
%%-----------------------------------------------------------------------------
209210
-spec word_size() -> 4 | 8.
210-
word_size() -> 8.
211+
word_size() -> ?WORD_SIZE.
211212

212213
%%-----------------------------------------------------------------------------
213214
%% @doc Create a new backend state for provided variant, module and stream.
@@ -403,7 +404,7 @@ call_primitive(
403404
0 ->
404405
jit_aarch64_asm:ldr(?IP0_REG, {?NATIVE_INTERFACE_REG, 0});
405406
N ->
406-
jit_aarch64_asm:ldr(?IP0_REG, {?NATIVE_INTERFACE_REG, N * 8})
407+
jit_aarch64_asm:ldr(?IP0_REG, {?NATIVE_INTERFACE_REG, N * ?WORD_SIZE})
407408
end,
408409
Stream1 = StreamModule:append(Stream0, PrepCall),
409410
StateCall = State#state{stream = Stream1},
@@ -441,7 +442,7 @@ call_primitive_last(
441442
0 ->
442443
jit_aarch64_asm:ldr(Temp, {?NATIVE_INTERFACE_REG, 0});
443444
N ->
444-
jit_aarch64_asm:ldr(Temp, {?NATIVE_INTERFACE_REG, N * 8})
445+
jit_aarch64_asm:ldr(Temp, {?NATIVE_INTERFACE_REG, N * ?WORD_SIZE})
445446
end,
446447
Stream1 = StreamModule:append(Stream0, PrepCall),
447448
State1 = set_args(
@@ -999,7 +1000,7 @@ call_func_ptr(
9991000
0 ->
10001001
jit_aarch64_asm:ldr(?IP0_REG, {?NATIVE_INTERFACE_REG, 0});
10011002
N ->
1002-
jit_aarch64_asm:ldr(?IP0_REG, {?NATIVE_INTERFACE_REG, N * 8})
1003+
jit_aarch64_asm:ldr(?IP0_REG, {?NATIVE_INTERFACE_REG, N * ?WORD_SIZE})
10031004
end,
10041005
{?IP0_REG, StreamModule:append(Stream2, PrepCall)}
10051006
end,
@@ -1191,7 +1192,7 @@ set_args1({ptr, Source}, Reg) ->
11911192
set_args1({y_reg, X}, Reg) ->
11921193
[
11931194
jit_aarch64_asm:ldr(Reg, ?Y_REGS),
1194-
jit_aarch64_asm:ldr(Reg, {Reg, X * 8})
1195+
jit_aarch64_asm:ldr(Reg, {Reg, X * ?WORD_SIZE})
11951196
];
11961197
set_args1(ArgReg, Reg) when ?IS_GPR(ArgReg) ->
11971198
jit_aarch64_asm:mov(Reg, ArgReg);
@@ -1228,7 +1229,7 @@ move_to_vm_register(#state{available_regs = [Temp | _]} = State0, Src, {y_reg, Y
12281229
is_atom(Src)
12291230
->
12301231
I1 = jit_aarch64_asm:ldr(Temp, ?Y_REGS),
1231-
I2 = jit_aarch64_asm:str(Src, {Temp, Y * 8}),
1232+
I2 = jit_aarch64_asm:str(Src, {Temp, Y * ?WORD_SIZE}),
12321233
Stream1 = (State0#state.stream_module):append(State0#state.stream, <<I1/binary, I2/binary>>),
12331234
State0#state{stream = Stream1};
12341235
% Source is an integer
@@ -1259,7 +1260,7 @@ move_to_vm_register(#state{available_regs = [Temp | AT] = AR0} = State0, {ptr, R
12591260
State1#state{available_regs = AR0};
12601261
move_to_vm_register(#state{available_regs = [Temp | AT] = AR0} = State0, {y_reg, Y}, Dest) ->
12611262
I1 = jit_aarch64_asm:ldr(Temp, ?Y_REGS),
1262-
I2 = jit_aarch64_asm:ldr(Temp, {Temp, Y * 8}),
1263+
I2 = jit_aarch64_asm:ldr(Temp, {Temp, Y * ?WORD_SIZE}),
12631264
Stream1 = (State0#state.stream_module):append(State0#state.stream, <<I1/binary, I2/binary>>),
12641265
State1 = move_to_vm_register(State0#state{stream = Stream1, available_regs = AT}, Temp, Dest),
12651266
State1#state{available_regs = AR0};
@@ -1269,9 +1270,9 @@ move_to_vm_register(
12691270
{free, {ptr, Reg, 1}},
12701271
{fp_reg, F}
12711272
) ->
1272-
I1 = jit_aarch64_asm:ldr(Reg, {Reg, 8}),
1273+
I1 = jit_aarch64_asm:ldr(Reg, {Reg, ?WORD_SIZE}),
12731274
I2 = jit_aarch64_asm:ldr(Temp, ?FP_REGS),
1274-
I3 = jit_aarch64_asm:str(Reg, {Temp, F * 8}),
1275+
I3 = jit_aarch64_asm:str(Reg, {Temp, F * ?WORD_SIZE}),
12751276
Code = <<I1/binary, I2/binary, I3/binary>>,
12761277
Stream1 = StreamModule:append(Stream0, Code),
12771278
State1 = free_native_register(State0, Reg),
@@ -1298,7 +1299,7 @@ move_array_element(
12981299
Index,
12991300
{x_reg, X}
13001301
) when X < ?MAX_REG andalso is_atom(Reg) andalso is_integer(Index) ->
1301-
I1 = jit_aarch64_asm:ldr(Temp, {Reg, Index * 8}),
1302+
I1 = jit_aarch64_asm:ldr(Temp, {Reg, Index * ?WORD_SIZE}),
13021303
I2 = jit_aarch64_asm:str(Temp, ?X_REG(X)),
13031304
Stream1 = StreamModule:append(Stream0, <<I1/binary, I2/binary>>),
13041305
State#state{stream = Stream1};
@@ -1308,7 +1309,7 @@ move_array_element(
13081309
Index,
13091310
{ptr, Dest}
13101311
) when is_atom(Reg) andalso is_integer(Index) ->
1311-
I1 = jit_aarch64_asm:ldr(Temp, {Reg, Index * 8}),
1312+
I1 = jit_aarch64_asm:ldr(Temp, {Reg, Index * ?WORD_SIZE}),
13121313
I2 = jit_aarch64_asm:str(Temp, {Dest, 0}),
13131314
Stream1 = StreamModule:append(Stream0, <<I1/binary, I2/binary>>),
13141315
State#state{stream = Stream1};
@@ -1320,8 +1321,8 @@ move_array_element(
13201321
{y_reg, Y}
13211322
) when is_atom(Reg) andalso is_integer(Index) ->
13221323
I1 = jit_aarch64_asm:ldr(Temp1, ?Y_REGS),
1323-
I2 = jit_aarch64_asm:ldr(Temp2, {Reg, Index * 8}),
1324-
I3 = jit_aarch64_asm:str(Temp2, {Temp1, Y * 8}),
1324+
I2 = jit_aarch64_asm:ldr(Temp2, {Reg, Index * ?WORD_SIZE}),
1325+
I3 = jit_aarch64_asm:str(Temp2, {Temp1, Y * ?WORD_SIZE}),
13251326
Code = <<I1/binary, I2/binary, I3/binary>>,
13261327
Stream1 = StreamModule:append(Stream0, Code),
13271328
State#state{stream = Stream1};
@@ -1333,15 +1334,15 @@ move_array_element(
13331334
{y_reg, Y}
13341335
) when is_integer(Index) ->
13351336
I1 = jit_aarch64_asm:ldr(Temp, ?Y_REGS),
1336-
I2 = jit_aarch64_asm:ldr(Reg, {Reg, Index * 8}),
1337-
I3 = jit_aarch64_asm:str(Reg, {Temp, Y * 8}),
1337+
I2 = jit_aarch64_asm:ldr(Reg, {Reg, Index * ?WORD_SIZE}),
1338+
I3 = jit_aarch64_asm:str(Reg, {Temp, Y * ?WORD_SIZE}),
13381339
Code = <<I1/binary, I2/binary, I3/binary>>,
13391340
Stream1 = StreamModule:append(Stream0, Code),
13401341
State#state{stream = Stream1};
13411342
move_array_element(
13421343
#state{stream_module = StreamModule, stream = Stream0} = State, Reg, Index, Dest
13431344
) when is_atom(Dest) andalso is_integer(Index) ->
1344-
I1 = jit_aarch64_asm:ldr(Dest, {Reg, Index * 8}),
1345+
I1 = jit_aarch64_asm:ldr(Dest, {Reg, Index * ?WORD_SIZE}),
13451346
Stream1 = StreamModule:append(Stream0, I1),
13461347
State#state{stream = Stream1};
13471348
move_array_element(
@@ -1397,7 +1398,7 @@ move_array_element(
13971398
) when ?IS_GPR(IndexReg) ->
13981399
I1 = jit_aarch64_asm:ldr(Temp, ?Y_REGS),
13991400
I2 = jit_aarch64_asm:ldr(IndexReg, {Reg, IndexReg, lsl, 3}),
1400-
I3 = jit_aarch64_asm:str(IndexReg, {Temp, Y * 8}),
1401+
I3 = jit_aarch64_asm:str(IndexReg, {Temp, Y * ?WORD_SIZE}),
14011402
{AvailableRegs1, UsedRegs1} = free_reg(AvailableRegs0, UsedRegs0, IndexReg),
14021403
Stream1 = StreamModule:append(
14031404
Stream0, <<I1/binary, I2/binary, I3/binary>>
@@ -1428,7 +1429,7 @@ get_array_element(
14281429
{free, Reg},
14291430
Index
14301431
) ->
1431-
I1 = jit_aarch64_asm:ldr(Reg, {Reg, Index * 8}),
1432+
I1 = jit_aarch64_asm:ldr(Reg, {Reg, Index * ?WORD_SIZE}),
14321433
Stream1 = StreamModule:append(Stream0, <<I1/binary>>),
14331434
{State#state{stream = Stream1}, Reg};
14341435
get_array_element(
@@ -1441,7 +1442,7 @@ get_array_element(
14411442
Reg,
14421443
Index
14431444
) ->
1444-
I1 = jit_aarch64_asm:ldr(ElemReg, {Reg, Index * 8}),
1445+
I1 = jit_aarch64_asm:ldr(ElemReg, {Reg, Index * ?WORD_SIZE}),
14451446
Stream1 = StreamModule:append(Stream0, <<I1/binary>>),
14461447
{
14471448
State#state{
@@ -1469,7 +1470,7 @@ move_to_array_element(
14691470
Reg,
14701471
Index
14711472
) when ?IS_GPR(ValueReg) andalso ?IS_GPR(Reg) andalso is_integer(Index) ->
1472-
I1 = jit_aarch64_asm:str(ValueReg, {Reg, Index * 8}),
1473+
I1 = jit_aarch64_asm:str(ValueReg, {Reg, Index * ?WORD_SIZE}),
14731474
Stream1 = StreamModule:append(Stream0, I1),
14741475
State0#state{stream = Stream1};
14751476
move_to_array_element(
@@ -1607,7 +1608,7 @@ move_to_native_register(
16071608
{y_reg, Y}
16081609
) ->
16091610
I1 = jit_aarch64_asm:ldr(Reg, ?Y_REGS),
1610-
I2 = jit_aarch64_asm:ldr(Reg, {Reg, Y * 8}),
1611+
I2 = jit_aarch64_asm:ldr(Reg, {Reg, Y * ?WORD_SIZE}),
16111612
Code = <<I1/binary, I2/binary>>,
16121613
Stream1 = StreamModule:append(Stream0, Code),
16131614
{State#state{stream = Stream1, available_regs = AvailT, used_regs = [Reg | Used]}, Reg}.
@@ -1652,7 +1653,7 @@ move_to_native_register(
16521653
#state{stream_module = StreamModule, stream = Stream0} = State, {y_reg, Y}, RegDst
16531654
) ->
16541655
I1 = jit_aarch64_asm:ldr(RegDst, ?Y_REGS),
1655-
I2 = jit_aarch64_asm:ldr(RegDst, {RegDst, Y * 8}),
1656+
I2 = jit_aarch64_asm:ldr(RegDst, {RegDst, Y * ?WORD_SIZE}),
16561657
Code = <<I1/binary, I2/binary>>,
16571658
Stream1 = StreamModule:append(Stream0, Code),
16581659
State#state{stream = Stream1}.
@@ -1707,7 +1708,7 @@ move_to_cp(
17071708
{y_reg, Y}
17081709
) ->
17091710
I1 = jit_aarch64_asm:ldr(Reg, ?Y_REGS),
1710-
I2 = jit_aarch64_asm:ldr(Reg, {Reg, Y * 8}),
1711+
I2 = jit_aarch64_asm:ldr(Reg, {Reg, Y * ?WORD_SIZE}),
17111712
I3 = jit_aarch64_asm:str(Reg, ?CP),
17121713
Code = <<I1/binary, I2/binary, I3/binary>>,
17131714
Stream1 = StreamModule:append(Stream0, Code),
@@ -1726,7 +1727,7 @@ increment_sp(
17261727
Offset
17271728
) ->
17281729
I1 = jit_aarch64_asm:ldr(Reg, ?Y_REGS),
1729-
I2 = jit_aarch64_asm:add(Reg, Reg, Offset * 8),
1730+
I2 = jit_aarch64_asm:add(Reg, Reg, Offset * ?WORD_SIZE),
17301731
I3 = jit_aarch64_asm:str(Reg, ?Y_REGS),
17311732
Code = <<I1/binary, I2/binary, I3/binary>>,
17321733
Stream1 = StreamModule:append(Stream0, Code),

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