chore(atsamd-hal)!: MSRV to 1.85.1, 2024 edition

PR #875

Author: jbeaurivage

atsamd-hal-macros/Cargo.toml

@@ -1,9 +1,9 @@
 [package]
 authors = ["Tethys Svensson"]
 name = "atsamd-hal-macros"
-rust-version = "1.77.2"
+rust-version = "1.85.1"
 version = "0.2.5"
-edition = "2021"
+edition = "2024"
 license = "MIT OR Apache-2.0"
 categories = ["embedded", "hardware-support", "no-std"]
 description = "Procedural macros for the atsamd-hal library"

atsamd-hal-macros/build.rs

@@ -251,11 +251,11 @@ fn load_peripheral_mapping(
                         peripheral
                             .only
                             .as_ref()
-                            .map_or(true, |only| only.contains(key))
+                            .is_none_or(|only| only.contains(key))
                             && peripheral
                                 .except
                                 .as_ref()
-                                .map_or(true, |except| !except.contains(key))
+                                .is_none_or(|except| !except.contains(key))
                     })
                     .cloned();
                 peripheral_mapping
@@ -271,9 +271,11 @@ fn load_peripheral_mapping(
     }
 
     for (sub_peripheral_key, sub_peripheral) in peripheral_sub_mapping {
-        assert!(peripheral_mapping
-            .insert(sub_peripheral_key, sub_peripheral)
-            .is_none());
+        assert!(
+            peripheral_mapping
+                .insert(sub_peripheral_key, sub_peripheral)
+                .is_none()
+        );
     }
 
     Ok(peripheral_mapping)

hal/Cargo.toml

@@ -13,13 +13,13 @@ authors = [
 categories = ["embedded", "hardware-support", "no-std"]
 description = "HAL and Peripheral access API for ATSAMD11, ATSAMD21, ATSAMD51, ATSAME51, ATSAME53 and ATSAME54 microcontrollers"
 documentation = "https://docs.rs/crate/atsamd-hal/"
-edition = "2021"
+edition = "2024"
 keywords = ["no-std", "arm", "cortex-m", "embedded-hal"]
 license = "MIT OR Apache-2.0"
 name = "atsamd-hal"
 readme = "README.md"
 repository = "https://github.com/atsamd-rs/atsamd"
-rust-version = "1.77.2"
+rust-version = "1.85.1"
 version = "0.22.0"
 
 [package.metadata.docs.rs]

hal/src/async_hal/interrupts.rs

@@ -91,7 +91,9 @@ macro_rules! declare_multiple_interrupts {
             $(#[$cfg])*
             impl $crate::async_hal::interrupts::InterruptSource for $name {
                 unsafe fn enable() {
-                    $($crate::pac::Interrupt::$irq.enable();)+
+                    unsafe {
+                        $($crate::pac::Interrupt::$irq.enable();)+
+                    }
                 }
 
                 fn disable() {
@@ -242,7 +244,9 @@ pub trait InterruptSource: crate::typelevel::Sealed {
 
 impl<T: Interrupt> InterruptSource for T {
     unsafe fn enable() {
-        Self::enable();
+        unsafe {
+            Self::enable();
+        }
     }
 
     fn disable() {
@@ -278,7 +282,7 @@ pub trait Interrupt: crate::typelevel::Sealed {
     /// Do not enable any interrupt inside a critical section.
     #[inline]
     unsafe fn enable() {
-        Self::IRQ.enable()
+        unsafe { Self::IRQ.enable() }
     }
 
     /// Disable the interrupt.

hal/src/async_hal/mod.rs

@@ -6,11 +6,11 @@
 //!
 //! This module provides the basis for interacting with peripherals through
 //! `async` APIs. Notably, in order to function correctly and wake an `await`ing
-//! [`Future`](core::future::Future), peripherals must be able to signal when
-//! their respective interrupts fire. Traditionally, the user manually writes
-//! their own interrupt handlers. When using `async` APIs, the peripherals
-//! effectively take control of their own interrupt handlers in order to wake
-//! tasks at the appropriate time.
+//! [`Future`], peripherals must be able to signal when their respective
+//! interrupts fire. Traditionally, the user manually writes their own interrupt
+//! handlers. When using `async` APIs, the peripherals effectively take control
+//! of their own interrupt handlers in order to wake tasks at the appropriate
+//! time.
 //!
 //! ## Using the `async` APIs
 //!
@@ -172,7 +172,7 @@ macro_rules! bind_interrupts {
 
         $(
             #[allow(non_snake_case)]
-            #[no_mangle]
+            #[unsafe(no_mangle)]
             unsafe extern "C" fn $irq() {
                 $(
                     <$handler as $crate::async_hal::interrupts::Handler<$crate::async_hal::interrupts::$irq>>::on_interrupt();
@@ -225,7 +225,7 @@ macro_rules! bind_multiple_interrupts {
 
         $(
             #[allow(non_snake_case)]
-            #[no_mangle]
+            #[unsafe(no_mangle)]
             unsafe extern "C" fn $irq() {
                 <$handler as $crate::async_hal::interrupts::Handler<$crate::async_hal::interrupts::$int_source>>::on_interrupt();
             }

hal/src/delay.rs

@@ -1,8 +1,8 @@
 //! Delays
 
 use atsamd_hal_macros::hal_cfg;
-use cortex_m::peripheral::syst::SystClkSource;
 use cortex_m::peripheral::SYST;
+use cortex_m::peripheral::syst::SystClkSource;
 
 use crate::clock::GenericClockController;
 use crate::ehal::delay::DelayNs;
@@ -13,7 +13,7 @@ use crate::time::Hertz;
 use crate::typelevel::Increment;
 
 #[hal_cfg("rtc-d5x")]
-use crate::clock::v2::{gclk::Gclk0Id, Source};
+use crate::clock::v2::{Source, gclk::Gclk0Id};
 
 /// System timer (SysTick) as a delay provider
 pub struct Delay {

hal/src/dmac/async_api.rs

@@ -3,8 +3,8 @@
 use atsamd_hal_macros::hal_cfg;
 
 use crate::{
-    async_hal::interrupts::{Handler, DMAC},
-    dmac::{waker::WAKERS, TriggerSource},
+    async_hal::interrupts::{DMAC, Handler},
+    dmac::{TriggerSource, waker::WAKERS},
     util::BitIter,
 };
 

hal/src/dmac/channel/mod.rs

@@ -39,10 +39,10 @@ use core::sync::atomic;
 use atsamd_hal_macros::{hal_cfg, hal_macro_helper};
 
 use super::{
+    Beat, Buffer, Error,
     dma_controller::{ChId, PriorityLevel, TriggerAction, TriggerSource},
     sram::{self, DmacDescriptor},
     transfer::{BufferPair, Transfer},
-    Beat, Buffer, Error,
 };
 use crate::typelevel::{Is, Sealed};
 use modular_bitfield::prelude::*;
@@ -351,7 +351,9 @@ impl<Id: ChId, S: Status> Channel<Id, S> {
             core::ptr::null_mut()
         };
 
-        write_descriptor(descriptor, source, destination, descaddr);
+        unsafe {
+            write_descriptor(descriptor, source, destination, descaddr);
+        }
     }
 
     /// Add a linked descriptor after the first descriptor in the transfer.
@@ -524,7 +526,9 @@ impl<Id: ChId> Channel<Id, Ready> {
         D: Buffer<Beat = S::Beat>,
     {
         Transfer::<Self, BufferPair<S, D>>::check_buffer_pair(source, dest)?;
-        self.transfer_unchecked(source, dest, trig_src, trig_act, linked_descriptor);
+        unsafe {
+            self.transfer_unchecked(source, dest, trig_src, trig_act, linked_descriptor);
+        }
         Ok(())
     }
 
@@ -559,10 +563,12 @@ impl<Id: ChId> Channel<Id, Ready> {
         S: Buffer,
         D: Buffer<Beat = S::Beat>,
     {
-        self.fill_descriptor(source, dest, false);
+        unsafe {
+            self.fill_descriptor(source, dest, false);
 
-        if let Some(next) = linked_descriptor {
-            self.link_next(next as *mut _);
+            if let Some(next) = linked_descriptor {
+                self.link_next(next as *mut _);
+            }
         }
 
         self.configure_trigger(trig_src, trig_act);

hal/src/dmac/channel/reg.rs

@@ -17,13 +17,12 @@ use core::marker::PhantomData;
 use paste::paste;
 
 use crate::pac::{
-    self,
+    self, Dmac, Peripherals,
+    dmac::{Busych, Intstatus, Pendch, Swtrigctrl},
     dmac::{
         busych::BusychSpec, intstatus::IntstatusSpec, pendch::PendchSpec,
         swtrigctrl::SwtrigctrlSpec,
     },
-    dmac::{Busych, Intstatus, Pendch, Swtrigctrl},
-    Dmac, Peripherals,
 };
 
 #[hal_cfg(any("dmac-d11", "dmac-d21"))]
@@ -33,13 +32,13 @@ use pac::dmac as channel_regs;
 use pac::dmac::channel as channel_regs;
 
 use channel_regs::{
-    chctrla::ChctrlaSpec, chctrlb::ChctrlbSpec, chintenclr::ChintenclrSpec,
-    chintenset::ChintensetSpec, chintflag::ChintflagSpec, chstatus::ChstatusSpec,
+    Chctrla, Chctrlb, Chintenclr, Chintenset, Chintflag, Chstatus, chctrla::ChctrlaSpec,
+    chctrlb::ChctrlbSpec, chintenclr::ChintenclrSpec, chintenset::ChintensetSpec,
+    chintflag::ChintflagSpec, chstatus::ChstatusSpec,
 };
-use channel_regs::{Chctrla, Chctrlb, Chintenclr, Chintenset, Chintflag, Chstatus};
 
 #[hal_cfg("dmac-d5x")]
-use pac::dmac::channel::{chprilvl::ChprilvlSpec, Chprilvl};
+use pac::dmac::channel::{Chprilvl, chprilvl::ChprilvlSpec};
 
 //==============================================================================
 // RegisterBlock

hal/src/dmac/dma_controller.rs

@@ -293,11 +293,11 @@ impl<T> DmaController<T> {
     pub fn into_future<I>(self, _interrupts: I) -> DmaController<I>
     where
         I: crate::async_hal::interrupts::Binding<
-            crate::async_hal::interrupts::DMAC,
-            super::async_api::InterruptHandler,
-        >,
+                crate::async_hal::interrupts::DMAC,
+                super::async_api::InterruptHandler,
+            >,
     {
-        use crate::async_hal::interrupts::{InterruptSource, DMAC};
+        use crate::async_hal::interrupts::{DMAC, InterruptSource};
 
         DMAC::unpend();
         unsafe { DMAC::enable() };
@@ -320,9 +320,9 @@ impl<T> DmaController<T> {
 impl<I> DmaController<I>
 where
     I: crate::async_hal::interrupts::Binding<
-        crate::async_hal::interrupts::DMAC,
-        super::async_api::InterruptHandler,
-    >,
+            crate::async_hal::interrupts::DMAC,
+            super::async_api::InterruptHandler,
+        >,
 {
     /// Release the DMAC and return the register block.
     ///
@@ -390,9 +390,9 @@ macro_rules! define_split_future {
 impl<I> DmaController<I>
 where
     I: crate::async_hal::interrupts::Binding<
-        crate::async_hal::interrupts::DMAC,
-        super::async_api::InterruptHandler,
-    >,
+            crate::async_hal::interrupts::DMAC,
+            super::async_api::InterruptHandler,
+        >,
 {
     with_num_channels!(define_split_future);
 }