Merge commit 'b57cbbcb6a6b' from llvm.org/main into next

Author: git apple-llvm automerger

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

@@ -90,6 +90,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
   const LLT s16 = LLT::scalar(16);
   const LLT s32 = LLT::scalar(32);
   const LLT s64 = LLT::scalar(64);
+  const LLT s128 = LLT::scalar(128);
 
   const LLT nxv1s1 = LLT::scalable_vector(1, s1);
   const LLT nxv2s1 = LLT::scalable_vector(2, s1);
@@ -535,13 +536,16 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
   getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
       .legalIf(all(typeInSet(0, {s32, sXLen}), typeIsScalarFPArith(1, ST)))
       .widenScalarToNextPow2(0)
-      .clampScalar(0, s32, sXLen)
-      .libcall();
+      .minScalar(0, s32)
+      .libcallFor({{s32, s32}, {s64, s32}, {s32, s64}, {s64, s64}})
+      .libcallFor(ST.is64Bit(), {{s128, s32}, {s128, s64}});
 
   getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
       .legalIf(all(typeIsScalarFPArith(0, ST), typeInSet(1, {s32, sXLen})))
       .widenScalarToNextPow2(1)
-      .clampScalar(1, s32, sXLen);
+      .minScalar(1, s32)
+      .libcallFor({{s32, s32}, {s64, s32}, {s32, s64}, {s64, s64}})
+      .libcallFor(ST.is64Bit(), {{s32, s128}, {s64, s128}});
 
   // FIXME: We can do custom inline expansion like SelectionDAG.
   // FIXME: Legal with Zfa.

llvm/test/CodeGen/RISCV/GlobalISel/double-convert.ll

@@ -0,0 +1,370 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+d -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32d | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64d | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
+
+define float @fcvt_s_d(double %a) nounwind {
+; CHECKIFD-LABEL: fcvt_s_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.s.d fa0, fa0
+; CHECKIFD-NEXT:    ret
+  %1 = fptrunc double %a to float
+  ret float %1
+}
+
+define double @fcvt_d_s(float %a) nounwind {
+; CHECKIFD-LABEL: fcvt_d_s:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.s fa0, fa0
+; CHECKIFD-NEXT:    ret
+  %1 = fpext float %a to double
+  ret double %1
+}
+
+define i32 @fcvt_w_d(double %a) nounwind {
+; CHECKIFD-LABEL: fcvt_w_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; CHECKIFD-NEXT:    ret
+  %1 = fptosi double %a to i32
+  ret i32 %1
+}
+
+define i32 @fcvt_wu_d(double %a) nounwind {
+; CHECKIFD-LABEL: fcvt_wu_d:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT:    ret
+  %1 = fptoui double %a to i32
+  ret i32 %1
+}
+
+define i32 @fcvt_wu_d_multiple_use(double %x, ptr %y) nounwind {
+; RV32IFD-LABEL: fcvt_wu_d_multiple_use:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    fcvt.wu.d a1, fa0, rtz
+; RV32IFD-NEXT:    li a0, 1
+; RV32IFD-NEXT:    beqz a1, .LBB4_2
+; RV32IFD-NEXT:  # %bb.1:
+; RV32IFD-NEXT:    mv a0, a1
+; RV32IFD-NEXT:  .LBB4_2:
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fcvt.wu.d a1, fa0, rtz
+; RV64IFD-NEXT:    slli a0, a1, 32
+; RV64IFD-NEXT:    srli a2, a0, 32
+; RV64IFD-NEXT:    li a0, 1
+; RV64IFD-NEXT:    beqz a2, .LBB4_2
+; RV64IFD-NEXT:  # %bb.1:
+; RV64IFD-NEXT:    mv a0, a1
+; RV64IFD-NEXT:  .LBB4_2:
+; RV64IFD-NEXT:    ret
+  %a = fptoui double %x to i32
+  %b = icmp eq i32 %a, 0
+  %c = select i1 %b, i32 1, i32 %a
+  ret i32 %c
+}
+
+define double @fcvt_d_w(i32 %a) nounwind {
+; CHECKIFD-LABEL: fcvt_d_w:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
+  %1 = sitofp i32 %a to double
+  ret double %1
+}
+
+define double @fcvt_d_w_load(ptr %p) nounwind {
+; CHECKIFD-LABEL: fcvt_d_w_load:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    lw a0, 0(a0)
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
+  %a = load i32, ptr %p
+  %1 = sitofp i32 %a to double
+  ret double %1
+}
+
+define double @fcvt_d_wu(i32 %a) nounwind {
+; CHECKIFD-LABEL: fcvt_d_wu:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT:    ret
+  %1 = uitofp i32 %a to double
+  ret double %1
+}
+
+define double @fcvt_d_wu_load(ptr %p) nounwind {
+; CHECKIFD-LABEL: fcvt_d_wu_load:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    lw a0, 0(a0)
+; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT:    ret
+  %a = load i32, ptr %p
+  %1 = uitofp i32 %a to double
+  ret double %1
+}
+
+define i64 @fcvt_l_d(double %a) nounwind {
+; RV32IFD-LABEL: fcvt_l_d:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi sp, sp, -16
+; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT:    call __fixdfdi
+; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT:    addi sp, sp, 16
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_l_d:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fcvt.l.d a0, fa0, rtz
+; RV64IFD-NEXT:    ret
+  %1 = fptosi double %a to i64
+  ret i64 %1
+}
+
+define i64 @fcvt_lu_d(double %a) nounwind {
+; RV32IFD-LABEL: fcvt_lu_d:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi sp, sp, -16
+; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT:    call __fixunsdfdi
+; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT:    addi sp, sp, 16
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_lu_d:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fcvt.lu.d a0, fa0, rtz
+; RV64IFD-NEXT:    ret
+  %1 = fptoui double %a to i64
+  ret i64 %1
+}
+
+define i64 @fmv_x_d(double %a, double %b) nounwind {
+; RV32IFD-LABEL: fmv_x_d:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi sp, sp, -16
+; RV32IFD-NEXT:    fadd.d fa5, fa0, fa1
+; RV32IFD-NEXT:    fsd fa5, 8(sp)
+; RV32IFD-NEXT:    lw a0, 8(sp)
+; RV32IFD-NEXT:    lw a1, 12(sp)
+; RV32IFD-NEXT:    addi sp, sp, 16
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fmv_x_d:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fadd.d fa5, fa0, fa1
+; RV64IFD-NEXT:    fmv.x.d a0, fa5
+; RV64IFD-NEXT:    ret
+  %1 = fadd double %a, %b
+  %2 = bitcast double %1 to i64
+  ret i64 %2
+}
+
+define double @fcvt_d_l(i64 %a) nounwind {
+; RV32IFD-LABEL: fcvt_d_l:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi sp, sp, -16
+; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT:    call __floatdidf
+; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT:    addi sp, sp, 16
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_d_l:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fcvt.d.l fa0, a0
+; RV64IFD-NEXT:    ret
+  %1 = sitofp i64 %a to double
+  ret double %1
+}
+
+define double @fcvt_d_lu(i64 %a) nounwind {
+; RV32IFD-LABEL: fcvt_d_lu:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi sp, sp, -16
+; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT:    call __floatundidf
+; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT:    addi sp, sp, 16
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_d_lu:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fcvt.d.lu fa0, a0
+; RV64IFD-NEXT:    ret
+  %1 = uitofp i64 %a to double
+  ret double %1
+}
+
+define double @fmv_d_x(i64 %a, i64 %b) nounwind {
+; RV32IFD-LABEL: fmv_d_x:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi sp, sp, -16
+; RV32IFD-NEXT:    sw a0, 8(sp)
+; RV32IFD-NEXT:    sw a1, 12(sp)
+; RV32IFD-NEXT:    fld fa5, 8(sp)
+; RV32IFD-NEXT:    sw a2, 8(sp)
+; RV32IFD-NEXT:    sw a3, 12(sp)
+; RV32IFD-NEXT:    fld fa4, 8(sp)
+; RV32IFD-NEXT:    fadd.d fa0, fa5, fa4
+; RV32IFD-NEXT:    addi sp, sp, 16
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fmv_d_x:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fmv.d.x fa5, a0
+; RV64IFD-NEXT:    fmv.d.x fa4, a1
+; RV64IFD-NEXT:    fadd.d fa0, fa5, fa4
+; RV64IFD-NEXT:    ret
+  %1 = bitcast i64 %a to double
+  %2 = bitcast i64 %b to double
+  %3 = fadd double %1, %2
+  ret double %3
+}
+
+define double @fcvt_d_w_i8(i8 signext %a) nounwind {
+; CHECKIFD-LABEL: fcvt_d_w_i8:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
+  %1 = sitofp i8 %a to double
+  ret double %1
+}
+
+define double @fcvt_d_wu_i8(i8 zeroext %a) nounwind {
+; CHECKIFD-LABEL: fcvt_d_wu_i8:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT:    ret
+  %1 = uitofp i8 %a to double
+  ret double %1
+}
+
+define double @fcvt_d_w_i16(i16 signext %a) nounwind {
+; CHECKIFD-LABEL: fcvt_d_w_i16:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.w fa0, a0
+; CHECKIFD-NEXT:    ret
+  %1 = sitofp i16 %a to double
+  ret double %1
+}
+
+define double @fcvt_d_wu_i16(i16 zeroext %a) nounwind {
+; CHECKIFD-LABEL: fcvt_d_wu_i16:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.d.wu fa0, a0
+; CHECKIFD-NEXT:    ret
+  %1 = uitofp i16 %a to double
+  ret double %1
+}
+
+define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
+; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi a0, a0, 1
+; RV32IFD-NEXT:    fcvt.d.w fa5, a0
+; RV32IFD-NEXT:    fsd fa5, 0(a1)
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    addiw a0, a0, 1
+; RV64IFD-NEXT:    fcvt.d.w fa5, a0
+; RV64IFD-NEXT:    fsd fa5, 0(a1)
+; RV64IFD-NEXT:    ret
+  %3 = add i32 %0, 1
+  %4 = sitofp i32 %3 to double
+  store double %4, ptr %1, align 8
+  ret i32 %3
+}
+
+define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
+; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi a0, a0, 1
+; RV32IFD-NEXT:    fcvt.d.wu fa5, a0
+; RV32IFD-NEXT:    fsd fa5, 0(a1)
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    addiw a0, a0, 1
+; RV64IFD-NEXT:    fcvt.d.wu fa5, a0
+; RV64IFD-NEXT:    fsd fa5, 0(a1)
+; RV64IFD-NEXT:    ret
+  %3 = add i32 %0, 1
+  %4 = uitofp i32 %3 to double
+  store double %4, ptr %1, align 8
+  ret i32 %3
+}
+
+define signext i16 @fcvt_w_s_i16(double %a) nounwind {
+; RV32IFD-LABEL: fcvt_w_s_i16:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; RV32IFD-NEXT:    slli a0, a0, 16
+; RV32IFD-NEXT:    srai a0, a0, 16
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_w_s_i16:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; RV64IFD-NEXT:    slli a0, a0, 48
+; RV64IFD-NEXT:    srai a0, a0, 48
+; RV64IFD-NEXT:    ret
+  %1 = fptosi double %a to i16
+  ret i16 %1
+}
+
+define zeroext i16 @fcvt_wu_s_i16(double %a) nounwind {
+; RV32IFD-LABEL: fcvt_wu_s_i16:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; RV32IFD-NEXT:    lui a1, 16
+; RV32IFD-NEXT:    addi a1, a1, -1
+; RV32IFD-NEXT:    and a0, a0, a1
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_wu_s_i16:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; RV64IFD-NEXT:    lui a1, 16
+; RV64IFD-NEXT:    addiw a1, a1, -1
+; RV64IFD-NEXT:    and a0, a0, a1
+; RV64IFD-NEXT:    ret
+  %1 = fptoui double %a to i16
+  ret i16 %1
+}
+
+define signext i8 @fcvt_w_s_i8(double %a) nounwind {
+; RV32IFD-LABEL: fcvt_w_s_i8:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; RV32IFD-NEXT:    slli a0, a0, 24
+; RV32IFD-NEXT:    srai a0, a0, 24
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_w_s_i8:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fcvt.w.d a0, fa0, rtz
+; RV64IFD-NEXT:    slli a0, a0, 56
+; RV64IFD-NEXT:    srai a0, a0, 56
+; RV64IFD-NEXT:    ret
+  %1 = fptosi double %a to i8
+  ret i8 %1
+}
+
+define zeroext i8 @fcvt_wu_s_i8(double %a) nounwind {
+; CHECKIFD-LABEL: fcvt_wu_s_i8:
+; CHECKIFD:       # %bb.0:
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT:    andi a0, a0, 255
+; CHECKIFD-NEXT:    ret
+  %1 = fptoui double %a to i8
+  ret i8 %1
+}