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karstenkoenigrlubos
karstenkoenig
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rlubos
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[nrf fromtree] boards: nordic: nrf54h20dk: ETM in JLinkScript
The JLinkScript originally configured more than needed which reduces readability, so stripped it down to the minimum. At the same time improved behavior under reset and added ETM to the radiocore JLinkScript. Signed-off-by: Karsten Koenig <[email protected]> (cherry picked from commit a50dc9f)
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‎boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript‎

Lines changed: 62 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -1,36 +1,27 @@
1+
/*
2+
* Copyright (c) 2024 Nordic Semiconductor ASA
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
17
__constant U32 _CPUCONF_ADDR = 0x52011000;
28
__constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C;
39

410
// ATBFUNNEL
511
__constant U32 _ATBFUNNEL211_ADDR = 0xBF04D000;
612
__constant U32 _ATBFUNNEL212_ADDR = 0xBF04E000;
713
__constant U32 _ATBFUNNEL_CTRLREG_OFFSET = 0x0;
14+
__constant U32 _ATBFUNNEL_HOLDTIME_MASK = 0x700;
815
__constant U32 _HOLDTIME_4 = 0x300;
9-
__constant U32 _ENS0 = 0x1;
10-
__constant U32 _ENS1 = 0x2;
11-
__constant U32 _ENS2 = 0x4;
16+
__constant U32 _ENS0 = 0x1; // Application Core
17+
__constant U32 _ENS1 = 0x2; // Radio Core
1218

1319
// ATBREPLICATOR
1420
__constant U32 _ATBREPLICATOR212_ADDR = 0xBF04A000;
1521
__constant U32 _ATBREPLICATOR213_ADDR = 0xBF04B000;
1622
__constant U32 _ATBREPLICATOR_IDFILTER0_OFFSET = 0x0;
1723
__constant U32 _ATBREPLICATOR_IDFILTER1_OFFSET = 0x4;
18-
__constant U32 _ID_NONE = 0xFFFFFFFF;
19-
__constant U32 _ID1x = 0xFFFFFFFD;
20-
21-
// TSGEN
22-
__constant U32 _TSGEN_ADDR = 0xBF041000;
23-
__constant U32 _TSGEN_CNTCR_OFFSET = 0x0;
24-
__constant U32 _TSGEN_CNTFID0_OFFSET = 0x20;
25-
// Clock rate = TDD Freq. / 8
26-
__constant U32 _TS_CLOCKRATE = 40000000;
27-
28-
// CTI
29-
__constant U32 _CTI210_ADDR = 0xBF046000;
30-
__constant U32 _CTICONTROL_OFFSET = 0x0;
31-
__constant U32 _CTIOUTEN_OFFSET = 0xA0;
32-
__constant U32 _CTIGATE_OFFSET = 0x140;
33-
__constant U32 _TPIU_FLUSH_TRIG = 0x2;
24+
__constant U32 _ATBREPLICATOR_IDFILTER_ETM = 0x2; // ETM has 0x10 TRACEID
3425

3526
// TPIU
3627
__constant U32 _TPIU_ADDR = 0xBF043000;
@@ -43,30 +34,10 @@ __constant U32 _ENFTC = 0x1;
4334
__constant U32 _TPIU_SYNC_FRAME_COUNT = 0x8;
4435
__constant U32 _CURRENTPORTSIZE_4 = 0x8;
4536

46-
// TDDCONF
47-
__constant U32 _TDDCONF_ADDR = 0xBF001000;
48-
__constant U32 _TRACEPORTSPEED_OFFSET = 0x408;
49-
__constant U32 _SPEED80MHZ = 0x0;
50-
5137
// CoreSight general
52-
__constant U32 _CORESIGHT_CLAIMSET_OFFSET = 0xFA0;
53-
__constant U32 _CORESIGHT_CLAIMCLR_OFFSET = 0xFA4;
5438
__constant U32 _CORESIGHT_LAR_OFFSET = 0xFB0;
5539
__constant U32 _CORESIGHT_UNLOCK_KEY = 0xC5ACCE55;
5640

57-
// GPIO P7
58-
__constant U32 _P7_ADDR = 0x5F938E00;
59-
__constant U32 _PIN_CNF3_OFFSET = 0x8C;
60-
__constant U32 _PIN_CNF4_OFFSET = 0x90;
61-
__constant U32 _PIN_CNF5_OFFSET = 0x94;
62-
__constant U32 _PIN_CNF6_OFFSET = 0x98;
63-
__constant U32 _PIN_CNF7_OFFSET = 0x9C;
64-
__constant U32 _PIN_CNF_TPIU_CLOCK_VALUE = 0x80000503;
65-
__constant U32 _PIN_CNF_TPIU_DATA_VALUE = 0x00000503;
66-
67-
// Settings
68-
__constant U32 _DEBUGGER_CLAIM_MASK = 0x2;
69-
7041
// Used to check if we have already set up tracing
7142
int _needCoresightSetup = 1;
7243

@@ -82,68 +53,59 @@ void _CSLock(U32 addr)
8253
JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, 0);
8354
}
8455

85-
// Set claim bits in the CoreSight peripheral to indicate to the firmware that it
86-
// has been configured by the host debugger
87-
void _CSClaim(U32 addr)
88-
{
89-
JLINK_MEM_WriteU32(addr + _CORESIGHT_CLAIMSET_OFFSET, _DEBUGGER_CLAIM_MASK);
90-
}
91-
9256
// Set up CoreSight and other necessary configuration so to enable ETM -> TPIU tracing.
9357
int _SetupETMTPIUTrace(void)
9458
{
59+
U32 ctrlreg_old;
60+
U32 ctrlreg_new;
61+
U32 idfilter0_old;
62+
U32 idfilter1_old;
63+
U32 idfilter0_new;
64+
U32 idfilter1_new;
65+
9566
// Set up ATB funnels/replicators to route ApplicationDomain ETM to TPIU
67+
9668
_CSUnlock(_ATBFUNNEL212_ADDR);
97-
JLINK_MEM_WriteU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, _HOLDTIME_4 | _ENS0);
98-
_CSClaim(_ATBFUNNEL212_ADDR);
69+
ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET);
70+
ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS0;
71+
JLINK_MEM_WriteU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new);
9972
_CSLock(_ATBFUNNEL212_ADDR);
10073

10174
_CSUnlock(_ATBREPLICATOR212_ADDR);
102-
JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, _ID_NONE);
103-
JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, _ID1x);
104-
_CSLock(_ATBREPLICATOR212_ADDR);
105-
_CSClaim(_ATBREPLICATOR212_ADDR);
75+
idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET);
76+
idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET);
77+
78+
idfilter0_new = idfilter0_old | _ATBREPLICATOR_IDFILTER_ETM; // SET for output 0
79+
idfilter1_new = idfilter1_old & ~_ATBREPLICATOR_IDFILTER_ETM; // CLEAR for output 1
80+
81+
JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new);
82+
JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new);
10683
_CSLock(_ATBREPLICATOR212_ADDR);
10784

10885
_CSUnlock(_ATBFUNNEL211_ADDR);
109-
JLINK_MEM_WriteU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, _HOLDTIME_4 | _ENS0);
110-
_CSClaim(_ATBFUNNEL211_ADDR);
86+
ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET);
87+
ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS0;
88+
JLINK_MEM_WriteU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new);
11189
_CSLock(_ATBFUNNEL211_ADDR);
11290

11391
_CSUnlock(_ATBREPLICATOR213_ADDR);
114-
JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, _ID1x);
115-
JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, _ID_NONE);
116-
_CSClaim(_ATBREPLICATOR213_ADDR);
117-
_CSLock(_ATBREPLICATOR213_ADDR);
92+
idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET);
93+
idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET);
11894

119-
// Configure timestamp generator for the correct clock rate
120-
JLINK_MEM_WriteU32(_TSGEN_ADDR + _TSGEN_CNTFID0_OFFSET, _TS_CLOCKRATE);
121-
JLINK_MEM_WriteU32(_TSGEN_ADDR + _TSGEN_CNTCR_OFFSET, 1);
122-
_CSClaim(_TSGEN_ADDR);
95+
idfilter0_new = idfilter0_old & ~_ATBREPLICATOR_IDFILTER_ETM; // CLEAR for output 0
96+
idfilter1_new = idfilter1_old | _ATBREPLICATOR_IDFILTER_ETM; // SET for output 1
12397

124-
// Configure CTI1 for TPIU formatter flushing
125-
_CSUnlock(_CTI210_ADDR);
126-
JLINK_MEM_WriteU32(_CTI210_ADDR + _CTIOUTEN_OFFSET, _TPIU_FLUSH_TRIG);
127-
JLINK_MEM_WriteU32(_CTI210_ADDR + _CTIGATE_OFFSET, _TPIU_FLUSH_TRIG);
128-
JLINK_MEM_WriteU32(_CTI210_ADDR + _CTICONTROL_OFFSET, 1);
129-
_CSClaim(_CTI210_ADDR);
130-
_CSLock(_CTI210_ADDR);
98+
JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new);
99+
JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new);
100+
_CSLock(_ATBREPLICATOR213_ADDR);
131101

132102
// Configure TPIU for port size 4, continuous formatting
133103
_CSUnlock(_TPIU_ADDR);
134104
JLINK_MEM_WriteU32(_TPIU_ADDR + _CURRENTPORTSIZE_OFFSET, _CURRENTPORTSIZE_4);
135105
JLINK_MEM_WriteU32(_TPIU_ADDR + _FFCR_OFFSET, _ENFCONT | _FONFLIN | _ENFTC);
136106
JLINK_MEM_WriteU32(_TPIU_ADDR + _FSCR_OFFSET, _TPIU_SYNC_FRAME_COUNT);
137-
_CSClaim(_TPIU_ADDR);
138107
_CSLock(_TPIU_ADDR);
139108

140-
// Configure the trace pins
141-
JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF3_OFFSET, _PIN_CNF_TPIU_CLOCK_VALUE);
142-
JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF4_OFFSET, _PIN_CNF_TPIU_DATA_VALUE);
143-
JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF5_OFFSET, _PIN_CNF_TPIU_DATA_VALUE);
144-
JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF6_OFFSET, _PIN_CNF_TPIU_DATA_VALUE);
145-
JLINK_MEM_WriteU32(_P7_ADDR + _PIN_CNF7_OFFSET, _PIN_CNF_TPIU_DATA_VALUE);
146-
147109
return 0;
148110
}
149111

@@ -155,6 +117,19 @@ int ConfigTargetSettings(void)
155117
// Adjust trace sample delay to compensate for timing when using 320MHz
156118
JLINK_ExecCommand("TraceSampleAdjust TD = 1000");
157119

120+
JLINK_ExecCommand("CORESIGHT_SetTPIUBaseAddr = 0xBF043000");
121+
122+
return 0;
123+
}
124+
125+
int StartTPIU(void)
126+
{
127+
/* We sort this ourselves in _SetupETMTPIUTrace, don't let JLink touch it */
128+
return 0;
129+
}
130+
131+
int StopTPIU(void)
132+
{
158133
return 0;
159134
}
160135

@@ -169,6 +144,11 @@ int OnTraceStart(void)
169144
return 0;
170145
}
171146

147+
int AfterResetTarget(void)
148+
{
149+
_needCoresightSetup = 1;
150+
return 0;
151+
}
172152

173153
int SetupTarget(void)
174154
{
@@ -179,3 +159,8 @@ int SetupTarget(void)
179159

180160
return 0;
181161
}
162+
163+
int InitEMU(void) {
164+
JLINK_ExecCommand("EnableLowPowerHandlingMode");
165+
return 0;
166+
}

‎boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript‎

Lines changed: 148 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,153 @@
1-
__constant U32 _CPUCONF_ADDR = 0x53011000;
1+
/*
2+
* Copyright (c) 2024 Nordic Semiconductor ASA
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
__constant U32 _CPUCONF_ADDR = 0x52011000;
28
__constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C;
39

10+
// ATBFUNNEL
11+
__constant U32 _ATBFUNNEL211_ADDR = 0xBF04D000;
12+
__constant U32 _ATBFUNNEL212_ADDR = 0xBF04E000;
13+
__constant U32 _ATBFUNNEL_CTRLREG_OFFSET = 0x0;
14+
__constant U32 _ATBFUNNEL_HOLDTIME_MASK = 0x700;
15+
__constant U32 _HOLDTIME_4 = 0x300;
16+
__constant U32 _ENS0 = 0x1; // Application Core
17+
__constant U32 _ENS1 = 0x2; // Radio Core
18+
19+
// ATBREPLICATOR
20+
__constant U32 _ATBREPLICATOR212_ADDR = 0xBF04A000;
21+
__constant U32 _ATBREPLICATOR213_ADDR = 0xBF04B000;
22+
__constant U32 _ATBREPLICATOR_IDFILTER0_OFFSET = 0x0;
23+
__constant U32 _ATBREPLICATOR_IDFILTER1_OFFSET = 0x4;
24+
__constant U32 _ATBREPLICATOR_IDFILTER_ETM = 0x2; // ETM has 0x10 TRACEID
25+
26+
// TPIU
27+
__constant U32 _TPIU_ADDR = 0xBF043000;
28+
__constant U32 _CURRENTPORTSIZE_OFFSET = 0x4;
29+
__constant U32 _FFCR_OFFSET = 0x304;
30+
__constant U32 _FSCR_OFFSET = 0x308;
31+
__constant U32 _ENFCONT = 0x02;
32+
__constant U32 _FONFLIN = 0x10;
33+
__constant U32 _ENFTC = 0x1;
34+
__constant U32 _TPIU_SYNC_FRAME_COUNT = 0x8;
35+
__constant U32 _CURRENTPORTSIZE_4 = 0x8;
36+
37+
// CoreSight general
38+
__constant U32 _CORESIGHT_LAR_OFFSET = 0xFB0;
39+
__constant U32 _CORESIGHT_UNLOCK_KEY = 0xC5ACCE55;
40+
41+
// Used to check if we have already set up tracing
42+
int _needCoresightSetup = 1;
43+
44+
// Unlock a CoreSight peripheral
45+
void _CSUnlock(U32 addr)
46+
{
47+
JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, _CORESIGHT_UNLOCK_KEY);
48+
}
49+
50+
// Lock a CoreSight peripheral
51+
void _CSLock(U32 addr)
52+
{
53+
JLINK_MEM_WriteU32(addr + _CORESIGHT_LAR_OFFSET, 0);
54+
}
55+
56+
// Set up CoreSight and other necessary configuration so to enable ETM -> TPIU tracing.
57+
int _SetupETMTPIUTrace(void)
58+
{
59+
U32 ctrlreg_old;
60+
U32 ctrlreg_new;
61+
U32 idfilter0_old;
62+
U32 idfilter1_old;
63+
U32 idfilter0_new;
64+
U32 idfilter1_new;
65+
66+
// Set up ATB funnels/replicators to route ApplicationDomain ETM to TPIU
67+
68+
_CSUnlock(_ATBFUNNEL212_ADDR);
69+
ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET);
70+
ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS1;
71+
JLINK_MEM_WriteU32(_ATBFUNNEL212_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new);
72+
_CSLock(_ATBFUNNEL212_ADDR);
73+
74+
_CSUnlock(_ATBREPLICATOR212_ADDR);
75+
idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET);
76+
idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET);
77+
78+
idfilter0_new = idfilter0_old | _ATBREPLICATOR_IDFILTER_ETM; // SET for output 0
79+
idfilter1_new = idfilter1_old & ~_ATBREPLICATOR_IDFILTER_ETM; // CLEAR for output 1
80+
81+
JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new);
82+
JLINK_MEM_WriteU32(_ATBREPLICATOR212_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new);
83+
_CSLock(_ATBREPLICATOR212_ADDR);
84+
85+
_CSUnlock(_ATBFUNNEL211_ADDR);
86+
ctrlreg_old = JLINK_MEM_ReadU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET);
87+
ctrlreg_new = (ctrlreg_old & ~_ATBFUNNEL_HOLDTIME_MASK) | _HOLDTIME_4 | _ENS1;
88+
JLINK_MEM_WriteU32(_ATBFUNNEL211_ADDR + _ATBFUNNEL_CTRLREG_OFFSET, ctrlreg_new);
89+
_CSLock(_ATBFUNNEL211_ADDR);
90+
91+
_CSUnlock(_ATBREPLICATOR213_ADDR);
92+
idfilter0_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET);
93+
idfilter1_old = JLINK_MEM_ReadU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET);
94+
95+
idfilter0_new = idfilter0_old & ~_ATBREPLICATOR_IDFILTER_ETM; // CLEAR for output 0
96+
idfilter1_new = idfilter1_old | _ATBREPLICATOR_IDFILTER_ETM; // SET for output 1
97+
98+
JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER0_OFFSET, idfilter0_new);
99+
JLINK_MEM_WriteU32(_ATBREPLICATOR213_ADDR + _ATBREPLICATOR_IDFILTER1_OFFSET, idfilter1_new);
100+
_CSLock(_ATBREPLICATOR213_ADDR);
101+
102+
// Configure TPIU for port size 4, continuous formatting
103+
_CSUnlock(_TPIU_ADDR);
104+
JLINK_MEM_WriteU32(_TPIU_ADDR + _CURRENTPORTSIZE_OFFSET, _CURRENTPORTSIZE_4);
105+
JLINK_MEM_WriteU32(_TPIU_ADDR + _FFCR_OFFSET, _ENFCONT | _FONFLIN | _ENFTC);
106+
JLINK_MEM_WriteU32(_TPIU_ADDR + _FSCR_OFFSET, _TPIU_SYNC_FRAME_COUNT);
107+
_CSLock(_TPIU_ADDR);
108+
109+
return 0;
110+
}
111+
4112
int ConfigTargetSettings(void)
5113
{
6114
JLINK_ExecCommand("CORESIGHT_AddAP = Index=1 Type=AHB-AP");
7115
CORESIGHT_IndexAHBAPToUse = 1;
8116

117+
// Adjust trace sample delay to compensate for timing when using 320MHz
118+
JLINK_ExecCommand("TraceSampleAdjust TD = 1000");
119+
120+
JLINK_ExecCommand("CORESIGHT_SetTPIUBaseAddr = 0xBF043000");
121+
122+
return 0;
123+
}
124+
125+
int StartTPIU(void)
126+
{
127+
/* We sort this ourselves in _SetupETMTPIUTrace, don't let JLink touch it */
128+
return 0;
129+
}
130+
131+
int StopTPIU(void)
132+
{
133+
return 0;
134+
}
135+
136+
137+
int OnTraceStart(void)
138+
{
139+
// Set up CoreSight if not already configured
140+
if (_needCoresightSetup) {
141+
_SetupETMTPIUTrace();
142+
_needCoresightSetup = 0;
143+
}
144+
145+
return 0;
146+
}
147+
148+
int AfterResetTarget(void)
149+
{
150+
_needCoresightSetup = 1;
9151
return 0;
10152
}
11153

@@ -18,3 +160,8 @@ int SetupTarget(void)
18160

19161
return 0;
20162
}
163+
164+
int InitEMU(void) {
165+
JLINK_ExecCommand("EnableLowPowerHandlingMode");
166+
return 0;
167+
}

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