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dhower-qcayosher
dhower-qc
authored and
ayosher
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Remove extra sail() property in inst yaml (riscv-software-src#162)
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180 files changed

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‎arch/inst/A/amoadd.d.yaml‎

Lines changed: 0 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -138,95 +138,3 @@ amoadd.d:
138138
139139
140140
141-
sail(): |
142-
{
143-
if extension("A") then {
144-
/* Get the address, X(rs1) (no offset).
145-
* Some extensions perform additional checks on address validity.
146-
*/
147-
match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) {
148-
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
149-
Ext_DataAddr_OK(vaddr) => {
150-
match translateAddr(vaddr, ReadWrite(Data, Data)) {
151-
TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
152-
TR_Address(addr, _) => {
153-
let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {
154-
(BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true),
155-
(HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true),
156-
(WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true),
157-
(DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true),
158-
_ => internal_error(__FILE__, __LINE__, "Unexpected AMO width")
159-
};
160-
let is_unsigned : bool = match op {
161-
AMOMINU => true,
162-
AMOMAXU => true,
163-
_ => false
164-
};
165-
let rs2_val : xlenbits = match width {
166-
BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]),
167-
HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]),
168-
WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]),
169-
DOUBLE => X(rs2)
170-
};
171-
match (eares) {
172-
MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
173-
MemValue(_) => {
174-
let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) {
175-
(BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)),
176-
(HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)),
177-
(WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)),
178-
(DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)),
179-
_ => internal_error(__FILE__, __LINE__, "Unexpected AMO width")
180-
};
181-
match (mval) {
182-
MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
183-
MemValue(loaded) => {
184-
let result : xlenbits =
185-
match op {
186-
AMOSWAP => rs2_val,
187-
AMOADD => rs2_val + loaded,
188-
AMOXOR => rs2_val ^ loaded,
189-
AMOAND => rs2_val & loaded,
190-
AMOOR => rs2_val | loaded,
191-
192-
/* These operations convert bitvectors to integer values using [un]signed,
193-
* and back using to_bits().
194-
*/
195-
AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))),
196-
AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))),
197-
AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))),
198-
AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded)))
199-
};
200-
let rval : xlenbits = match width {
201-
BYTE => sign_extend(loaded[7..0]),
202-
HALF => sign_extend(loaded[15..0]),
203-
WORD => sign_extend(loaded[31..0]),
204-
DOUBLE => loaded
205-
};
206-
let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) {
207-
(BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true),
208-
(HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true),
209-
(WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true),
210-
(DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true),
211-
_ => internal_error(__FILE__, __LINE__, "Unexpected AMO width")
212-
};
213-
match (wval) {
214-
MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS },
215-
MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") },
216-
MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }
217-
}
218-
}
219-
}
220-
}
221-
}
222-
}
223-
}
224-
}
225-
}
226-
} else {
227-
handle_illegal();
228-
RETIRE_FAIL
229-
}
230-
}
231-
232-

‎arch/inst/A/amoadd.w.yaml‎

Lines changed: 0 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -137,95 +137,3 @@ amoadd.w:
137137
138138
139139
140-
sail(): |
141-
{
142-
if extension("A") then {
143-
/* Get the address, X(rs1) (no offset).
144-
* Some extensions perform additional checks on address validity.
145-
*/
146-
match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) {
147-
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
148-
Ext_DataAddr_OK(vaddr) => {
149-
match translateAddr(vaddr, ReadWrite(Data, Data)) {
150-
TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
151-
TR_Address(addr, _) => {
152-
let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {
153-
(BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true),
154-
(HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true),
155-
(WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true),
156-
(DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true),
157-
_ => internal_error(__FILE__, __LINE__, "Unexpected AMO width")
158-
};
159-
let is_unsigned : bool = match op {
160-
AMOMINU => true,
161-
AMOMAXU => true,
162-
_ => false
163-
};
164-
let rs2_val : xlenbits = match width {
165-
BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]),
166-
HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]),
167-
WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]),
168-
DOUBLE => X(rs2)
169-
};
170-
match (eares) {
171-
MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
172-
MemValue(_) => {
173-
let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) {
174-
(BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)),
175-
(HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)),
176-
(WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)),
177-
(DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)),
178-
_ => internal_error(__FILE__, __LINE__, "Unexpected AMO width")
179-
};
180-
match (mval) {
181-
MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
182-
MemValue(loaded) => {
183-
let result : xlenbits =
184-
match op {
185-
AMOSWAP => rs2_val,
186-
AMOADD => rs2_val + loaded,
187-
AMOXOR => rs2_val ^ loaded,
188-
AMOAND => rs2_val & loaded,
189-
AMOOR => rs2_val | loaded,
190-
191-
/* These operations convert bitvectors to integer values using [un]signed,
192-
* and back using to_bits().
193-
*/
194-
AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))),
195-
AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))),
196-
AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))),
197-
AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded)))
198-
};
199-
let rval : xlenbits = match width {
200-
BYTE => sign_extend(loaded[7..0]),
201-
HALF => sign_extend(loaded[15..0]),
202-
WORD => sign_extend(loaded[31..0]),
203-
DOUBLE => loaded
204-
};
205-
let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) {
206-
(BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true),
207-
(HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true),
208-
(WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true),
209-
(DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true),
210-
_ => internal_error(__FILE__, __LINE__, "Unexpected AMO width")
211-
};
212-
match (wval) {
213-
MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS },
214-
MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") },
215-
MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }
216-
}
217-
}
218-
}
219-
}
220-
}
221-
}
222-
}
223-
}
224-
}
225-
} else {
226-
handle_illegal();
227-
RETIRE_FAIL
228-
}
229-
}
230-
231-

‎arch/inst/A/amoand.d.yaml‎

Lines changed: 0 additions & 92 deletions
Original file line numberDiff line numberDiff line change
@@ -138,95 +138,3 @@ amoand.d:
138138
139139
140140
141-
sail(): |
142-
{
143-
if extension("A") then {
144-
/* Get the address, X(rs1) (no offset).
145-
* Some extensions perform additional checks on address validity.
146-
*/
147-
match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) {
148-
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
149-
Ext_DataAddr_OK(vaddr) => {
150-
match translateAddr(vaddr, ReadWrite(Data, Data)) {
151-
TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
152-
TR_Address(addr, _) => {
153-
let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) {
154-
(BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true),
155-
(HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true),
156-
(WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true),
157-
(DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true),
158-
_ => internal_error(__FILE__, __LINE__, "Unexpected AMO width")
159-
};
160-
let is_unsigned : bool = match op {
161-
AMOMINU => true,
162-
AMOMAXU => true,
163-
_ => false
164-
};
165-
let rs2_val : xlenbits = match width {
166-
BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]),
167-
HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]),
168-
WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]),
169-
DOUBLE => X(rs2)
170-
};
171-
match (eares) {
172-
MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
173-
MemValue(_) => {
174-
let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) {
175-
(BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)),
176-
(HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)),
177-
(WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)),
178-
(DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)),
179-
_ => internal_error(__FILE__, __LINE__, "Unexpected AMO width")
180-
};
181-
match (mval) {
182-
MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
183-
MemValue(loaded) => {
184-
let result : xlenbits =
185-
match op {
186-
AMOSWAP => rs2_val,
187-
AMOADD => rs2_val + loaded,
188-
AMOXOR => rs2_val ^ loaded,
189-
AMOAND => rs2_val & loaded,
190-
AMOOR => rs2_val | loaded,
191-
192-
/* These operations convert bitvectors to integer values using [un]signed,
193-
* and back using to_bits().
194-
*/
195-
AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))),
196-
AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))),
197-
AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))),
198-
AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded)))
199-
};
200-
let rval : xlenbits = match width {
201-
BYTE => sign_extend(loaded[7..0]),
202-
HALF => sign_extend(loaded[15..0]),
203-
WORD => sign_extend(loaded[31..0]),
204-
DOUBLE => loaded
205-
};
206-
let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) {
207-
(BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true),
208-
(HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true),
209-
(WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true),
210-
(DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true),
211-
_ => internal_error(__FILE__, __LINE__, "Unexpected AMO width")
212-
};
213-
match (wval) {
214-
MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS },
215-
MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") },
216-
MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }
217-
}
218-
}
219-
}
220-
}
221-
}
222-
}
223-
}
224-
}
225-
}
226-
} else {
227-
handle_illegal();
228-
RETIRE_FAIL
229-
}
230-
}
231-
232-

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