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[SelectionDAG] Require last operand of (STRICT_)FP_ROUND to be a TargetConstant. (llvm#117639)
Fix all the places I could find that did't do this. We were already mostly correct for FP_ROUND after 9a976f3, but not STRICT_FP_ROUND.
1 parent 6e57186 commit bc28260

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8 files changed

+51
-42
lines changed

8 files changed

+51
-42
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5277,7 +5277,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
52775277
Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
52785278
else
52795279
Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
5280-
DAG.getIntPtrConstant(0, dl));
5280+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true));
52815281
Results.push_back(Tmp1);
52825282
break;
52835283
}
@@ -5425,7 +5425,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
54255425
Tmp1 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
54265426
{Tmp3, Tmp1, Tmp2});
54275427
Tmp1 = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {OVT, MVT::Other},
5428-
{Tmp1.getValue(1), Tmp1, DAG.getIntPtrConstant(0, dl)});
5428+
{Tmp1.getValue(1), Tmp1,
5429+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)});
54295430
Results.push_back(Tmp1);
54305431
Results.push_back(Tmp1.getValue(1));
54315432
break;
@@ -5450,7 +5451,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
54505451
Tmp4 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
54515452
{Tmp4, Tmp1, Tmp2, Tmp3});
54525453
Tmp4 = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {OVT, MVT::Other},
5453-
{Tmp4.getValue(1), Tmp4, DAG.getIntPtrConstant(0, dl)});
5454+
{Tmp4.getValue(1), Tmp4,
5455+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)});
54545456
Results.push_back(Tmp4);
54555457
Results.push_back(Tmp4.getValue(1));
54565458
break;
@@ -5491,7 +5493,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
54915493
Tmp2 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
54925494
{Tmp1.getValue(1), Tmp1, Node->getOperand(2)});
54935495
Tmp3 = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {OVT, MVT::Other},
5494-
{Tmp2.getValue(1), Tmp2, DAG.getIntPtrConstant(0, dl)});
5496+
{Tmp2.getValue(1), Tmp2,
5497+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)});
54955498
Results.push_back(Tmp3);
54965499
Results.push_back(Tmp3.getValue(1));
54975500
break;
@@ -5575,7 +5578,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
55755578
Tmp2 = DAG.getNode(Node->getOpcode(), dl, {NVT, MVT::Other},
55765579
{Tmp1.getValue(1), Tmp1});
55775580
Tmp3 = DAG.getNode(ISD::STRICT_FP_ROUND, dl, {OVT, MVT::Other},
5578-
{Tmp2.getValue(1), Tmp2, DAG.getIntPtrConstant(0, dl)});
5581+
{Tmp2.getValue(1), Tmp2,
5582+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)});
55795583
Results.push_back(Tmp3);
55805584
Results.push_back(Tmp3.getValue(1));
55815585
break;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1460,7 +1460,7 @@ SelectionDAG::getStrictFPExtendOrRound(SDValue Op, SDValue Chain,
14601460
VT.bitsGT(Op.getValueType())
14611461
? getNode(ISD::STRICT_FP_EXTEND, DL, {VT, MVT::Other}, {Chain, Op})
14621462
: getNode(ISD::STRICT_FP_ROUND, DL, {VT, MVT::Other},
1463-
{Chain, Op, getIntPtrConstant(0, DL)});
1463+
{Chain, Op, getIntPtrConstant(0, DL, /*isTarget=*/true)});
14641464

14651465
return std::pair<SDValue, SDValue>(Res, SDValue(Res.getNode(), 1));
14661466
}
@@ -7355,11 +7355,10 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
73557355
return N1;
73567356
break;
73577357
case ISD::FP_ROUND:
7358-
assert(VT.isFloatingPoint() &&
7359-
N1.getValueType().isFloatingPoint() &&
7360-
VT.bitsLE(N1.getValueType()) &&
7361-
N2C && (N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
7362-
"Invalid FP_ROUND!");
7358+
assert(VT.isFloatingPoint() && N1.getValueType().isFloatingPoint() &&
7359+
VT.bitsLE(N1.getValueType()) && N2C &&
7360+
(N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
7361+
N2.getOpcode() == ISD::TargetConstant && "Invalid FP_ROUND!");
73637362
if (N1.getValueType() == VT) return N1; // noop conversion.
73647363
break;
73657364
case ISD::AssertSext:
@@ -10542,7 +10541,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
1054210541
assert(VTList.VTs[0].isFloatingPoint() &&
1054310542
Ops[1].getValueType().isFloatingPoint() &&
1054410543
VTList.VTs[0].bitsLT(Ops[1].getValueType()) &&
10545-
isa<ConstantSDNode>(Ops[2]) &&
10544+
Ops[2].getOpcode() == ISD::TargetConstant &&
1054610545
(Ops[2]->getAsZExtVal() == 0 || Ops[2]->getAsZExtVal() == 1) &&
1054710546
"Invalid STRICT_FP_ROUND!");
1054810547
break;

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 20 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -4901,13 +4901,14 @@ SDValue AArch64TargetLowering::LowerVectorINT_TO_FP(SDValue Op,
49014901
if (IsStrict) {
49024902
SDValue Val = DAG.getNode(Op.getOpcode(), dl, {F32, MVT::Other},
49034903
{Op.getOperand(0), In});
4904-
return DAG.getNode(
4905-
ISD::STRICT_FP_ROUND, dl, {Op.getValueType(), MVT::Other},
4906-
{Val.getValue(1), Val.getValue(0), DAG.getIntPtrConstant(0, dl)});
4904+
return DAG.getNode(ISD::STRICT_FP_ROUND, dl,
4905+
{Op.getValueType(), MVT::Other},
4906+
{Val.getValue(1), Val.getValue(0),
4907+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)});
49074908
}
49084909
return DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(),
49094910
DAG.getNode(Op.getOpcode(), dl, F32, In),
4910-
DAG.getIntPtrConstant(0, dl));
4911+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true));
49114912
}
49124913

49134914
uint64_t VTSize = VT.getFixedSizeInBits();
@@ -4919,9 +4920,9 @@ SDValue AArch64TargetLowering::LowerVectorINT_TO_FP(SDValue Op,
49194920
if (IsStrict) {
49204921
In = DAG.getNode(Opc, dl, {CastVT, MVT::Other},
49214922
{Op.getOperand(0), In});
4922-
return DAG.getNode(
4923-
ISD::STRICT_FP_ROUND, dl, {VT, MVT::Other},
4924-
{In.getValue(1), In.getValue(0), DAG.getIntPtrConstant(0, dl)});
4923+
return DAG.getNode(ISD::STRICT_FP_ROUND, dl, {VT, MVT::Other},
4924+
{In.getValue(1), In.getValue(0),
4925+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)});
49254926
}
49264927
In = DAG.getNode(Opc, dl, CastVT, In);
49274928
return DAG.getNode(ISD::FP_ROUND, dl, VT, In,
@@ -4969,13 +4970,14 @@ SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
49694970
if (IsStrict) {
49704971
SDValue Val = DAG.getNode(Op.getOpcode(), dl, {PromoteVT, MVT::Other},
49714972
{Op.getOperand(0), SrcVal});
4972-
return DAG.getNode(
4973-
ISD::STRICT_FP_ROUND, dl, {Op.getValueType(), MVT::Other},
4974-
{Val.getValue(1), Val.getValue(0), DAG.getIntPtrConstant(0, dl)});
4973+
return DAG.getNode(ISD::STRICT_FP_ROUND, dl,
4974+
{Op.getValueType(), MVT::Other},
4975+
{Val.getValue(1), Val.getValue(0),
4976+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)});
49754977
}
49764978
return DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(),
49774979
DAG.getNode(Op.getOpcode(), dl, PromoteVT, SrcVal),
4978-
DAG.getIntPtrConstant(0, dl));
4980+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true));
49794981
};
49804982

49814983
if (Op.getValueType() == MVT::bf16) {
@@ -5067,12 +5069,13 @@ SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
50675069
DAG.getNode(ISD::OR, DL, MVT::i64, RoundedBits, NeedsAdjustment);
50685070
SDValue Adjusted = DAG.getNode(ISD::BITCAST, DL, MVT::f64, AdjustedBits);
50695071
return IsStrict
5070-
? DAG.getNode(ISD::STRICT_FP_ROUND, DL,
5071-
{Op.getValueType(), MVT::Other},
5072-
{Rounded.getValue(1), Adjusted,
5073-
DAG.getIntPtrConstant(0, DL)})
5072+
? DAG.getNode(
5073+
ISD::STRICT_FP_ROUND, DL,
5074+
{Op.getValueType(), MVT::Other},
5075+
{Rounded.getValue(1), Adjusted,
5076+
DAG.getIntPtrConstant(0, DL, /*isTarget=*/true)})
50745077
: DAG.getNode(ISD::FP_ROUND, DL, Op.getValueType(), Adjusted,
5075-
DAG.getIntPtrConstant(0, DL, true));
5078+
DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
50765079
}
50775080
}
50785081

@@ -7109,7 +7112,7 @@ static SDValue LowerFLDEXP(SDValue Op, SelectionDAG &DAG) {
71097112
DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, X.getValueType(), FScale, Zero);
71107113
if (X.getValueType() != XScalarTy)
71117114
Final = DAG.getNode(ISD::FP_ROUND, DL, XScalarTy, Final,
7112-
DAG.getIntPtrConstant(1, SDLoc(Op)));
7115+
DAG.getIntPtrConstant(1, SDLoc(Op), /*isTarget=*/true));
71137116
return Final;
71147117
}
71157118

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10756,7 +10756,7 @@ SDValue SITargetLowering::LowerFDIV16(SDValue Op, SelectionDAG &DAG) const {
1075610756
Tmp = DAG.getNode(ISD::BITCAST, SL, MVT::f32, TmpCast);
1075710757
Quot = DAG.getNode(ISD::FADD, SL, MVT::f32, Tmp, Quot, Op->getFlags());
1075810758
SDValue RDst = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot,
10759-
DAG.getConstant(0, SL, MVT::i32));
10759+
DAG.getTargetConstant(0, SL, MVT::i32));
1076010760
return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, RDst, RHS, LHS,
1076110761
Op->getFlags());
1076210762
}

‎llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1575,9 +1575,10 @@ HexagonTargetLowering::resizeToWidth(SDValue VecV, MVT ResTy, bool Signed,
15751575
unsigned ResWidth = ResTy.getSizeInBits();
15761576

15771577
if (InpTy.isFloatingPoint()) {
1578-
return InpWidth < ResWidth ? DAG.getNode(ISD::FP_EXTEND, dl, ResTy, VecV)
1579-
: DAG.getNode(ISD::FP_ROUND, dl, ResTy, VecV,
1580-
getZero(dl, MVT::i32, DAG));
1578+
return InpWidth < ResWidth
1579+
? DAG.getNode(ISD::FP_EXTEND, dl, ResTy, VecV)
1580+
: DAG.getNode(ISD::FP_ROUND, dl, ResTy, VecV,
1581+
DAG.getTargetConstant(0, dl, MVT::i32));
15811582
}
15821583

15831584
assert(InpTy.isInteger());

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2786,7 +2786,7 @@ SDValue NVPTXTargetLowering::LowerINT_TO_FP(SDValue Op,
27862786
return DAG.getNode(
27872787
ISD::FP_ROUND, Loc, MVT::bf16,
27882788
DAG.getNode(Op.getOpcode(), Loc, MVT::f32, Op.getOperand(0)),
2789-
DAG.getIntPtrConstant(0, Loc));
2789+
DAG.getIntPtrConstant(0, Loc, /*isTarget=*/true));
27902790
}
27912791

27922792
// Everything else is considered legal.

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8963,9 +8963,10 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
89638963

89648964
if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
89658965
if (IsStrict)
8966-
FP = DAG.getNode(ISD::STRICT_FP_ROUND, dl,
8967-
DAG.getVTList(MVT::f32, MVT::Other),
8968-
{Chain, FP, DAG.getIntPtrConstant(0, dl)}, Flags);
8966+
FP = DAG.getNode(
8967+
ISD::STRICT_FP_ROUND, dl, DAG.getVTList(MVT::f32, MVT::Other),
8968+
{Chain, FP, DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)},
8969+
Flags);
89698970
else
89708971
FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
89718972
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true));
@@ -9044,9 +9045,9 @@ SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
90449045
Chain = FP.getValue(1);
90459046
if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
90469047
if (IsStrict)
9047-
FP = DAG.getNode(ISD::STRICT_FP_ROUND, dl,
9048-
DAG.getVTList(MVT::f32, MVT::Other),
9049-
{Chain, FP, DAG.getIntPtrConstant(0, dl)}, Flags);
9048+
FP = DAG.getNode(
9049+
ISD::STRICT_FP_ROUND, dl, DAG.getVTList(MVT::f32, MVT::Other),
9050+
{Chain, FP, DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)}, Flags);
90509051
else
90519052
FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
90529053
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true));

‎llvm/lib/Target/X86/X86ISelLowering.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19601,7 +19601,7 @@ static SDValue promoteXINT_TO_FP(SDValue Op, const SDLoc &dl,
1960119601
MVT VT = Op.getSimpleValueType();
1960219602
MVT NVT = VT.isVector() ? VT.changeVectorElementType(MVT::f32) : MVT::f32;
1960319603

19604-
SDValue Rnd = DAG.getIntPtrConstant(0, dl);
19604+
SDValue Rnd = DAG.getIntPtrConstant(0, dl, /*isTarget=*/true);
1960519605
if (IsStrict)
1960619606
return DAG.getNode(
1960719607
ISD::STRICT_FP_ROUND, dl, {VT, MVT::Other},
@@ -20272,7 +20272,8 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
2027220272
if (DstVT == MVT::f80)
2027320273
return Add;
2027420274
return DAG.getNode(ISD::STRICT_FP_ROUND, dl, {DstVT, MVT::Other},
20275-
{Add.getValue(1), Add, DAG.getIntPtrConstant(0, dl)});
20275+
{Add.getValue(1), Add,
20276+
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)});
2027620277
}
2027720278
unsigned Opc = ISD::FADD;
2027820279
// Windows needs the precision control changed to 80bits around this add.

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