ref(armv8-r): Update armv8-r MPU driver

miguelafsilva5 · miguelafsilva5 · commit 061deed57581 · 2025-06-11T15:52:52.000+01:00
The MPU driver for armv8-r had to be updated according to the new VMPU
implementation.

Signed-off-by: Miguel Silva &lt;miguelafsilva5@gmail.com&gt;
diff --git a/src/arch/armv8/aarch32/exceptions.S b/src/arch/armv8/aarch32/exceptions.S
@@ -50,6 +50,15 @@
     push {r0-r12}
     SAVE_ELR_SPSR
 
+    mrc p15, 4, r0, c13, c0, 2  // Read HTPIDR (CPU base address)
+    mov r1, #CPU_VCPU_OFF
+    ldr r0, [r0, r1]
+    add r0, r0, #CPU_AS_ARCH_MASK_OFF
+    mcr p15, 4, r0, c6, c1, 1 //HPRENR
+
+    //cpu.as.arch.entry_mask
+    //trocar HPRENR
+
 .endm
 
 
@@ -133,7 +142,26 @@
 
 .macro VM_ENTRY
 
+    
     mrc p15, 4, r0, c13, c0, 2  // Read HTPIDR (CPU base address)
+
+//#ifdef MEM_PROT_MPU   //0x2043a780
+    //trocar o HPRENR
+    //cpu->vcpu->vm->as.arch.entry_mask | cpu.arch.profile.mpu.locked
+    ldr r1, [r0, #CPU_VCPU_OFF]
+    mov r2, #VCPU_VM_OFF
+    add r1, r1, r2
+    ldr r1, [r1]
+    ldr r1, [r1, #VM_AS_ARCH_MASK_OFF]
+
+    mov r2, #CPU_ARCH_PROFILE_MPU_LOCKED_OFF
+    add r2, r2, r0
+    ldr r2, [r2]
+
+    orr r1, r1, r2
+    mcr p15, 4, r1, c6, c1, 1 //HPRENR
+//#endif
+
     ldr r0, [r0, #CPU_VCPU_OFF]
     add r0, r0, #VCPU_REGS_OFF
     mov sp, r0
@@ -143,6 +171,7 @@
     LOAD_SP
     pop {r14}
     
+
     eret
     b   .
 
diff --git a/src/arch/armv8/armv8-r/aarch32/boot.S b/src/arch/armv8/armv8-r/aarch32/boot.S
@@ -55,64 +55,64 @@ boot_arch_profile_init:
      * If the vm image section is used and has built-in vm images, we need to map the loadble and
      * non-loadble region of the image separately. Otherwise we can map it as a single region.
      */
-    add r4, r4, #1
-    mcr p15, 4, r4, c6, c2, 1   // HPRSELR
-    ldr r3, =_image_start
-    and r3, r3, #PRBAR_BASE_MSK
-    orr r3, r3, #PRBAR_SH_IS
-    orr r3, r3, #PRBAR_AP_RW_EL2
-    mcr p15, 4, r3, c6, c3, 0   // HPRBAR
-    ldr r10, =_image_load_end
-    ldr r11, =_image_noload_start
-    cmp r10, r11
-    ldreq r3, =_image_end
-    ldrne r3, =_image_load_end
-    sub r3, r3, #1
-    and r3, r3, #PRLAR_LIMIT_MSK
-    orr r3, r3, #(PRLAR_ATTR(1) | PRLAR_EN)
-    mcr p15, 4, r3, c6, c3, 1   // HPRLAR
+    //add r4, r4, #1
+    //mcr p15, 4, r4, c6, c2, 1   // HPRSELR
+    //ldr r3, =_image_start
+    //and r3, r3, #PRBAR_BASE_MSK
+    //orr r3, r3, #PRBAR_SH_IS
+    //orr r3, r3, #PRBAR_AP_RW_EL2
+    //mcr p15, 4, r3, c6, c3, 0   // HPRBAR
+    //ldr r10, =_image_load_end
+    //ldr r11, =_image_noload_start
+    //cmp r10, r11
+    //ldreq r3, =_image_end
+    //ldrne r3, =_image_load_end
+    //sub r3, r3, #1
+    //and r3, r3, #PRLAR_LIMIT_MSK
+    //orr r3, r3, #(PRLAR_ATTR(1) | PRLAR_EN)
+    //mcr p15, 4, r3, c6, c3, 1   // HPRLAR
 
     /* Map Image Non-loadable if needed */
-    ldr r10, =_image_load_end
-    ldr r11, =_image_noload_start
-    cmp r10, r11
-    beq skip_non_loadable
-    add r4, r4, #1
-    mcr p15, 4, r4, c6, c2, 1   // HPRSELR
-    ldr r3, =_image_noload_start
-    and r3, r3, #PRBAR_BASE_MSK
-    orr r3, r3, #PRBAR_SH_IS
-    orr r3, r3, #PRBAR_AP_RW_EL2
-    mcr p15, 4, r3, c6, c3, 0   // HPRBAR
-    ldr r3, =_image_end
-    sub r3, r3, #1
-    and r3, r3, #PRLAR_LIMIT_MSK
-    orr r3, r3, #(PRLAR_ATTR(1) | PRLAR_EN)
-    mcr p15, 4, r3, c6, c3, 1   // HPRLAR
+    //ldr r10, =_image_load_end
+    //ldr r11, =_image_noload_start
+    //cmp r10, r11
+    //beq skip_non_loadable
+    //add r4, r4, #1
+    //mcr p15, 4, r4, c6, c2, 1   // HPRSELR
+    //ldr r3, =_image_noload_start
+    //and r3, r3, #PRBAR_BASE_MSK
+    //orr r3, r3, #PRBAR_SH_IS
+    //orr r3, r3, #PRBAR_AP_RW_EL2
+    //mcr p15, 4, r3, c6, c3, 0   // HPRBAR
+    //ldr r3, =_image_end
+    //sub r3, r3, #1
+    //and r3, r3, #PRLAR_LIMIT_MSK
+    //orr r3, r3, #(PRLAR_ATTR(1) | PRLAR_EN)
+    //mcr p15, 4, r3, c6, c3, 1   // HPRLAR
 
 skip_non_loadable:
 
     /* Region 2 - CPU */
-    add r4, r4, #1
-    mcr p15, 4, r4, c6, c2, 1   // HPRSELR
-    mrc p15, 4, r3, c13, c0, 2  // HTPIDR (read CPU base addr)
-    and r3, r3, #PRBAR_BASE_MSK
-    orr r3, r3, #PRBAR_SH_IS
-    orr r3, r3, #PRBAR_AP_RW_EL2
-    mcr p15, 4, r3, c6, c3, 0   // HPRBAR
-    mrc p15, 4, r3, c13, c0, 2  // HTPIDR (read CPU base addr)
-    add r3, r3, #CPU_SIZE
-    sub r3, r3, #1
-    and r3, r3, #PRLAR_LIMIT_MSK
-    orr r3, #(PRLAR_ATTR(1) | PRLAR_EN)
-    mcr p15, 4, r3, c6, c3, 1   // HPRLAR
+    //add r4, r4, #1
+    //mcr p15, 4, r4, c6, c2, 1   // HPRSELR
+    //mrc p15, 4, r3, c13, c0, 2  // HTPIDR (read CPU base addr)
+    //and r3, r3, #PRBAR_BASE_MSK
+    //orr r3, r3, #PRBAR_SH_IS
+    //orr r3, r3, #PRBAR_AP_RW_EL2
+    //mcr p15, 4, r3, c6, c3, 0   // HPRBAR
+    //mrc p15, 4, r3, c13, c0, 2  // HTPIDR (read CPU base addr)
+    //add r3, r3, #CPU_SIZE
+    //sub r3, r3, #1
+    //and r3, r3, #PRLAR_LIMIT_MSK
+    //orr r3, #(PRLAR_ATTR(1) | PRLAR_EN)
+    //mcr p15, 4, r3, c6, c3, 1   // HPRLAR
 
     dsb
     isb
 
     /* Enable caches and MPU */
-    ldr r4, =(SCTLR_RES1_AARCH32 | SCTLR_C | SCTLR_I | SCTLR_M)
-    mcr p15, 4, r4, c1, c0, 0 // HSCTLR
+    //ldr r4, =(SCTLR_RES1_AARCH32 | SCTLR_C | SCTLR_I | SCTLR_M)
+    //mcr p15, 4, r4, c1, c0, 0 // HSCTLR
 
     dsb
     isb
diff --git a/src/arch/armv8/armv8-r/inc/arch/bao.h b/src/arch/armv8/armv8-r/inc/arch/bao.h
@@ -6,7 +6,7 @@
 #ifndef __ARCH_BAO_H__
 #define __ARCH_BAO_H__
 
-#define BAO_VAS_BASE CONFIG_HYP_BASE_ADDR
+#define BAO_VAS_BASE 0x20000000 // CONFIG_HYP_BASE_ADDR
 #define PAGE_SIZE    (64)
 #define STACK_SIZE   (0x1000)
 
diff --git a/src/arch/armv8/armv8-r/inc/arch/mem.h b/src/arch/armv8/armv8-r/inc/arch/mem.h
@@ -36,6 +36,10 @@ typedef union {
     };
 } mem_flags_t;
 
+struct addr_space_arch {
+    unsigned long entry_mask;
+};
+
 #define PTE_FLAGS(_prbar, _prlar) \
     ((mem_flags_t){               \
         .prbar = (_prbar),        \
@@ -50,7 +54,7 @@ typedef union {
 #define PTE_VM_DEV_FLAGS \
     PTE_FLAGS(PRBAR_XN | PRBAR_AP_RW_EL1_EL2 | PRBAR_SH_IS, PRLAR_ATTR(2) | PRLAR_EN)
 
-#define MPU_ARCH_MAX_NUM_ENTRIES (64)
+#define MPU_ARCH_MAX_NUM_ENTRIES 16 //(64)
 
 static inline size_t mpu_granularity(void)
 {
diff --git a/src/arch/armv8/armv8-r/inc/arch/mpu.h b/src/arch/armv8/armv8-r/inc/arch/mpu.h
@@ -9,12 +9,26 @@
 
 #include <bao.h>
 #include <arch/sysregs.h>
+#include <bitmap.h>
+#include <mem.h>
 
-void mpu_arch_init(void);
-void mpu_arch_enable(void);
-bool mpu_add_region(struct mp_region* reg, bool locked);
-bool mpu_remove_region(struct mp_region* reg);
-bool mpu_update_region(struct mp_region* reg);
+struct mpu_perms {
+    perms_t el2;
+    perms_t el1;
+};
+
+struct mpu_arch {
+    unsigned long bitmap;
+    unsigned long locked;
+
+    struct mpu_perms entry_perms[MPU_ARCH_MAX_NUM_ENTRIES];
+};
+
+// void mpu_arch_init(void);
+// void mpu_arch_enable(void);
+// bool mpu_add_region(struct mp_region* reg, bool locked);
+// bool mpu_remove_region(struct mp_region* reg);
+// bool mpu_update_region(struct mp_region* reg);
 bool mpu_perms_compatible(uint32_t perms1, uint32_t perms2);
 
-#endif /* __ARCH_MPU_H__ */
+#endif /* __ARCH_MPU_H__ */
diff --git a/src/arch/armv8/armv8-r/inc/arch/profile/cpu.h b/src/arch/armv8/armv8-r/inc/arch/profile/cpu.h
@@ -8,34 +8,14 @@
 
 #include <bao.h>
 #include <arch/sysregs.h>
+#include <arch/mpu.h>
 #include <bitmap.h>
 #include <list.h>
 #include <mem.h>
 #include <list.h>
 
 struct cpu_arch_profile {
-    struct {
-        BITMAP_ALLOC(bitmap, MPU_ARCH_MAX_NUM_ENTRIES);
-        /**
-         * A locked region means that it can never be removed from the MPU. For example,
-         */
-        BITMAP_ALLOC(locked, MPU_ARCH_MAX_NUM_ENTRIES);
-        struct mpu_perms {
-            perms_t el2;
-            perms_t el1;
-        } perms[MPU_ARCH_MAX_NUM_ENTRIES];
-        /**
-         * We maintain an ordered list of the regions currently in the mpu to simplify the merging
-         * algorithm when mapping an overllaping region.
-         */
-        struct {
-            struct list list;
-            struct mpu_node {
-                node_t node;
-                mpid_t mpid;
-            } node[MPU_ARCH_MAX_NUM_ENTRIES];
-        } order;
-    } mpu;
+    struct mpu_arch mpu;
 };
 
 static inline struct cpu* cpu(void)
diff --git a/src/arch/armv8/armv8-r/mpu.c b/src/arch/armv8/armv8-r/mpu.c
