ref: Remove unused local macros

Signed-off-by: Miguel Silva <[email protected]>

Author: miguelafsilva5

src/arch/armv8/aarch32/exceptions.S

@@ -6,8 +6,6 @@
 #include <asm_defs.h>
 #include <arch/sysregs.h>
 
-#define ENTRY_SIZE   (0x4)
-
 .text 
 
 .macro SAVE_HYP_GPRS

src/arch/riscv/iommu.c

@@ -34,15 +34,6 @@
 #define RV_IOMMU_FCTL_WSI_BIT      (0x1UL << 1)
 #define RV_IOMMU_FCTL_DEFAULT      (RV_IOMMU_FCTL_WSI_BIT)
 
-// Device Directory Table Pointer register
-#define RV_IOMMU_DDTP_MODE_OFF     (0ULL)
-#define RV_IOMMU_DDTP_MODE_BARE    (1ULL)
-#define RV_IOMMU_DDTP_MODE_1LVL    (2ULL)
-#define RV_IOMMU_DDTP_MODE_2LVL    (3ULL)
-#define RV_IOMMU_DDTP_MODE_3LVL    (4ULL)
-
-#define RV_IOMMU_DDTP_BUSY_BIT     (0x1ULL << 4)
-
 #define RV_IOMMU_DDTP_PPN_OFF      (10)
 #define RV_IOMMU_DDTP_PPN_LEN      (44)
 #define RV_IOMMU_DDTP_PPN_MASK     BIT64_MASK(RV_IOMMU_DDTP_PPN_OFF, RV_IOMMU_DDTP_PPN_LEN)
@@ -55,8 +46,6 @@
 #define RV_IOMMU_XQCSR_EN_BIT      (1ULL << 0)
 #define RV_IOMMU_XQCSR_IE_BIT      (1ULL << 1)
 #define RV_IOMMU_XQCSR_MF_BIT      (1ULL << 8)
-#define RV_IOMMU_XQCSR_ON_BIT      (1ULL << 16)
-#define RV_IOMMU_XQCSR_BUSY_BIT    (1ULL << 17)
 
 // FQ CSR
 #define RV_IOMMU_FQCSR_OF_BIT      (1ULL << 9)
@@ -120,7 +109,6 @@ struct riscv_iommu_regmap {
 
 // # RISC-V IOMMU Device Directory Table
 #define RV_IOMMU_DC_VALID_BIT       (1ULL << 0)
-#define RV_IOMMU_DC_DTF_BIT         (1ULL << 4)
 
 #define RV_IOMMU_DC_IOHGATP_PPN_OFF (0)
 #define RV_IOMMU_DC_IOHGATP_PPN_LEN (44)
@@ -131,36 +119,7 @@ struct riscv_iommu_regmap {
 #define RV_IOMMU_DC_IOHGATP_GSCID_MASK \
     BIT64_MASK(RV_IOMMU_DC_IOHGATP_GSCID_OFF, RV_IOMMU_DC_IOHGATP_GSCID_LEN)
 #define RV_IOMMU_DC_IOHGATP_MODE_OFF (60)
-#define RV_IOMMU_DC_IOHGATP_MODE_LEN (4)
-#define RV_IOMMU_DC_IOHGATP_MODE_MASK \
-    BIT64_MASK(RV_IOMMU_DC_IOHGATP_MODE_OFF, RV_IOMMU_DC_IOHGATP_MODE_LEN)
-#define RV_IOMMU_IOHGATP_SV39X4       (8ULL << RV_IOMMU_DC_IOHGATP_MODE_OFF)
-#define RV_IOMMU_IOHGATP_BARE         (0ULL << RV_IOMMU_DC_IOHGATP_MODE_OFF)
-
-#define RV_IOMMU_DC_IOHGATP_PSCID_OFF (12)
-#define RV_IOMMU_DC_IOHGATP_PSCID_LEN (20)
-#define RV_IOMMU_DC_IOHGATP_PSCID_MASK \
-    BIT64_MASK(RV_IOMMU_DC_IOHGATP_PSCID_OFF, RV_IOMMU_DC_IOHGATP_PSCID_LEN)
-
-#define RV_IOMMU_DC_FSC_PPN_OFF    (0)
-#define RV_IOMMU_DC_FSC_PPN_LEN    (44)
-#define RV_IOMMU_DC_FSC_PPN_MASK   BIT64_MASK(RV_IOMMU_DC_FSC_PPN_OFF, RV_IOMMU_DC_FSC_PPN_LEN)
-#define RV_IOMMU_DC_FSC_MODE_OFF   (60)
-#define RV_IOMMU_DC_FSC_MODE_LEN   (4)
-#define RV_IOMMU_DC_FSC_MODE_MASK  BIT64_MASK(RV_IOMMU_DC_FSC_MODE_OFF, RV_IOMMU_DC_FSC_MODE_LEN)
-
-#define RV_IOMMU_DC_MSIPTP_PPN_OFF (0)
-#define RV_IOMMU_DC_MSIPTP_PPN_LEN (44)
-#define RV_IOMMU_DC_MSIPTP_PPN_MASK \
-    BIT64_MASK(RV_IOMMU_DC_MSIPTP_PPN_OFF, RV_IOMMU_DC_MSIPTP_PPN_LEN)
-#define RV_IOMMU_DC_MSIPTP_MODE_OFF (60)
-#define RV_IOMMU_DC_MSIPTP_MODE_LEN (4)
-#define RV_IOMMU_DC_MSIPTP_MODE_MASK \
-    BIT64_MASK(RV_IOMMU_DC_MSIPTP_MODE_OFF, RV_IOMMU_DC_MSIPTP_MODE_LEN)
-
-#define RV_IOMMU_DC_MSIMASK_OFF  (0)
-#define RV_IOMMU_DC_MSIMASK_LEN  (52)
-#define RV_IOMMU_DC_MSIMASK_MASK BIT64_MASK(RV_IOMMU_DC_MSIMASK_OFF, RV_IOMMU_DC_MSIMASK_LEN)
+#define RV_IOMMU_IOHGATP_SV39X4      (8ULL << RV_IOMMU_DC_IOHGATP_MODE_OFF)
 
 struct ddt_entry {
     uint64_t tc;
@@ -176,10 +135,6 @@ struct ddt_entry {
 // # Fault Queue Record
 #define RV_IOMMU_FQ_CAUSE_OFF (0)
 #define RV_IOMMU_FQ_CAUSE_LEN (12)
-#define RV_IOMMU_FQ_PID_OFF   (12)
-#define RV_IOMMU_FQ_PID_LEN   (20)
-#define RV_IOMMU_FQ_TTYP_OFF  (34)
-#define RV_IOMMU_FQ_TTYP_LEN  (6)
 #define RV_IOMMU_FQ_DID_OFF   (40)
 #define RV_IOMMU_FQ_DID_LEN   (24)
 

src/arch/riscv/irqc/aia/aplic.c

@@ -9,19 +9,9 @@
 #include <fences.h>
 
 /** APLIC fields and masks defines */
-#define APLIC_DOMAINCFG_CTRL_MASK      (0x1FF)
-
-#define DOMAINCFG_DM                   (1U << 2)
-
-#define INTP_IDENTITY                  (16)
-#define INTP_IDENTITY_MASK             (0x3FF)
-
-#define APLIC_DISABLE_IDELIVERY        (0)
-#define APLIC_ENABLE_IDELIVERY         (1)
-#define APLIC_DISABLE_IFORCE           (0)
-#define APLIC_ENABLE_IFORCE            (1)
-#define APLIC_IDC_ITHRESHOLD_EN_ALL    (0)
-#define APLIC_IDC_ITHRESHOLD_DISBL_ALL (1)
+#define APLIC_ENABLE_IDELIVERY      (1)
+#define APLIC_DISABLE_IFORCE        (0)
+#define APLIC_IDC_ITHRESHOLD_EN_ALL (0)
 
 /** APLIC public data */
 volatile struct aplic_control_hw* aplic_control;

src/arch/riscv/irqc/aia/vaplic.c

@@ -13,7 +13,6 @@
 
 #define APLIC_MIN_PRIO             (0xFF)
 #define UPDATE_ALL_HARTS           (~0U)
-#define MASK_INTP_ZERO             (0xFFFFFFFE)
 
 #define SET_INTP_REG(reg, intp_id) (reg[intp_id / 32] = bit32_set(reg[intp_id / 32], intp_id % 32))
 #define GET_INTP_REG(reg, intp_id) ((bit32_get(reg[intp_id / 32], intp_id % 32) != 0) ? 1U : 0U)