FIX: PL011 RPi4 UART configuration

- Page alignment is required for Bao; all UARTs except for UART0 in the RPi4 are
not page aligned, thus requiring an offset. This must be defined by the
platform's user (plat/platform.h).
- UART_CLK must be overridable and defined by the platform's user (plat/platform.h): in RPi4 PL011 run at 48 MHz

Signed-off-by: ElectroQuanta <[email protected]>

CI validated

Author: ElectroQuanta

src/platform/drivers/pl011_uart/inc/drivers/pl011_uart.h

@@ -8,27 +8,34 @@
 
 #include <stdint.h>
 
+#include <plat/platform.h>
+#ifndef PL011_PAGE_OFFSET
+#define PL011_PAGE_OFFSET (0x000) /**< offset in range of 0-0xFFF */
+#endif
+
 /* UART Base Address (PL011) */
 
-#define UART_BASE_0             0xFDF02000
-#define UART_BASE_1             0xFDF00000
-#define UART_BASE_2             0xFDF03000
-#define UART_BASE_4             0xFDF01000
-#define UART_BASE_5             0xFDF05000
-#define UART_BASE_6             0xFFF32000
+#define UART_BASE_0      0xFDF02000
+#define UART_BASE_1      0xFDF00000
+#define UART_BASE_2      0xFDF03000
+#define UART_BASE_4      0xFDF01000
+#define UART_BASE_5      0xFDF05000
+#define UART_BASE_6      0xFFF32000
 
 /* UART Interrupts */
 
-#define UART_0_INTERRUPT        106
-#define UART_1_INTERRUPT        107
-#define UART_2_INTERRUPT        108
-#define UART_4_INTERRUPT        109
-#define UART_5_INTERRUPT        110
-#define UART_6_INTERRUPT        111
+#define UART_0_INTERRUPT 106
+#define UART_1_INTERRUPT 107
+#define UART_2_INTERRUPT 108
+#define UART_4_INTERRUPT 109
+#define UART_5_INTERRUPT 110
+#define UART_6_INTERRUPT 111
 
-#define NUM_UART                6
+#define NUM_UART         6
 
-#define UART_CLK                19200000
+#ifndef UART_CLK
+#define UART_CLK 19200000
+#endif
 #define UART_BAUD_RATE          115200
 
 /* UART Data Register */
@@ -177,25 +184,26 @@
 /* UART (PL011) register structure */
 
 struct Pl011_Uart_hw {
-    volatile uint32_t data;               // UART Data Register
-    volatile uint32_t status_error;       // UART Receive Status Register/Error Clear
-                                          // Register
-    const uint32_t reserved1[4];          // Reserved: 4(0x4) bytes
-    volatile uint32_t flag;               // UART Flag Register
-    const uint32_t reserved2[1];          // Reserved: 1(0x1) bytes
-    volatile uint32_t lp_counter;         // UART Low-power Counter Register
-    volatile uint32_t integer_br;         // UART Integer Baud Rate Register
-    volatile uint32_t fractional_br;      // UART Fractional Baud Rate Register
-    volatile uint32_t line_control;       // UART Line Control Register
-    volatile uint32_t control;            // UART Control Register
-    volatile uint32_t isr_fifo_level_sel; // UART Interrupt FIFO level Select
-                                          // Register
-    volatile uint32_t isr_mask;           // UART Interrupt Mask Set/Clear Register
-    volatile uint32_t raw_isr_status;     // UART Raw Interrupt Status Register
-    volatile uint32_t masked_isr_status;  // UART Masked Interrupt Status
-                                          // Register
-    volatile uint32_t isr_clear;          // UART Interrupt Clear Register
-    volatile uint32_t DMA_control;        // UART DMA control Register
+    const uint8_t offset[PL011_PAGE_OFFSET]; // Offset for page alignment
+    volatile uint32_t data;                  // UART Data Register
+    volatile uint32_t status_error;          // UART Receive Status Register/Error Clear
+                                             // Register
+    const uint32_t reserved1[4];             // Reserved: 4(0x4) bytes
+    volatile uint32_t flag;                  // UART Flag Register
+    const uint32_t reserved2[1];             // Reserved: 1(0x1) bytes
+    volatile uint32_t lp_counter;            // UART Low-power Counter Register
+    volatile uint32_t integer_br;            // UART Integer Baud Rate Register
+    volatile uint32_t fractional_br;         // UART Fractional Baud Rate Register
+    volatile uint32_t line_control;          // UART Line Control Register
+    volatile uint32_t control;               // UART Control Register
+    volatile uint32_t isr_fifo_level_sel;    // UART Interrupt FIFO level Select
+                                             // Register
+    volatile uint32_t isr_mask;              // UART Interrupt Mask Set/Clear Register
+    volatile uint32_t raw_isr_status;        // UART Raw Interrupt Status Register
+    volatile uint32_t masked_isr_status;     // UART Masked Interrupt Status
+                                             // Register
+    volatile uint32_t isr_clear;             // UART Interrupt Clear Register
+    volatile uint32_t DMA_control;           // UART DMA control Register
 };
 
 typedef struct Pl011_Uart_hw bao_uart_t;