fix(riscv): add low order bits to faulting address

josecm · danielRep · commit 9bfb8203b005 · 2024-11-04T11:16:36.000Z
Signed-off-by: Jose Martins &lt;josemartins90@gmail.com&gt;
diff --git a/src/arch/riscv/sync_exceptions.c b/src/arch/riscv/sync_exceptions.c
@@ -80,7 +80,7 @@ static inline bool is_pseudo_ins(uint32_t ins)
 
 static size_t guest_page_fault_handler(void)
 {
-    vaddr_t addr = csrs_htval_read() << 2;
+    vaddr_t addr = (csrs_htval_read() << 2) | (csrs_stval_read() & 0x3);
 
     emul_handler_t handler = vm_emul_get_mem(cpu()->vcpu->vm, addr);
     if (handler != NULL) {

Original file line number	Diff line number	Diff line change
`@@ -80,7 +80,7 @@ static inline bool is_pseudo_ins(uint32_t ins)`
`80`	`80`
`81`	`81`	`static size_t guest_page_fault_handler(void)`
`82`	`82`	`{`
`83`		`- vaddr_t addr = csrs_htval_read() << 2;`
	`83`	`+ vaddr_t addr = (csrs_htval_read() << 2) \| (csrs_stval_read() & 0x3);`
`84`	`84`
`85`	`85`	`emul_handler_t handler = vm_emul_get_mem(cpu()->vcpu->vm, addr);`
`86`	`86`	`if (handler != NULL) {`