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Commit 9e37025

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ref: fix build-riscv test issues
Signed-off-by: Manuel Rodríguez <[email protected]>
1 parent 8549433 commit 9e37025

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2 files changed

+25
-48
lines changed

2 files changed

+25
-48
lines changed

src/arch/riscv/inc/arch/iommu.h

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,4 +13,15 @@ struct iommu_vm_arch {
1313
EMPTY_STRUCT_FIELDS
1414
};
1515

16+
struct vm;
17+
void rv_iommu_fq_irq_handler(irqid_t irq_id);
18+
void alloc_2lvl_vptrs(void);
19+
void up_1lvl_to_2lvl(void);
20+
void alloc_3lvl_vptrs(void);
21+
void up_2lvl_to_3lvl(void);
22+
void ddt_init(void);
23+
void rv_iommu_init(void);
24+
bool rv_iommu_alloc_did(deviceid_t dev_id);
25+
void rv_iommu_write_ddt(deviceid_t dev_id, struct vm* vm, paddr_t root_pt);
26+
1627
#endif /* __IOMMU_ARCH_H__ */

src/arch/riscv/iommu.c

Lines changed: 14 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -30,14 +30,11 @@
3030
#define RV_IOMMU_FCTL_DEFAULT (RV_IOMMU_FCTL_WSI_BIT)
3131

3232
// Device Directory Table Pointer register
33-
#define RV_IOMMU_DDTP_MODE_OFF (0ULL)
3433
#define RV_IOMMU_DDTP_MODE_BARE (1ULL)
3534
#define RV_IOMMU_DDTP_MODE_1LVL (2ULL)
3635
#define RV_IOMMU_DDTP_MODE_2LVL (3ULL)
3736
#define RV_IOMMU_DDTP_MODE_3LVL (4ULL)
3837

39-
#define RV_IOMMU_DDTP_BUSY_BIT (0x1ULL << 4)
40-
4138
#define RV_IOMMU_DDTP_PPN_OFF (10)
4239
#define RV_IOMMU_DDTP_PPN_LEN (44)
4340
#define RV_IOMMU_DDTP_PPN_MASK BIT64_MASK(RV_IOMMU_DDTP_PPN_OFF, RV_IOMMU_DDTP_PPN_LEN)
@@ -50,8 +47,6 @@
5047
#define RV_IOMMU_XQCSR_EN_BIT (1ULL << 0)
5148
#define RV_IOMMU_XQCSR_IE_BIT (1ULL << 1)
5249
#define RV_IOMMU_XQCSR_MF_BIT (1ULL << 8)
53-
#define RV_IOMMU_XQCSR_ON_BIT (1ULL << 16)
54-
#define RV_IOMMU_XQCSR_BUSY_BIT (1ULL << 17)
5550

5651
// FQ CSR
5752
#define RV_IOMMU_FQCSR_OF_BIT (1ULL << 9)
@@ -137,7 +132,6 @@ struct riscv_iommu_regmap {
137132

138133
// Leaf
139134
#define RV_IOMMU_DC_VALID_BIT (1ULL << 0)
140-
#define RV_IOMMU_DC_DTF_BIT (1ULL << 4)
141135

142136
#define RV_IOMMU_DC_IOHGATP_PPN_OFF (0)
143137
#define RV_IOMMU_DC_IOHGATP_PPN_LEN (44)
@@ -148,36 +142,7 @@ struct riscv_iommu_regmap {
148142
#define RV_IOMMU_DC_IOHGATP_GSCID_MASK \
149143
BIT64_MASK(RV_IOMMU_DC_IOHGATP_GSCID_OFF, RV_IOMMU_DC_IOHGATP_GSCID_LEN)
150144
#define RV_IOMMU_DC_IOHGATP_MODE_OFF (60)
151-
#define RV_IOMMU_DC_IOHGATP_MODE_LEN (4)
152-
#define RV_IOMMU_DC_IOHGATP_MODE_MASK \
153-
BIT64_MASK(RV_IOMMU_DC_IOHGATP_MODE_OFF, RV_IOMMU_DC_IOHGATP_MODE_LEN)
154-
#define RV_IOMMU_IOHGATP_SV39X4 (8ULL << RV_IOMMU_DC_IOHGATP_MODE_OFF)
155-
#define RV_IOMMU_IOHGATP_BARE (0ULL << RV_IOMMU_DC_IOHGATP_MODE_OFF)
156-
157-
#define RV_IOMMU_DC_IOHGATP_PSCID_OFF (12)
158-
#define RV_IOMMU_DC_IOHGATP_PSCID_LEN (20)
159-
#define RV_IOMMU_DC_IOHGATP_PSCID_MASK \
160-
BIT64_MASK(RV_IOMMU_DC_IOHGATP_PSCID_OFF, RV_IOMMU_DC_IOHGATP_PSCID_LEN)
161-
162-
#define RV_IOMMU_DC_FSC_PPN_OFF (0)
163-
#define RV_IOMMU_DC_FSC_PPN_LEN (44)
164-
#define RV_IOMMU_DC_FSC_PPN_MASK BIT64_MASK(RV_IOMMU_DC_FSC_PPN_OFF, RV_IOMMU_DC_FSC_PPN_LEN)
165-
#define RV_IOMMU_DC_FSC_MODE_OFF (60)
166-
#define RV_IOMMU_DC_FSC_MODE_LEN (4)
167-
#define RV_IOMMU_DC_FSC_MODE_MASK BIT64_MASK(RV_IOMMU_DC_FSC_MODE_OFF, RV_IOMMU_DC_FSC_MODE_LEN)
168-
169-
#define RV_IOMMU_DC_MSIPTP_PPN_OFF (0)
170-
#define RV_IOMMU_DC_MSIPTP_PPN_LEN (44)
171-
#define RV_IOMMU_DC_MSIPTP_PPN_MASK \
172-
BIT64_MASK(RV_IOMMU_DC_MSIPTP_PPN_OFF, RV_IOMMU_DC_MSIPTP_PPN_LEN)
173-
#define RV_IOMMU_DC_MSIPTP_MODE_OFF (60)
174-
#define RV_IOMMU_DC_MSIPTP_MODE_LEN (4)
175-
#define RV_IOMMU_DC_MSIPTP_MODE_MASK \
176-
BIT64_MASK(RV_IOMMU_DC_MSIPTP_MODE_OFF, RV_IOMMU_DC_MSIPTP_MODE_LEN)
177-
178-
#define RV_IOMMU_DC_MSIMASK_OFF (0)
179-
#define RV_IOMMU_DC_MSIMASK_LEN (52)
180-
#define RV_IOMMU_DC_MSIMASK_MASK BIT64_MASK(RV_IOMMU_DC_MSIMASK_OFF, RV_IOMMU_DC_MSIMASK_LEN)
145+
#define RV_IOMMU_IOHGATP_SV39X4 (8ULL << RV_IOMMU_DC_IOHGATP_MODE_OFF)
181146

182147
typedef uint64_t* ddt_bitmap_t;
183148

@@ -200,10 +165,6 @@ struct ddt_entry {
200165
// # Fault Queue
201166
#define RV_IOMMU_FQ_CAUSE_OFF (0)
202167
#define RV_IOMMU_FQ_CAUSE_LEN (12)
203-
#define RV_IOMMU_FQ_PID_OFF (12)
204-
#define RV_IOMMU_FQ_PID_LEN (20)
205-
#define RV_IOMMU_FQ_TTYP_OFF (34)
206-
#define RV_IOMMU_FQ_TTYP_LEN (6)
207168
#define RV_IOMMU_FQ_DID_OFF (40)
208169
#define RV_IOMMU_FQ_DID_LEN (24)
209170

@@ -248,7 +209,7 @@ struct riscv_iommu_priv rv_iommu;
248209
*/
249210
static void rv_iommu_check_features(void)
250211
{
251-
unsigned version =
212+
uint64_t version =
252213
bit64_extract(rv_iommu.caps, RV_IOMMU_CAPS_VERSION_OFF, RV_IOMMU_CAPS_VERSION_LEN);
253214

254215
if (version != RV_IOMMU_SUPPORTED_VERSION) {
@@ -259,7 +220,7 @@ static void rv_iommu_check_features(void)
259220
ERROR("RV IOMMU: Sv39x4 not supported");
260221
}
261222

262-
unsigned igs = bit64_extract(rv_iommu.caps, RV_IOMMU_CAPS_IGS_OFF, RV_IOMMU_CAPS_IGS_LEN);
223+
uint64_t igs = bit64_extract(rv_iommu.caps, RV_IOMMU_CAPS_IGS_OFF, RV_IOMMU_CAPS_IGS_LEN);
263224
if (!igs) {
264225
WARNING("RV IOMMU: WSI generation not supported. MSI generation is currently not supported "
265226
"by Bao");
@@ -271,6 +232,8 @@ static void rv_iommu_check_features(void)
271232
*/
272233
void rv_iommu_fq_irq_handler(irqid_t irq_id)
273234
{
235+
UNUSED_ARG(irq_id);
236+
274237
// Read ipsr.fip
275238
uint32_t ipsr = rv_iommu.hw.reg_ptr->ipsr;
276239

@@ -449,7 +412,7 @@ void ddt_init(void)
449412
uint64_t ddtp_readback = rv_iommu.hw.reg_ptr->ddtp;
450413

451414
if (ddtp_readback == ddtp_mode) {
452-
rv_iommu.supported_modes |= (1 << (i + 2));
415+
rv_iommu.supported_modes |= (uint8_t)(1 << (i + 2));
453416
if (first) {
454417
first = false;
455418
simplest_mode = ddtp_mode; // save simplest mode
@@ -704,16 +667,16 @@ void rv_iommu_write_ddt(deviceid_t dev_id, struct vm* vm, paddr_t root_pt)
704667
/*** Write DC ***/
705668

706669
// Get DC pointer
707-
struct ddt_entry* dc_ptr = NULL;
670+
volatile struct ddt_entry* dc_ptr = NULL;
708671
switch (rv_iommu.iommu_mode) {
709672
case RV_IOMMU_DDTP_MODE_3LVL:
710-
dc_ptr = (struct ddt_entry*)(rv_iommu.hw.vddt_lvl2[ddi_2][ddi_1]);
673+
dc_ptr = (volatile struct ddt_entry*)(rv_iommu.hw.vddt_lvl2[ddi_2][ddi_1]);
711674
break;
712675
case RV_IOMMU_DDTP_MODE_2LVL:
713-
dc_ptr = (struct ddt_entry*)(rv_iommu.hw.vddt_lvl1[ddi_1]);
676+
dc_ptr = (volatile struct ddt_entry*)(rv_iommu.hw.vddt_lvl1[ddi_1]);
714677
break;
715678
case RV_IOMMU_DDTP_MODE_1LVL:
716-
dc_ptr = (struct ddt_entry*)rv_iommu.hw.vddt_lvl0;
679+
dc_ptr = (volatile struct ddt_entry*)rv_iommu.hw.vddt_lvl0;
717680
break;
718681

719682
default:
@@ -850,8 +813,11 @@ inline bool iommu_arch_vm_add_device(struct vm* vm, deviceid_t dev_id)
850813
*
851814
* @returns true on success, false on error.
852815
*/
853-
bool iommu_arch_vm_init(struct vm* vm, const struct vm_config* config)
816+
bool iommu_arch_vm_init(struct vm* vm, const struct vm_config* vm_config)
854817
{
818+
UNUSED_ARG(vm);
819+
UNUSED_ARG(vm_config);
820+
855821
// For now there is no data to initialize
856822
return true;
857823
}

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